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// Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// e32\nkern\x86\vectors.cpp
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//
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//
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// NThreadBase member data
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#define __INCLUDE_NTHREADBASE_DEFINES__
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#include <x86.h>
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#include "vectors.h"
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#ifdef _DEBUG
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#define __CHECK_LOCK_STATE__
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#endif
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void __X86VectorIrq();
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void __X86VectorExc();
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void __X86ExcFault(TAny*);
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/** Register the global IRQ handler
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Called by the base port at boot time to bind the top level IRQ dispatcher
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to the X86 common IRQ handler. Should not be called at any other time.
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The handler specified will be called with IRQs disabled. ESP will point
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to the top of the interrupt stack. On entry to the handler EAX will point
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to a block of saved registers, as follows:
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[EAX+00h] = saved EDX
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[EAX+04h] = saved ECX
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[EAX+08h] = saved EAX
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[EAX+0Ch] = saved ES
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[EAX+10h] = saved DS
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[EAX+14h] = interrupt vector number
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[EAX+18h] = return EIP
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[EAX+1Ch] = return CS
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[EAX+20h] = return EFLAGS
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[EAX+24h] = return ESP if interrupt occurred while CPL>0
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[EAX+28h] = return SS if interrupt occurred while CPL>0
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The handler should preserve all registers other than EAX, ECX, EDX
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and should return using a standard RET instruction.
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@param aHandler The address of the top level IRQ dispatcher routine
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*/
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EXPORT_C void X86::SetIrqHandler(TLinAddr aHandler)
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{
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X86_IrqHandler=aHandler;
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}
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/** Return the address immediately after the end of the interrupt stack.
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@return Interrupt Stack Base + Interrupt Stack Size
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*/
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EXPORT_C TLinAddr X86::IrqStackTop(TInt /*aCpu*/)
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{
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return TLinAddr(X86_IrqStack) + IRQ_STACK_SIZE;
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}
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void SetTrapGate(SX86Des* aEntry, PFV aHandler, TInt aDPL)
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{
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aEntry->iLow=(KRing0CS<<16)|(TUint32(aHandler)&0xffff);
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aEntry->iHigh=(TUint32(aHandler)&0xffff0000) | 0x8f00 | (aDPL<<13);
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}
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void SetInterruptGate(SX86Des* aEntry, PFV aHandler, TInt aDPL)
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{
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aEntry->iLow=(KRing0CS<<16)|(TUint32(aHandler)&0xffff);
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aEntry->iHigh=(TUint32(aHandler)&0xffff0000) | 0x8e00 | (aDPL<<13);
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}
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void SetTssDescriptor(SX86Des* aEntry, TX86Tss* aTss)
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{
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TUint addr3=TUint(aTss)>>24;
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TUint addr2=(TUint(aTss)>>16)&0xff;
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TUint addr01=TUint(aTss)&0xffff;
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aEntry->iLow=(addr01<<16)|(sizeof(TX86Tss)-1);
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aEntry->iHigh=(addr3<<24)|0x00108900|addr2;
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}
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void X86::Init1Interrupts()
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//
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// Initialise the interrupt and exception vector handlers.
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//
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{
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// TheIrqHandler=0; // done by placing TheIrqHandler, TheFiqHandler in .bss
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__KTRACE_OPT(KBOOT,DEBUGPRINT(">X86::Init1Interrupts()"));
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memset(X86_IrqStack,0xaa,IRQ_STACK_SIZE);
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#ifndef __STANDALONE_NANOKERNEL__
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TStackInfo& stackInfo = TheSuperPage().iStackInfo;
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stackInfo.iIrqStackBase = X86_IrqStack;
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stackInfo.iIrqStackSize = IRQ_STACK_SIZE;
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#endif
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TCpuPage& cp=X86::CpuPage();
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memclr(cp.iIdt, KIdtSize*sizeof(SX86Des));
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TInt i;
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for (i=0; i<64; i++)
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{
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if (i==0x03 || i==0x20 || i==0x21)
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SetTrapGate(cp.iIdt+i, TheExcVectors[i], 3);
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else if (i<0x20)
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SetTrapGate(cp.iIdt+i, TheExcVectors[i], 0);
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if (i>=0x30)
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SetInterruptGate(cp.iIdt+i, TheExcVectors[i], 0);
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}
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X86_IrqNestCount=-1;
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X86::DefaultCR0=get_cr0();
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memclr(&cp.iTss,sizeof(TX86Tss));
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cp.iTss.iCR3=get_cr3();
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cp.iTss.iSs0=KRing0DS;
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cp.iTss.iEsp0=get_esp();
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SetTssDescriptor(&cp.iGdt[5],&cp.iTss);
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X86_TSS_Ptr=&cp.iTss;
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__lidt(cp.iIdt,KIdtSize);
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__KTRACE_OPT(KBOOT,DEBUGPRINT("<X86::Init1Interrupts()"));
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}
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/** Return the current processor context type (thread, IDFC or interrupt)
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@return A value from NKern::TContext enumeration (but never EEscaped)
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@pre Any context
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@see NKern::TContext
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*/
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EXPORT_C TInt NKern::CurrentContext()
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{
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if (X86_IrqNestCount >= 0)
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return NKern::EInterrupt;
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if (TheScheduler.iInIDFC)
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return NKern::EIDFC;
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return NKern::EThread;
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}
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extern "C" void ExcFault(TAny*);
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void __X86ExcFault(TAny* aInfo)
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{
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ExcFault(aInfo);
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}
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