1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/kernel/eka/nkern/x86/vectors.cpp Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,156 @@
1.4 +// Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// e32\nkern\x86\vectors.cpp
1.18 +//
1.19 +//
1.20 +
1.21 +// NThreadBase member data
1.22 +#define __INCLUDE_NTHREADBASE_DEFINES__
1.23 +
1.24 +#include <x86.h>
1.25 +#include "vectors.h"
1.26 +
1.27 +#ifdef _DEBUG
1.28 +#define __CHECK_LOCK_STATE__
1.29 +#endif
1.30 +
1.31 +void __X86VectorIrq();
1.32 +void __X86VectorExc();
1.33 +void __X86ExcFault(TAny*);
1.34 +
1.35 +
1.36 +/** Register the global IRQ handler
1.37 + Called by the base port at boot time to bind the top level IRQ dispatcher
1.38 + to the X86 common IRQ handler. Should not be called at any other time.
1.39 +
1.40 + The handler specified will be called with IRQs disabled. ESP will point
1.41 + to the top of the interrupt stack. On entry to the handler EAX will point
1.42 + to a block of saved registers, as follows:
1.43 +
1.44 + [EAX+00h] = saved EDX
1.45 + [EAX+04h] = saved ECX
1.46 + [EAX+08h] = saved EAX
1.47 + [EAX+0Ch] = saved ES
1.48 + [EAX+10h] = saved DS
1.49 + [EAX+14h] = interrupt vector number
1.50 + [EAX+18h] = return EIP
1.51 + [EAX+1Ch] = return CS
1.52 + [EAX+20h] = return EFLAGS
1.53 + [EAX+24h] = return ESP if interrupt occurred while CPL>0
1.54 + [EAX+28h] = return SS if interrupt occurred while CPL>0
1.55 +
1.56 + The handler should preserve all registers other than EAX, ECX, EDX
1.57 + and should return using a standard RET instruction.
1.58 +
1.59 + @param aHandler The address of the top level IRQ dispatcher routine
1.60 + */
1.61 +EXPORT_C void X86::SetIrqHandler(TLinAddr aHandler)
1.62 + {
1.63 + X86_IrqHandler=aHandler;
1.64 + }
1.65 +
1.66 +
1.67 +/** Return the address immediately after the end of the interrupt stack.
1.68 +
1.69 + @return Interrupt Stack Base + Interrupt Stack Size
1.70 + */
1.71 +EXPORT_C TLinAddr X86::IrqStackTop(TInt /*aCpu*/)
1.72 + {
1.73 + return TLinAddr(X86_IrqStack) + IRQ_STACK_SIZE;
1.74 + }
1.75 +
1.76 +
1.77 +void SetTrapGate(SX86Des* aEntry, PFV aHandler, TInt aDPL)
1.78 + {
1.79 + aEntry->iLow=(KRing0CS<<16)|(TUint32(aHandler)&0xffff);
1.80 + aEntry->iHigh=(TUint32(aHandler)&0xffff0000) | 0x8f00 | (aDPL<<13);
1.81 + }
1.82 +
1.83 +void SetInterruptGate(SX86Des* aEntry, PFV aHandler, TInt aDPL)
1.84 + {
1.85 + aEntry->iLow=(KRing0CS<<16)|(TUint32(aHandler)&0xffff);
1.86 + aEntry->iHigh=(TUint32(aHandler)&0xffff0000) | 0x8e00 | (aDPL<<13);
1.87 + }
1.88 +
1.89 +void SetTssDescriptor(SX86Des* aEntry, TX86Tss* aTss)
1.90 + {
1.91 + TUint addr3=TUint(aTss)>>24;
1.92 + TUint addr2=(TUint(aTss)>>16)&0xff;
1.93 + TUint addr01=TUint(aTss)&0xffff;
1.94 + aEntry->iLow=(addr01<<16)|(sizeof(TX86Tss)-1);
1.95 + aEntry->iHigh=(addr3<<24)|0x00108900|addr2;
1.96 + }
1.97 +
1.98 +void X86::Init1Interrupts()
1.99 +//
1.100 +// Initialise the interrupt and exception vector handlers.
1.101 +//
1.102 + {
1.103 +// TheIrqHandler=0; // done by placing TheIrqHandler, TheFiqHandler in .bss
1.104 + __KTRACE_OPT(KBOOT,DEBUGPRINT(">X86::Init1Interrupts()"));
1.105 + memset(X86_IrqStack,0xaa,IRQ_STACK_SIZE);
1.106 +
1.107 +#ifndef __STANDALONE_NANOKERNEL__
1.108 + TStackInfo& stackInfo = TheSuperPage().iStackInfo;
1.109 + stackInfo.iIrqStackBase = X86_IrqStack;
1.110 + stackInfo.iIrqStackSize = IRQ_STACK_SIZE;
1.111 +#endif
1.112 +
1.113 + TCpuPage& cp=X86::CpuPage();
1.114 + memclr(cp.iIdt, KIdtSize*sizeof(SX86Des));
1.115 + TInt i;
1.116 + for (i=0; i<64; i++)
1.117 + {
1.118 + if (i==0x03 || i==0x20 || i==0x21)
1.119 + SetTrapGate(cp.iIdt+i, TheExcVectors[i], 3);
1.120 + else if (i<0x20)
1.121 + SetTrapGate(cp.iIdt+i, TheExcVectors[i], 0);
1.122 + if (i>=0x30)
1.123 + SetInterruptGate(cp.iIdt+i, TheExcVectors[i], 0);
1.124 + }
1.125 + X86_IrqNestCount=-1;
1.126 + X86::DefaultCR0=get_cr0();
1.127 + memclr(&cp.iTss,sizeof(TX86Tss));
1.128 + cp.iTss.iCR3=get_cr3();
1.129 + cp.iTss.iSs0=KRing0DS;
1.130 + cp.iTss.iEsp0=get_esp();
1.131 + SetTssDescriptor(&cp.iGdt[5],&cp.iTss);
1.132 + X86_TSS_Ptr=&cp.iTss;
1.133 + __lidt(cp.iIdt,KIdtSize);
1.134 + __KTRACE_OPT(KBOOT,DEBUGPRINT("<X86::Init1Interrupts()"));
1.135 + }
1.136 +
1.137 +
1.138 +/** Return the current processor context type (thread, IDFC or interrupt)
1.139 +
1.140 + @return A value from NKern::TContext enumeration (but never EEscaped)
1.141 + @pre Any context
1.142 +
1.143 + @see NKern::TContext
1.144 + */
1.145 +EXPORT_C TInt NKern::CurrentContext()
1.146 + {
1.147 + if (X86_IrqNestCount >= 0)
1.148 + return NKern::EInterrupt;
1.149 + if (TheScheduler.iInIDFC)
1.150 + return NKern::EIDFC;
1.151 + return NKern::EThread;
1.152 + }
1.153 +
1.154 +extern "C" void ExcFault(TAny*);
1.155 +void __X86ExcFault(TAny* aInfo)
1.156 + {
1.157 + ExcFault(aInfo);
1.158 + }
1.159 +