sl@0: // Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
sl@0: // All rights reserved.
sl@0: // This component and the accompanying materials are made available
sl@0: // under the terms of the License "Eclipse Public License v1.0"
sl@0: // which accompanies this distribution, and is available
sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
sl@0: //
sl@0: // Initial Contributors:
sl@0: // Nokia Corporation - initial contribution.
sl@0: //
sl@0: // Contributors:
sl@0: //
sl@0: // Description:
sl@0: // e32\nkern\x86\vectors.cpp
sl@0: // 
sl@0: //
sl@0: 
sl@0: // NThreadBase member data
sl@0: #define __INCLUDE_NTHREADBASE_DEFINES__
sl@0: 
sl@0: #include <x86.h>
sl@0: #include "vectors.h"
sl@0: 
sl@0: #ifdef _DEBUG
sl@0: #define __CHECK_LOCK_STATE__
sl@0: #endif
sl@0: 
sl@0: void __X86VectorIrq();
sl@0: void __X86VectorExc();
sl@0: void __X86ExcFault(TAny*);
sl@0: 
sl@0: 
sl@0: /** Register the global IRQ handler
sl@0: 	Called by the base port at boot time to bind the top level IRQ dispatcher
sl@0: 	to the X86 common IRQ handler. Should not be called at any other time.
sl@0: 
sl@0: 	The handler specified will be called with IRQs disabled. ESP will point
sl@0: 	to the top of the interrupt stack. On entry to the handler EAX will point
sl@0: 	to a block of saved registers, as follows:
sl@0: 
sl@0: 	[EAX+00h] = saved EDX
sl@0: 	[EAX+04h] = saved ECX
sl@0: 	[EAX+08h] = saved EAX
sl@0: 	[EAX+0Ch] = saved ES
sl@0: 	[EAX+10h] = saved DS
sl@0: 	[EAX+14h] = interrupt vector number
sl@0: 	[EAX+18h] = return EIP
sl@0: 	[EAX+1Ch] = return CS
sl@0: 	[EAX+20h] = return EFLAGS
sl@0: 	[EAX+24h] = return ESP if interrupt occurred while CPL>0
sl@0: 	[EAX+28h] = return SS if interrupt occurred while CPL>0
sl@0: 
sl@0: 	The handler should preserve all registers other than EAX, ECX, EDX
sl@0: 	and should return using a standard RET instruction.
sl@0: 
sl@0: 	@param	aHandler The address of the top level IRQ dispatcher routine
sl@0:  */
sl@0: EXPORT_C void X86::SetIrqHandler(TLinAddr aHandler)
sl@0: 	{
sl@0: 	X86_IrqHandler=aHandler;
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /** Return the address immediately after the end of the interrupt stack.
sl@0: 
sl@0: 	@return Interrupt Stack Base + Interrupt Stack Size
sl@0:  */
sl@0: EXPORT_C TLinAddr X86::IrqStackTop(TInt /*aCpu*/)
sl@0: 	{
sl@0: 	return TLinAddr(X86_IrqStack) + IRQ_STACK_SIZE;
sl@0: 	}
sl@0: 
sl@0: 
sl@0: void SetTrapGate(SX86Des* aEntry, PFV aHandler, TInt aDPL)
sl@0: 	{
sl@0: 	aEntry->iLow=(KRing0CS<<16)|(TUint32(aHandler)&0xffff);
sl@0: 	aEntry->iHigh=(TUint32(aHandler)&0xffff0000) | 0x8f00 | (aDPL<<13);
sl@0: 	}
sl@0: 
sl@0: void SetInterruptGate(SX86Des* aEntry, PFV aHandler, TInt aDPL)
sl@0: 	{
sl@0: 	aEntry->iLow=(KRing0CS<<16)|(TUint32(aHandler)&0xffff);
sl@0: 	aEntry->iHigh=(TUint32(aHandler)&0xffff0000) | 0x8e00 | (aDPL<<13);
sl@0: 	}
sl@0: 
sl@0: void SetTssDescriptor(SX86Des* aEntry, TX86Tss* aTss)
sl@0: 	{
sl@0: 	TUint addr3=TUint(aTss)>>24;
sl@0: 	TUint addr2=(TUint(aTss)>>16)&0xff;
sl@0: 	TUint addr01=TUint(aTss)&0xffff;
sl@0: 	aEntry->iLow=(addr01<<16)|(sizeof(TX86Tss)-1);
sl@0: 	aEntry->iHigh=(addr3<<24)|0x00108900|addr2;
sl@0: 	}
sl@0: 
sl@0: void X86::Init1Interrupts()
sl@0: //
sl@0: // Initialise the interrupt and exception vector handlers.
sl@0: //
sl@0: 	{
sl@0: //	TheIrqHandler=0;	// done by placing TheIrqHandler, TheFiqHandler in .bss
sl@0: 	__KTRACE_OPT(KBOOT,DEBUGPRINT(">X86::Init1Interrupts()"));
sl@0: 	memset(X86_IrqStack,0xaa,IRQ_STACK_SIZE);
sl@0: 
sl@0: #ifndef __STANDALONE_NANOKERNEL__
sl@0: 	TStackInfo& stackInfo =  TheSuperPage().iStackInfo;
sl@0: 	stackInfo.iIrqStackBase = X86_IrqStack;
sl@0: 	stackInfo.iIrqStackSize = IRQ_STACK_SIZE;
sl@0: #endif
sl@0: 	
sl@0: 	TCpuPage& cp=X86::CpuPage();
sl@0: 	memclr(cp.iIdt, KIdtSize*sizeof(SX86Des));
sl@0: 	TInt i;
sl@0: 	for (i=0; i<64; i++)
sl@0: 		{
sl@0: 		if (i==0x03 || i==0x20 || i==0x21)
sl@0: 			SetTrapGate(cp.iIdt+i, TheExcVectors[i], 3);
sl@0: 		else if (i<0x20)
sl@0: 			SetTrapGate(cp.iIdt+i, TheExcVectors[i], 0);
sl@0: 		if (i>=0x30)
sl@0: 			SetInterruptGate(cp.iIdt+i, TheExcVectors[i], 0);
sl@0: 		}
sl@0: 	X86_IrqNestCount=-1;
sl@0: 	X86::DefaultCR0=get_cr0();
sl@0: 	memclr(&cp.iTss,sizeof(TX86Tss));
sl@0: 	cp.iTss.iCR3=get_cr3();
sl@0: 	cp.iTss.iSs0=KRing0DS;
sl@0: 	cp.iTss.iEsp0=get_esp();
sl@0: 	SetTssDescriptor(&cp.iGdt[5],&cp.iTss);
sl@0: 	X86_TSS_Ptr=&cp.iTss;
sl@0: 	__lidt(cp.iIdt,KIdtSize);
sl@0: 	__KTRACE_OPT(KBOOT,DEBUGPRINT("<X86::Init1Interrupts()"));
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /**	Return the current processor context type (thread, IDFC or interrupt)
sl@0: 
sl@0: 	@return	A value from NKern::TContext enumeration (but never EEscaped)
sl@0: 	@pre	Any context
sl@0: 
sl@0: 	@see	NKern::TContext
sl@0:  */
sl@0: EXPORT_C TInt NKern::CurrentContext()
sl@0: 	{
sl@0: 	if (X86_IrqNestCount >= 0)
sl@0: 		return NKern::EInterrupt;
sl@0: 	if (TheScheduler.iInIDFC)
sl@0: 		return NKern::EIDFC;
sl@0: 	return NKern::EThread;
sl@0: 	}
sl@0: 
sl@0: extern "C" void ExcFault(TAny*);
sl@0: void __X86ExcFault(TAny* aInfo)
sl@0: 	{
sl@0: 	ExcFault(aInfo);
sl@0: 	}
sl@0: