test: epoc32/include/assp/omap3530_assp/omap3530_hardware

     1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).

     2 // All rights reserved.

     3 // This component and the accompanying materials are made available

     4 // under the terms of the License "Eclipse Public License v1.0"

     5 // which accompanies this distribution, and is available

     6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".

     7 //

     8 // Initial Contributors:

     9 // Nokia Corporation - initial contribution.

    10 //

    11 // Contributors:

    12 //

    13 // Description:

    14 // omap3530/assp/inc/omap3530_hardware_base.h

    15 // Linear base addresses for hardware peripherals on the beagle board.

    16 // This file is part of the Beagle Base port

    17 //

    19 #ifndef OMAP3530_HARDWARE_BASE_H__

    20 #	define OMAP3530_HARDWARE_BASE_H__

    22 #include <assp.h> // for TPhysAddr, AsspRegister

    23 #include <assp/omap3530_assp/omap3530_asspreg.h>

    25 namespace TexasInstruments

    26 	{

    28 	namespace Omap3530

    29 		{

    31 		/**

    32 		Define constants for the various physical address blocks used on the OMAP3530

    33 		*/

    34 		enum TPhysicalAddresses

    35 			{

    36 			KKiloByte				=	1024,

    37 			KMegaByte				=	(1024 * KKiloByte),

    38 			KL4_Core_PhysicalBase	=	0x48000000,

    39 			KL4_Core_PhysicalSize	=	(4 * KMegaByte),

    40 			KL4_Core_PhysicalEnd	=	(KL4_Core_PhysicalBase + KL4_Core_PhysicalSize),

    42 			KL4_WakeUp_PhysicalBase	=	0x48300000,

    43 			KL4_WakeUp_PhysicalSize	=	(256 * KKiloByte ),

    44 			KL4_WakeUp_PhysicalEnd	=	(KL4_WakeUp_PhysicalBase + KL4_WakeUp_PhysicalSize),

    46 			KL4_Per_PhysicalBase	=	0x49000000,

    47 			KL4_Per_PhysicalSize	=	(1 * KMegaByte),

    48 			KL4_Per_PhysicalEnd		=	(KL4_Per_PhysicalBase + KL4_Per_PhysicalSize),

    50 			KL4_Sgx_PhysicalBase	=	0x50000000,

    51 			KL4_Sgx_PhysicalSize	=	(64 * KKiloByte),

    52 			KL4_Sgx_PhysicalEnd		=	(KL4_Sgx_PhysicalBase + KL4_Sgx_PhysicalSize),

    54 			KL4_Emu_PhysicalBase	=	0x54000000,

    55 			KL4_Emu_PhysicalSize	=	(8 * KMegaByte),

    56 			KL4_Emu_PhysicalEnd		=	(KL4_Emu_PhysicalBase + KL4_Emu_PhysicalSize),

    58 			KL3_Control_PhysicalBase	=	0x68000000,

    59 			KL3_Control_PhysicalSize	=	(1 * KMegaByte),

    60 			KL3_Control_PhysicalEnd		=	(KL3_Control_PhysicalBase + KL3_Control_PhysicalSize),

    62 			KL3_Gpmc_PhysicalBase		=	0x6e000000,

    63 			KL3_Gpmc_PhysicalSize		=	(1 * KMegaByte),

    64 			KL3_Gpmc_PhysicalEnd		=	(KL3_Gpmc_PhysicalBase + KL3_Gpmc_PhysicalSize)

    65 			} ;

    67 		/**

    68 		Define constants for the virtual address mappings used on the OMAP3530

    69 		*/

    70 		enum TLinearAddresses

    71 			{

    72 			KL4_Core_LinearBase		=	0xC6000000,

    73 			KL4_Core_LinearSize		=	KL4_Core_PhysicalSize,

    74 			KL4_Core_LinearEnd		=	(KL4_Core_LinearBase + KL4_Core_LinearSize),

    76 			KL4_WakeUp_LinearBase	=	(KL4_Core_LinearBase + (KL4_WakeUp_PhysicalBase - KL4_Core_PhysicalBase)),

    77 			KL4_WakeUp_LinearSize	=	KL4_WakeUp_PhysicalSize,

    78 			KL4_WakeUp_LinearEnd	=	(KL4_WakeUp_LinearBase + KL4_WakeUp_LinearSize),

    80 			KL4_Per_LinearBase		=	KL4_Core_LinearEnd,

    81 			KL4_Per_LinearSize		=	KL4_Per_PhysicalSize,

    82 			KL4_Per_LinearEnd		=	(KL4_Per_LinearBase + KL4_Per_LinearSize),

    84 			KL4_Sgx_LinearBase		=	KL4_Per_LinearEnd,

    85 			KL4_Sgx_LinearSize		=	KL4_Sgx_PhysicalSize,

    86 			KL4_Sgx_LinearEnd		=	(KL4_Sgx_LinearBase + KL4_Sgx_LinearSize),

    88 			KL4_Emu_LinearBase		=	KL4_Sgx_LinearBase + KMegaByte,

    89 			KL4_Emu_LinearSize		=	KL4_Emu_PhysicalSize,

    90 			KL4_Emu_LinearEnd		=	(KL4_Emu_LinearBase + KL4_Emu_LinearSize),

    92 			KL3_Control_LinearBase	=	KL4_Emu_LinearEnd,

    93 			KL3_Control_LinearSize	=	KL3_Control_PhysicalSize,

    94 			KL3_Control_LinearEnd	=	(KL3_Control_LinearBase + KL3_Control_LinearSize),

    96 			KL3_Gpmc_LinearBase		=	KL3_Control_LinearEnd,

    97 			KL3_Gpmc_LinearSize		=	KL3_Gpmc_PhysicalSize,

    98 			KL3_Gpmc_LinearEnd		=	(KL3_Gpmc_LinearBase + KL3_Gpmc_LinearSize)

    99 			} ;

   101 		/**

   102 		A template to provide the virtual address of a given physical address.

   103 		@example

   104 		@code

   105 			enum TTimerBaseAddress

   106 				{

   107 				KGPTIMER1_Base			= Omap3530HwBase::TVirtual<0x48318000>::Value,

   108 				} ;

   109 		*/

   110 		template<const TPhysAddr aDdReSs>

   111 		struct TVirtual

   112 			{

   113 			enum TConstants

   114 				{

   115 				KIsL4Core		=	((aDdReSs >= KL4_Core_PhysicalBase) && (aDdReSs < KL4_Core_PhysicalEnd)),

   116 				KIsL4WakeUp		=	((aDdReSs >= KL4_WakeUp_PhysicalBase) && (aDdReSs < KL4_WakeUp_PhysicalEnd)),	// Subset of L4Core

   117 				KIsL4Per		=	((aDdReSs >= KL4_Per_PhysicalBase) && (aDdReSs < KL4_Per_PhysicalEnd)),

   118 				KIsL4Sgx		=	((aDdReSs >= KL4_Sgx_PhysicalBase) && (aDdReSs < KL4_Sgx_PhysicalEnd)),

   119 				KIsL4Emu		=	((aDdReSs >= KL4_Emu_PhysicalBase) && (aDdReSs < KL4_Emu_PhysicalEnd)),

   120 				KIsL3Control	=	((aDdReSs >= KL3_Control_PhysicalBase) && (aDdReSs < KL3_Control_PhysicalEnd)),

   121 				KIsL3Gpmc		=	((aDdReSs >= KL3_Gpmc_PhysicalBase) && (aDdReSs < KL3_Gpmc_PhysicalEnd)),

   122 				KIsConvertable	=	(KIsL4Core || KIsL4Per || KIsL4Sgx || KIsL4Emu || KIsL3Control || KIsL3Gpmc),

   123 				KIsMapped		=	(KIsL4Core || KIsL4Per || KIsL4Sgx || KIsL4Emu || KIsL3Control || KIsL3Gpmc),

   124 				KOffset			= 	((KIsL4Core) ? (aDdReSs - KL4_Core_PhysicalBase)

   125 										: ((KIsL4Per) ? (aDdReSs - KL4_Per_PhysicalBase)

   126 											: ((KIsL4Sgx) ? (aDdReSs - KL4_Sgx_PhysicalBase)

   127 												: ((KIsL4Emu) ? (aDdReSs - KL4_Emu_PhysicalBase)

   128 													: ((KIsL3Control) ? (aDdReSs - KL3_Control_PhysicalBase)

   129 														: ((KIsL3Gpmc) ? (aDdReSs - KL3_Gpmc_PhysicalBase)

   130 															: (0))))))),

   131 				// TODO: Change to give compile time error if address not mapped

   132 				KLinearBase		=	((KIsL4Core) ? (KL4_Core_LinearBase)

   133 										: ((KIsL4Per) ? (KL4_Per_LinearBase)

   134 											: ((KIsL4Sgx) ? (KL4_Sgx_LinearBase)

   135 												: ((KIsL4Emu) ? (KL4_Emu_LinearBase)

   136 													: ((KIsL3Control) ? (KL3_Control_LinearBase)

   137 														: ((KIsL3Gpmc) ? (KL3_Gpmc_LinearBase)

   138 															: (0))))))),

   139 				/**

   140 				Returns the Linear address mapping  for a specific Physical address

   141 				*/

   142 				Value			=	(KLinearBase + KOffset)

   143 				} ;

   144 			} ;

   146 		template<const TLinAddr aDdReSs>

   147 		struct TLinearCheck

   148 			{

   149 			enum TConstants

   150 				{

   151 				KIsL4Core		=	((aDdReSs >= KL4_Core_LinearBase) && (aDdReSs < KL4_Core_LinearEnd)),

   152 				KIsL4Per		=	((aDdReSs >= KL4_Per_LinearBase) && (aDdReSs < KL4_Per_LinearEnd)),

   153 				KIsL4Sgx		=	((aDdReSs >= KL4_Sgx_LinearBase) && (aDdReSs < KL4_Sgx_LinearEnd)),

   154 				KIsL4Emu		=	((aDdReSs >= KL4_Emu_LinearBase) && (aDdReSs < KL4_Emu_LinearEnd)),

   155 				KIsL3Control	=	((aDdReSs >= KL3_Control_LinearBase) && (aDdReSs < KL3_Control_LinearBase)),

   156 				KIsL3Gpmc		=	((aDdReSs >= KL3_Gpmc_LinearBase) && (aDdReSs < KL3_Gpmc_LinearBase)),

   157 				KIsMapped		=	(KIsL4Core || KIsL4Per || KIsL4Sgx || KIsL4Emu || KIsL3Control || KIsL3Gpmc)

   158 				} ;

   159 			} ;

   161 #	ifdef __MEMMODEL_MULTIPLE__

   162 		const TUint KL4_Core	= KL4_Core_LinearBase; // KPrimaryIOBase

   163 		const TUint KL4_Per		= KL4_Per_LinearBase;

   164 		const TUint KSgx		= KL4_Sgx_LinearBase;

   165 		const TUint KL4_Emu		= KL4_Emu_LinearBase;

   166 		const TUint KL3_Control	= KL3_Control_LinearBase;

   167 		const TUint KL3_Gpmc	= KL3_Gpmc_LinearBase;

   168 //const TUint KIva2_2Ss = KL4_Core + 0x01910000;

   169 //const TUint KL3ControlRegisters = KL4_Core + 0x04910000;

   170 //const TUint KSmsRegisters = KL4_Core + 0x05910000;

   171 //const TUint KSdrcRegisters = KL4_Core + 0x06910000;

   172 //const TUint KGpmcRegisters = KL4_Core + 0x07910000;

   174 //#elif __MEMMODEL_FLEXIBLE__

   175 // define flexible memery model hw base addresses

   177 #	else // unknown memery model

   178 #		error hardware_base.h: Constants may need changing

   179 #	endif // memory model

   181 // Register Access types.

   183 		typedef	TUint32	TRegValue;

   184 		typedef	TUint32	TRegValue32;

   185 		typedef	TUint16	TRegValue16;

   186 		typedef	TUint8	TRegValue8;

   188 		/**

   189 		An interface template for read-only registers.

   190 		*/

   191 		template <TLinAddr aDdReSs>

   192 		class TReg32_R

   193 			{

   194 		  public :

   195 			static inline TRegValue Read()

   196 				{

   197 				__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;

   198 				return AsspRegister::Read32(aDdReSs) ;

   199 				}

   200 			} ;

   202 		template <TLinAddr aDdReSs>

   203 		class TReg16_R

   204 			{

   205 		  public :

   206 			static inline TRegValue16 Read()

   207 				{

   208 				__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;

   209 				return AsspRegister::Read16(aDdReSs) ;

   210 				}

   211 			} ;

   213 		template <TLinAddr aDdReSs>

   214 		class TReg8_R

   215 			{

   216 		  public :

   217 			static inline TRegValue8 Read()

   218 				{

   219 				__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;

   220 				return AsspRegister::Read8(aDdReSs) ;

   221 				}

   222 			} ;

   224 		/**

   225 		An interface template for read-write registers.

   226 		*/

   227 		template <TLinAddr aDdReSs>

   228 		class TReg32_RW : public TReg32_R<aDdReSs>

   229 			{

   230 		  public :

   231 			static inline void Write(const TRegValue aValue)

   232 				{

   233 				__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;

   234 				AsspRegister::Write32(aDdReSs, aValue) ;

   235 				}

   236 			static inline void Modify(const TRegValue aClearMask, const TRegValue aSetMask)

   237 				{

   238 				__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;

   239 				AsspRegister::Modify32(aDdReSs, aClearMask, aSetMask) ;

   240 				}

   241 			} ;

   243 		template <TLinAddr aDdReSs>

   244 		class TReg16_RW : public TReg16_R<aDdReSs>

   245 			{

   246 		  public :

   247 			static inline void Write(const TRegValue16 aValue)

   248 				{

   249 				__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;

   250 				AsspRegister::Write16(aDdReSs, aValue) ;

   251 				}

   252 			static inline void Modify(const TRegValue16 aClearMask, const TRegValue16 aSetMask)

   253 				{

   254 				__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;

   255 				AsspRegister::Modify16(aDdReSs, aClearMask, aSetMask) ;

   256 				}

   257 			} ;

   259 		template <TLinAddr aDdReSs>

   260 		class TReg8_RW : public TReg8_R<aDdReSs>

   261 			{

   262 		  public :

   263 			static inline void Write(const TRegValue8 aValue)

   264 				{

   265 				__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;

   266 				AsspRegister::Write8(aDdReSs, aValue) ;

   267 				}

   268 			static inline void Modify(const TRegValue8 aClearMask, const TRegValue8 aSetMask)

   269 				{

   270 				__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;

   271 				AsspRegister::Modify8(aDdReSs, aClearMask, aSetMask) ;

   272 				}

   273 			} ;

   275 		/**

   276 		An interface template for write-only registers.

   277 		*/

   278 		template <TLinAddr aDdReSs>

   279 		class TReg32_W

   280 			{

   281 		  public :

   282 			static inline void Write(const TRegValue aValue)

   283 				{

   284 				__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;

   285 				AsspRegister::Write32(aDdReSs, aValue) ;

   286 				}

   287 			} ;

   289 		template <TLinAddr aDdReSs>

   290 		class TReg16_W

   291 			{

   292 		  public :

   293 			static inline void Write(const TRegValue16 aValue)

   294 				{

   295 				__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;

   296 				AsspRegister::Write16(aDdReSs, aValue) ;

   297 				}

   298 			} ;

   300 		template <TLinAddr aDdReSs>

   301 		class TReg8_W

   302 			{

   303 		  public :

   304 			static inline void Write(const TRegValue8 aValue)

   305 				{

   306 				__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;

   307 				AsspRegister::Write8(aDdReSs, aValue) ;

   308 				}

   309 			} ;

   311 		/** Class for registers that have dynamic base address */

   312 		template <class T, TUint OfFsEt>

   313 		class TDynReg8_R

   314 			{

   315 		  public :

   316 			static inline TRegValue8 Read( const T& aOwner )

   317 				{

   318 				return AsspRegister::Read8( aOwner.Base() + OfFsEt ) ;

   319 				}

   320 			} ;

   322 		template <class T, TUint OfFsEt>

   323 		class TDynReg16_R

   324 			{

   325 		  public :

   326 			static inline TRegValue16 Read( const T& aOwner )

   327 				{

   328 				return AsspRegister::Read16( aOwner.Base() + OfFsEt ) ;

   329 				}

   330 			} ;

   332 		template <class T, TUint OfFsEt>

   333 		class TDynReg32_R

   334 			{

   335 		  public :

   336 			static inline TRegValue32 Read( const T& aOwner )

   337 				{

   338 				return AsspRegister::Read32( aOwner.Base() + OfFsEt ) ;

   339 				}

   340 			} ;

   343 		template <class T, TUint OfFsEt>

   344 		class TDynReg8_RW : public TDynReg8_R<T, OfFsEt>

   345 			{

   346 		  public :

   347 			static inline void Write( T& aOwner, const TRegValue8 aValue)

   348 				{

   349 				AsspRegister::Write8( aOwner.Base() + OfFsEt, aValue) ;

   350 				}

   351 			static inline void Modify( T& aOwner, const TRegValue8 aClearMask, const TRegValue8 aSetMask)

   352 				{

   353 				AsspRegister::Modify8( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ;

   354 				}

   355 			} ;

   357 		template <class T, TUint OfFsEt>

   358 		class TDynReg16_RW : public TDynReg16_R<T, OfFsEt>

   359 			{

   360 		  public :

   361 			static inline void Write( T& aOwner, const TRegValue16 aValue)

   362 				{

   363 				AsspRegister::Write16( aOwner.Base() + OfFsEt, aValue) ;

   364 				}

   365 			static inline void Modify( T& aOwner, const TRegValue16 aClearMask, const TRegValue16 aSetMask)

   366 				{

   367 				AsspRegister::Modify16( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ;

   368 				}

   369 			} ;

   371 		template <class T, TUint OfFsEt>

   372 		class TDynReg32_RW : public TDynReg32_R<T, OfFsEt>

   373 			{

   374 		  public :

   375 			static inline void Write( T& aOwner, const TRegValue32 aValue)

   376 				{

   377 				AsspRegister::Write32( aOwner.Base() + OfFsEt, aValue) ;

   378 				}

   379 			static inline void Modify( T& aOwner, const TRegValue32 aClearMask, const TRegValue32 aSetMask)

   380 				{

   381 				AsspRegister::Modify32( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ;

   382 				}

   383 			} ;

   385 		template <class T, TUint OfFsEt>

   386 		class TDynReg8_W

   387 			{

   388 		  public :

   389 			static inline void Write( T& aOwner, const TRegValue8 aValue)

   390 				{

   391 				AsspRegister::Write8( aOwner.Base() + OfFsEt, aValue) ;

   392 				}

   393 			static inline void Modify( T& aOwner, const TRegValue8 aClearMask, const TRegValue8 aSetMask)

   394 				{

   395 				AsspRegister::Modify8( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ;

   396 				}

   397 			} ;

   399 		template <class T, TUint OfFsEt>

   400 		class TDynReg16_W

   401 			{

   402 		  public :

   403 			static inline void Write( T& aOwner, const TRegValue16 aValue)

   404 				{

   405 				AsspRegister::Write16( aOwner.Base() + OfFsEt, aValue) ;

   406 				}

   407 			static inline void Modify( T& aOwner, const TRegValue16 aClearMask, const TRegValue16 aSetMask)

   408 				{

   409 				AsspRegister::Modify16( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ;

   410 				}

   411 			} ;

   413 		template <class T, TUint OfFsEt>

   414 		class TDynReg32_W

   415 			{

   416 		  public :

   417 			static inline void Write( T& aOwner, const TRegValue32 aValue)

   418 				{

   419 				AsspRegister::Write32( aOwner.Base() + OfFsEt, aValue) ;

   420 				}

   421 			static inline void Modify( T& aOwner, const TRegValue32 aClearMask, const TRegValue32 aSetMask)

   422 				{

   423 				AsspRegister::Modify32( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ;

   424 				}

   425 			} ;

   427 			/**

   428 		An Null class for when no register access is required.

   429 		*/

   430 		class TNull_Reg

   431 			{

   432 		  public :

   433 			static inline TRegValue Read()

   434 				{

   435 				return 0 ;

   436 				}

   437 			static inline void Write(const TRegValue)

   438 				{

   439 				}

   440 			static inline void Modify(const TRegValue, const TRegValue)

   441 				{

   442 				}

   443 			} ;

   445 		template <int aBiTpOsItIoN>

   446 		class TBit

   447 			{

   448 		  public :

   449 			enum	TConstants

   450 				{

   451 				KValue	= (1 << aBiTpOsItIoN)

   452 				} ;

   453 			} ;

   455 		template <int aBiTpOsItIoN, int aBiTwIdTh>

   456 		class TBitFieldBase

   457 			{

   458 		  public :

   459 			enum	TConstants

   460 				{

   461 				KShift		= aBiTpOsItIoN,

   462 				KValueMask	= (TBit<aBiTwIdTh>::KValue - 1),

   463 				KFieldMask	= (KValueMask << KShift),

   464 				KValueMax	= KValueMask

   465 				} ;

   466 			} ;

   468 		template <int aBiTpOsItIoN, int aBiTwIdTh, int aVaLuE>

   469 		class TBitFieldValue : public TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>

   470 			{

   471 		  public :

   472 			using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KShift ;

   473 			using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KValueMask ;

   474 			using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KFieldMask ;

   475 			using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KValueMax ;

   477 			enum	TValues

   478 				{

   479 				KValue	= ((KValueMask & aVaLuE) << KShift)

   480 				} ;

   481 			} ;

   483 		template <int aBiTpOsItIoN, int aBiTwIdTh>

   484 		class TBitField : public TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>

   485 			{

   486 			using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KShift ;

   487 			using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KValueMask ;

   488 			using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KFieldMask ;

   489 			using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KValueMax ;

   490 		  public :

   491 			template <int aVaLuE>

   492 			class	TConstVal : public TBitFieldValue<aBiTpOsItIoN, aBiTwIdTh, aVaLuE>

   493 				{

   494 			  public :

   495 				using TBitFieldValue<aBiTpOsItIoN, aBiTwIdTh, aVaLuE>::KValue ;

   496 				} ;

   498 			inline TBitField(const TRegValue aValue)

   499 				  : iValue((KValueMask & aValue) << KShift) {}

   501 			inline TBitField(const TRegValue * aValuePtr)

   502 				  : iValue(KFieldMask & *aValuePtr) {}

   504 			template <TLinAddr aDdReSs>

   505 			inline TBitField(const TReg32_R<aDdReSs>& aReg)

   506 				  : iValue(KFieldMask & aReg.Read()) {}

   508 			inline TRegValue Value() const {return (KValueMask & (iValue >> KShift)) ;}

   510 			inline TRegValue RegField() const {return (iValue) ;}

   512 		  private :

   513 			TRegValue			iValue ;

   514 			} ;

   516 		template <int aBiTpOsItIoN>

   517 		class TSingleBitField : public TBitField<aBiTpOsItIoN, 1>

   518 			{

   519 		  public :

   520 			enum TConstants

   521 				{

   522 				KOff	= 0,

   523 				KOn		= (1 << aBiTpOsItIoN),

   524 				KClear	= KOff,

   525 				KSet	= KOn,

   526 				KMask	= KOn,

   527 				} ;

   528 			} ;

   530 		} ;	// namespace Omap3530

   532 	} ;	// namespace TexasInstruments

   535 namespace TI = TexasInstruments ;

   537 namespace OMAP3530 = TexasInstruments::Omap3530 ;

   539 namespace Omap3530HwBase = TexasInstruments::Omap3530 ;

   541 // **** TEST CODE ****

   542 //#	define HEADER_OMAP3530_HARDWARE_BASE_H_DO_COMPILE_TIME_CHECK_TESTS 1

   543 #	ifdef HEADER_OMAP3530_HARDWARE_BASE_H_DO_COMPILE_TIME_CHECK_TESTS

   544 		inline void CompileTimeChecks(void)

   545 			{

   546 			__ASSERT_COMPILE((Omap3530HwBase::TVirtual<0x48318000>::KIsL4Core)) ;

   547 			__ASSERT_COMPILE((TI::Omap3530::TVirtual<0x48318000>::KIsL4WakeUp)) ;

   548 			__ASSERT_COMPILE((!Omap3530HwBase::TVirtual<0x48318000>::KIsL4Emu)) ;

   549 			__ASSERT_COMPILE((!Omap3530HwBase::TVirtual<0x0000FFFF>::KIsConvertable)) ;

   550 			__ASSERT_COMPILE((Omap3530HwBase::TLinearCheck< Omap3530HwBase::TVirtual<0x48318000>::Value >::KIsMapped)) ;

   551 			__ASSERT_COMPILE((!Omap3530HwBase::TLinearCheck< Omap3530HwBase::TVirtual<0x0000FFFF>::Value >::KIsMapped)) ;

   552 			const TLinAddr	mapped(Omap3530HwBase::TVirtual<0x48318000>::Value) ;

   553 			const TLinAddr	unmapped(Omap3530HwBase::TVirtual<0x0000FFFF>::Value) ;

   554 			__ASSERT_COMPILE((Omap3530HwBase::TLinearCheck< mapped >::KIsMapped)) ;

   555 			__ASSERT_COMPILE((!Omap3530HwBase::TLinearCheck< unmapped >::KIsMapped)) ;

   556 			__ASSERT_COMPILE((0)) ;		// Prove that testing is happening

   557 			}

   558 #	endif

   560 const TUint KSetNone = 0;

   561 const TUint KSetAll = 0xffffffff;

   562 const TUint KClearNone = 0;

   563 const TUint KClearAll = 0xffffffff;

   564 const TUint KHOmapClkULPD48Mhz = 48000000;

   566 #endif // !OMAP3530_HARDWARE_BASE_H__

author	William Roberts <williamr@symbian.org>
	Wed, 31 Mar 2010 12:33:34 +0100
branch	Symbian3
changeset 4	837f303aceeb
permissions	-rw-r--r--