1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/epoc32/include/assp/omap3530_assp/omap3530_hardware_base.h Wed Mar 31 12:33:34 2010 +0100
1.3 @@ -0,0 +1,569 @@
1.4 +// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// omap3530/assp/inc/omap3530_hardware_base.h
1.18 +// Linear base addresses for hardware peripherals on the beagle board.
1.19 +// This file is part of the Beagle Base port
1.20 +//
1.21 +
1.22 +#ifndef OMAP3530_HARDWARE_BASE_H__
1.23 +# define OMAP3530_HARDWARE_BASE_H__
1.24 +
1.25 +#include <assp.h> // for TPhysAddr, AsspRegister
1.26 +#include <assp/omap3530_assp/omap3530_asspreg.h>
1.27 +
1.28 +namespace TexasInstruments
1.29 + {
1.30 +
1.31 + namespace Omap3530
1.32 + {
1.33 +
1.34 + /**
1.35 + Define constants for the various physical address blocks used on the OMAP3530
1.36 + */
1.37 + enum TPhysicalAddresses
1.38 + {
1.39 + KKiloByte = 1024,
1.40 + KMegaByte = (1024 * KKiloByte),
1.41 + KL4_Core_PhysicalBase = 0x48000000,
1.42 + KL4_Core_PhysicalSize = (4 * KMegaByte),
1.43 + KL4_Core_PhysicalEnd = (KL4_Core_PhysicalBase + KL4_Core_PhysicalSize),
1.44 +
1.45 + KL4_WakeUp_PhysicalBase = 0x48300000,
1.46 + KL4_WakeUp_PhysicalSize = (256 * KKiloByte ),
1.47 + KL4_WakeUp_PhysicalEnd = (KL4_WakeUp_PhysicalBase + KL4_WakeUp_PhysicalSize),
1.48 +
1.49 + KL4_Per_PhysicalBase = 0x49000000,
1.50 + KL4_Per_PhysicalSize = (1 * KMegaByte),
1.51 + KL4_Per_PhysicalEnd = (KL4_Per_PhysicalBase + KL4_Per_PhysicalSize),
1.52 +
1.53 + KL4_Sgx_PhysicalBase = 0x50000000,
1.54 + KL4_Sgx_PhysicalSize = (64 * KKiloByte),
1.55 + KL4_Sgx_PhysicalEnd = (KL4_Sgx_PhysicalBase + KL4_Sgx_PhysicalSize),
1.56 +
1.57 + KL4_Emu_PhysicalBase = 0x54000000,
1.58 + KL4_Emu_PhysicalSize = (8 * KMegaByte),
1.59 + KL4_Emu_PhysicalEnd = (KL4_Emu_PhysicalBase + KL4_Emu_PhysicalSize),
1.60 +
1.61 + KL3_Control_PhysicalBase = 0x68000000,
1.62 + KL3_Control_PhysicalSize = (1 * KMegaByte),
1.63 + KL3_Control_PhysicalEnd = (KL3_Control_PhysicalBase + KL3_Control_PhysicalSize),
1.64 +
1.65 + KL3_Gpmc_PhysicalBase = 0x6e000000,
1.66 + KL3_Gpmc_PhysicalSize = (1 * KMegaByte),
1.67 + KL3_Gpmc_PhysicalEnd = (KL3_Gpmc_PhysicalBase + KL3_Gpmc_PhysicalSize)
1.68 + } ;
1.69 +
1.70 + /**
1.71 + Define constants for the virtual address mappings used on the OMAP3530
1.72 + */
1.73 + enum TLinearAddresses
1.74 + {
1.75 + KL4_Core_LinearBase = 0xC6000000,
1.76 + KL4_Core_LinearSize = KL4_Core_PhysicalSize,
1.77 + KL4_Core_LinearEnd = (KL4_Core_LinearBase + KL4_Core_LinearSize),
1.78 +
1.79 + KL4_WakeUp_LinearBase = (KL4_Core_LinearBase + (KL4_WakeUp_PhysicalBase - KL4_Core_PhysicalBase)),
1.80 + KL4_WakeUp_LinearSize = KL4_WakeUp_PhysicalSize,
1.81 + KL4_WakeUp_LinearEnd = (KL4_WakeUp_LinearBase + KL4_WakeUp_LinearSize),
1.82 +
1.83 + KL4_Per_LinearBase = KL4_Core_LinearEnd,
1.84 + KL4_Per_LinearSize = KL4_Per_PhysicalSize,
1.85 + KL4_Per_LinearEnd = (KL4_Per_LinearBase + KL4_Per_LinearSize),
1.86 +
1.87 + KL4_Sgx_LinearBase = KL4_Per_LinearEnd,
1.88 + KL4_Sgx_LinearSize = KL4_Sgx_PhysicalSize,
1.89 + KL4_Sgx_LinearEnd = (KL4_Sgx_LinearBase + KL4_Sgx_LinearSize),
1.90 +
1.91 + KL4_Emu_LinearBase = KL4_Sgx_LinearBase + KMegaByte,
1.92 + KL4_Emu_LinearSize = KL4_Emu_PhysicalSize,
1.93 + KL4_Emu_LinearEnd = (KL4_Emu_LinearBase + KL4_Emu_LinearSize),
1.94 +
1.95 + KL3_Control_LinearBase = KL4_Emu_LinearEnd,
1.96 + KL3_Control_LinearSize = KL3_Control_PhysicalSize,
1.97 + KL3_Control_LinearEnd = (KL3_Control_LinearBase + KL3_Control_LinearSize),
1.98 +
1.99 + KL3_Gpmc_LinearBase = KL3_Control_LinearEnd,
1.100 + KL3_Gpmc_LinearSize = KL3_Gpmc_PhysicalSize,
1.101 + KL3_Gpmc_LinearEnd = (KL3_Gpmc_LinearBase + KL3_Gpmc_LinearSize)
1.102 + } ;
1.103 +
1.104 + /**
1.105 + A template to provide the virtual address of a given physical address.
1.106 + @example
1.107 + @code
1.108 + enum TTimerBaseAddress
1.109 + {
1.110 + KGPTIMER1_Base = Omap3530HwBase::TVirtual<0x48318000>::Value,
1.111 + } ;
1.112 + */
1.113 + template<const TPhysAddr aDdReSs>
1.114 + struct TVirtual
1.115 + {
1.116 + enum TConstants
1.117 + {
1.118 + KIsL4Core = ((aDdReSs >= KL4_Core_PhysicalBase) && (aDdReSs < KL4_Core_PhysicalEnd)),
1.119 + KIsL4WakeUp = ((aDdReSs >= KL4_WakeUp_PhysicalBase) && (aDdReSs < KL4_WakeUp_PhysicalEnd)), // Subset of L4Core
1.120 + KIsL4Per = ((aDdReSs >= KL4_Per_PhysicalBase) && (aDdReSs < KL4_Per_PhysicalEnd)),
1.121 + KIsL4Sgx = ((aDdReSs >= KL4_Sgx_PhysicalBase) && (aDdReSs < KL4_Sgx_PhysicalEnd)),
1.122 + KIsL4Emu = ((aDdReSs >= KL4_Emu_PhysicalBase) && (aDdReSs < KL4_Emu_PhysicalEnd)),
1.123 + KIsL3Control = ((aDdReSs >= KL3_Control_PhysicalBase) && (aDdReSs < KL3_Control_PhysicalEnd)),
1.124 + KIsL3Gpmc = ((aDdReSs >= KL3_Gpmc_PhysicalBase) && (aDdReSs < KL3_Gpmc_PhysicalEnd)),
1.125 + KIsConvertable = (KIsL4Core || KIsL4Per || KIsL4Sgx || KIsL4Emu || KIsL3Control || KIsL3Gpmc),
1.126 + KIsMapped = (KIsL4Core || KIsL4Per || KIsL4Sgx || KIsL4Emu || KIsL3Control || KIsL3Gpmc),
1.127 + KOffset = ((KIsL4Core) ? (aDdReSs - KL4_Core_PhysicalBase)
1.128 + : ((KIsL4Per) ? (aDdReSs - KL4_Per_PhysicalBase)
1.129 + : ((KIsL4Sgx) ? (aDdReSs - KL4_Sgx_PhysicalBase)
1.130 + : ((KIsL4Emu) ? (aDdReSs - KL4_Emu_PhysicalBase)
1.131 + : ((KIsL3Control) ? (aDdReSs - KL3_Control_PhysicalBase)
1.132 + : ((KIsL3Gpmc) ? (aDdReSs - KL3_Gpmc_PhysicalBase)
1.133 + : (0))))))),
1.134 + // TODO: Change to give compile time error if address not mapped
1.135 + KLinearBase = ((KIsL4Core) ? (KL4_Core_LinearBase)
1.136 + : ((KIsL4Per) ? (KL4_Per_LinearBase)
1.137 + : ((KIsL4Sgx) ? (KL4_Sgx_LinearBase)
1.138 + : ((KIsL4Emu) ? (KL4_Emu_LinearBase)
1.139 + : ((KIsL3Control) ? (KL3_Control_LinearBase)
1.140 + : ((KIsL3Gpmc) ? (KL3_Gpmc_LinearBase)
1.141 + : (0))))))),
1.142 + /**
1.143 + Returns the Linear address mapping for a specific Physical address
1.144 + */
1.145 + Value = (KLinearBase + KOffset)
1.146 + } ;
1.147 + } ;
1.148 +
1.149 + template<const TLinAddr aDdReSs>
1.150 + struct TLinearCheck
1.151 + {
1.152 + enum TConstants
1.153 + {
1.154 + KIsL4Core = ((aDdReSs >= KL4_Core_LinearBase) && (aDdReSs < KL4_Core_LinearEnd)),
1.155 + KIsL4Per = ((aDdReSs >= KL4_Per_LinearBase) && (aDdReSs < KL4_Per_LinearEnd)),
1.156 + KIsL4Sgx = ((aDdReSs >= KL4_Sgx_LinearBase) && (aDdReSs < KL4_Sgx_LinearEnd)),
1.157 + KIsL4Emu = ((aDdReSs >= KL4_Emu_LinearBase) && (aDdReSs < KL4_Emu_LinearEnd)),
1.158 + KIsL3Control = ((aDdReSs >= KL3_Control_LinearBase) && (aDdReSs < KL3_Control_LinearBase)),
1.159 + KIsL3Gpmc = ((aDdReSs >= KL3_Gpmc_LinearBase) && (aDdReSs < KL3_Gpmc_LinearBase)),
1.160 + KIsMapped = (KIsL4Core || KIsL4Per || KIsL4Sgx || KIsL4Emu || KIsL3Control || KIsL3Gpmc)
1.161 + } ;
1.162 + } ;
1.163 +
1.164 +# ifdef __MEMMODEL_MULTIPLE__
1.165 + const TUint KL4_Core = KL4_Core_LinearBase; // KPrimaryIOBase
1.166 + const TUint KL4_Per = KL4_Per_LinearBase;
1.167 + const TUint KSgx = KL4_Sgx_LinearBase;
1.168 + const TUint KL4_Emu = KL4_Emu_LinearBase;
1.169 + const TUint KL3_Control = KL3_Control_LinearBase;
1.170 + const TUint KL3_Gpmc = KL3_Gpmc_LinearBase;
1.171 +//const TUint KIva2_2Ss = KL4_Core + 0x01910000;
1.172 +//const TUint KL3ControlRegisters = KL4_Core + 0x04910000;
1.173 +//const TUint KSmsRegisters = KL4_Core + 0x05910000;
1.174 +//const TUint KSdrcRegisters = KL4_Core + 0x06910000;
1.175 +//const TUint KGpmcRegisters = KL4_Core + 0x07910000;
1.176 +
1.177 +//#elif __MEMMODEL_FLEXIBLE__
1.178 +// define flexible memery model hw base addresses
1.179 +
1.180 +# else // unknown memery model
1.181 +# error hardware_base.h: Constants may need changing
1.182 +# endif // memory model
1.183 +
1.184 +// Register Access types.
1.185 +
1.186 + typedef TUint32 TRegValue;
1.187 + typedef TUint32 TRegValue32;
1.188 + typedef TUint16 TRegValue16;
1.189 + typedef TUint8 TRegValue8;
1.190 +
1.191 + /**
1.192 + An interface template for read-only registers.
1.193 + */
1.194 + template <TLinAddr aDdReSs>
1.195 + class TReg32_R
1.196 + {
1.197 + public :
1.198 + static inline TRegValue Read()
1.199 + {
1.200 + __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;
1.201 + return AsspRegister::Read32(aDdReSs) ;
1.202 + }
1.203 + } ;
1.204 +
1.205 + template <TLinAddr aDdReSs>
1.206 + class TReg16_R
1.207 + {
1.208 + public :
1.209 + static inline TRegValue16 Read()
1.210 + {
1.211 + __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;
1.212 + return AsspRegister::Read16(aDdReSs) ;
1.213 + }
1.214 + } ;
1.215 +
1.216 + template <TLinAddr aDdReSs>
1.217 + class TReg8_R
1.218 + {
1.219 + public :
1.220 + static inline TRegValue8 Read()
1.221 + {
1.222 + __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;
1.223 + return AsspRegister::Read8(aDdReSs) ;
1.224 + }
1.225 + } ;
1.226 +
1.227 + /**
1.228 + An interface template for read-write registers.
1.229 + */
1.230 + template <TLinAddr aDdReSs>
1.231 + class TReg32_RW : public TReg32_R<aDdReSs>
1.232 + {
1.233 + public :
1.234 + static inline void Write(const TRegValue aValue)
1.235 + {
1.236 + __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;
1.237 + AsspRegister::Write32(aDdReSs, aValue) ;
1.238 + }
1.239 + static inline void Modify(const TRegValue aClearMask, const TRegValue aSetMask)
1.240 + {
1.241 + __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;
1.242 + AsspRegister::Modify32(aDdReSs, aClearMask, aSetMask) ;
1.243 + }
1.244 + } ;
1.245 +
1.246 + template <TLinAddr aDdReSs>
1.247 + class TReg16_RW : public TReg16_R<aDdReSs>
1.248 + {
1.249 + public :
1.250 + static inline void Write(const TRegValue16 aValue)
1.251 + {
1.252 + __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;
1.253 + AsspRegister::Write16(aDdReSs, aValue) ;
1.254 + }
1.255 + static inline void Modify(const TRegValue16 aClearMask, const TRegValue16 aSetMask)
1.256 + {
1.257 + __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;
1.258 + AsspRegister::Modify16(aDdReSs, aClearMask, aSetMask) ;
1.259 + }
1.260 + } ;
1.261 +
1.262 + template <TLinAddr aDdReSs>
1.263 + class TReg8_RW : public TReg8_R<aDdReSs>
1.264 + {
1.265 + public :
1.266 + static inline void Write(const TRegValue8 aValue)
1.267 + {
1.268 + __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;
1.269 + AsspRegister::Write8(aDdReSs, aValue) ;
1.270 + }
1.271 + static inline void Modify(const TRegValue8 aClearMask, const TRegValue8 aSetMask)
1.272 + {
1.273 + __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;
1.274 + AsspRegister::Modify8(aDdReSs, aClearMask, aSetMask) ;
1.275 + }
1.276 + } ;
1.277 +
1.278 + /**
1.279 + An interface template for write-only registers.
1.280 + */
1.281 + template <TLinAddr aDdReSs>
1.282 + class TReg32_W
1.283 + {
1.284 + public :
1.285 + static inline void Write(const TRegValue aValue)
1.286 + {
1.287 + __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;
1.288 + AsspRegister::Write32(aDdReSs, aValue) ;
1.289 + }
1.290 + } ;
1.291 +
1.292 + template <TLinAddr aDdReSs>
1.293 + class TReg16_W
1.294 + {
1.295 + public :
1.296 + static inline void Write(const TRegValue16 aValue)
1.297 + {
1.298 + __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;
1.299 + AsspRegister::Write16(aDdReSs, aValue) ;
1.300 + }
1.301 + } ;
1.302 +
1.303 + template <TLinAddr aDdReSs>
1.304 + class TReg8_W
1.305 + {
1.306 + public :
1.307 + static inline void Write(const TRegValue8 aValue)
1.308 + {
1.309 + __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ;
1.310 + AsspRegister::Write8(aDdReSs, aValue) ;
1.311 + }
1.312 + } ;
1.313 +
1.314 + /** Class for registers that have dynamic base address */
1.315 + template <class T, TUint OfFsEt>
1.316 + class TDynReg8_R
1.317 + {
1.318 + public :
1.319 + static inline TRegValue8 Read( const T& aOwner )
1.320 + {
1.321 + return AsspRegister::Read8( aOwner.Base() + OfFsEt ) ;
1.322 + }
1.323 + } ;
1.324 +
1.325 + template <class T, TUint OfFsEt>
1.326 + class TDynReg16_R
1.327 + {
1.328 + public :
1.329 + static inline TRegValue16 Read( const T& aOwner )
1.330 + {
1.331 + return AsspRegister::Read16( aOwner.Base() + OfFsEt ) ;
1.332 + }
1.333 + } ;
1.334 +
1.335 + template <class T, TUint OfFsEt>
1.336 + class TDynReg32_R
1.337 + {
1.338 + public :
1.339 + static inline TRegValue32 Read( const T& aOwner )
1.340 + {
1.341 + return AsspRegister::Read32( aOwner.Base() + OfFsEt ) ;
1.342 + }
1.343 + } ;
1.344 +
1.345 +
1.346 + template <class T, TUint OfFsEt>
1.347 + class TDynReg8_RW : public TDynReg8_R<T, OfFsEt>
1.348 + {
1.349 + public :
1.350 + static inline void Write( T& aOwner, const TRegValue8 aValue)
1.351 + {
1.352 + AsspRegister::Write8( aOwner.Base() + OfFsEt, aValue) ;
1.353 + }
1.354 + static inline void Modify( T& aOwner, const TRegValue8 aClearMask, const TRegValue8 aSetMask)
1.355 + {
1.356 + AsspRegister::Modify8( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ;
1.357 + }
1.358 + } ;
1.359 +
1.360 + template <class T, TUint OfFsEt>
1.361 + class TDynReg16_RW : public TDynReg16_R<T, OfFsEt>
1.362 + {
1.363 + public :
1.364 + static inline void Write( T& aOwner, const TRegValue16 aValue)
1.365 + {
1.366 + AsspRegister::Write16( aOwner.Base() + OfFsEt, aValue) ;
1.367 + }
1.368 + static inline void Modify( T& aOwner, const TRegValue16 aClearMask, const TRegValue16 aSetMask)
1.369 + {
1.370 + AsspRegister::Modify16( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ;
1.371 + }
1.372 + } ;
1.373 +
1.374 + template <class T, TUint OfFsEt>
1.375 + class TDynReg32_RW : public TDynReg32_R<T, OfFsEt>
1.376 + {
1.377 + public :
1.378 + static inline void Write( T& aOwner, const TRegValue32 aValue)
1.379 + {
1.380 + AsspRegister::Write32( aOwner.Base() + OfFsEt, aValue) ;
1.381 + }
1.382 + static inline void Modify( T& aOwner, const TRegValue32 aClearMask, const TRegValue32 aSetMask)
1.383 + {
1.384 + AsspRegister::Modify32( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ;
1.385 + }
1.386 + } ;
1.387 +
1.388 + template <class T, TUint OfFsEt>
1.389 + class TDynReg8_W
1.390 + {
1.391 + public :
1.392 + static inline void Write( T& aOwner, const TRegValue8 aValue)
1.393 + {
1.394 + AsspRegister::Write8( aOwner.Base() + OfFsEt, aValue) ;
1.395 + }
1.396 + static inline void Modify( T& aOwner, const TRegValue8 aClearMask, const TRegValue8 aSetMask)
1.397 + {
1.398 + AsspRegister::Modify8( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ;
1.399 + }
1.400 + } ;
1.401 +
1.402 + template <class T, TUint OfFsEt>
1.403 + class TDynReg16_W
1.404 + {
1.405 + public :
1.406 + static inline void Write( T& aOwner, const TRegValue16 aValue)
1.407 + {
1.408 + AsspRegister::Write16( aOwner.Base() + OfFsEt, aValue) ;
1.409 + }
1.410 + static inline void Modify( T& aOwner, const TRegValue16 aClearMask, const TRegValue16 aSetMask)
1.411 + {
1.412 + AsspRegister::Modify16( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ;
1.413 + }
1.414 + } ;
1.415 +
1.416 + template <class T, TUint OfFsEt>
1.417 + class TDynReg32_W
1.418 + {
1.419 + public :
1.420 + static inline void Write( T& aOwner, const TRegValue32 aValue)
1.421 + {
1.422 + AsspRegister::Write32( aOwner.Base() + OfFsEt, aValue) ;
1.423 + }
1.424 + static inline void Modify( T& aOwner, const TRegValue32 aClearMask, const TRegValue32 aSetMask)
1.425 + {
1.426 + AsspRegister::Modify32( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ;
1.427 + }
1.428 + } ;
1.429 +
1.430 + /**
1.431 + An Null class for when no register access is required.
1.432 + */
1.433 + class TNull_Reg
1.434 + {
1.435 + public :
1.436 + static inline TRegValue Read()
1.437 + {
1.438 + return 0 ;
1.439 + }
1.440 + static inline void Write(const TRegValue)
1.441 + {
1.442 + }
1.443 + static inline void Modify(const TRegValue, const TRegValue)
1.444 + {
1.445 + }
1.446 + } ;
1.447 +
1.448 + template <int aBiTpOsItIoN>
1.449 + class TBit
1.450 + {
1.451 + public :
1.452 + enum TConstants
1.453 + {
1.454 + KValue = (1 << aBiTpOsItIoN)
1.455 + } ;
1.456 + } ;
1.457 +
1.458 + template <int aBiTpOsItIoN, int aBiTwIdTh>
1.459 + class TBitFieldBase
1.460 + {
1.461 + public :
1.462 + enum TConstants
1.463 + {
1.464 + KShift = aBiTpOsItIoN,
1.465 + KValueMask = (TBit<aBiTwIdTh>::KValue - 1),
1.466 + KFieldMask = (KValueMask << KShift),
1.467 + KValueMax = KValueMask
1.468 + } ;
1.469 + } ;
1.470 +
1.471 + template <int aBiTpOsItIoN, int aBiTwIdTh, int aVaLuE>
1.472 + class TBitFieldValue : public TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>
1.473 + {
1.474 + public :
1.475 + using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KShift ;
1.476 + using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KValueMask ;
1.477 + using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KFieldMask ;
1.478 + using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KValueMax ;
1.479 +
1.480 + enum TValues
1.481 + {
1.482 + KValue = ((KValueMask & aVaLuE) << KShift)
1.483 + } ;
1.484 + } ;
1.485 +
1.486 + template <int aBiTpOsItIoN, int aBiTwIdTh>
1.487 + class TBitField : public TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>
1.488 + {
1.489 + using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KShift ;
1.490 + using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KValueMask ;
1.491 + using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KFieldMask ;
1.492 + using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KValueMax ;
1.493 + public :
1.494 + template <int aVaLuE>
1.495 + class TConstVal : public TBitFieldValue<aBiTpOsItIoN, aBiTwIdTh, aVaLuE>
1.496 + {
1.497 + public :
1.498 + using TBitFieldValue<aBiTpOsItIoN, aBiTwIdTh, aVaLuE>::KValue ;
1.499 + } ;
1.500 +
1.501 + inline TBitField(const TRegValue aValue)
1.502 + : iValue((KValueMask & aValue) << KShift) {}
1.503 +
1.504 + inline TBitField(const TRegValue * aValuePtr)
1.505 + : iValue(KFieldMask & *aValuePtr) {}
1.506 +
1.507 + template <TLinAddr aDdReSs>
1.508 + inline TBitField(const TReg32_R<aDdReSs>& aReg)
1.509 + : iValue(KFieldMask & aReg.Read()) {}
1.510 +
1.511 + inline TRegValue Value() const {return (KValueMask & (iValue >> KShift)) ;}
1.512 +
1.513 + inline TRegValue RegField() const {return (iValue) ;}
1.514 +
1.515 + private :
1.516 + TRegValue iValue ;
1.517 + } ;
1.518 +
1.519 + template <int aBiTpOsItIoN>
1.520 + class TSingleBitField : public TBitField<aBiTpOsItIoN, 1>
1.521 + {
1.522 + public :
1.523 + enum TConstants
1.524 + {
1.525 + KOff = 0,
1.526 + KOn = (1 << aBiTpOsItIoN),
1.527 + KClear = KOff,
1.528 + KSet = KOn,
1.529 + KMask = KOn,
1.530 + } ;
1.531 + } ;
1.532 +
1.533 + } ; // namespace Omap3530
1.534 +
1.535 + } ; // namespace TexasInstruments
1.536 +
1.537 +
1.538 +namespace TI = TexasInstruments ;
1.539 +
1.540 +namespace OMAP3530 = TexasInstruments::Omap3530 ;
1.541 +
1.542 +namespace Omap3530HwBase = TexasInstruments::Omap3530 ;
1.543 +
1.544 +// **** TEST CODE ****
1.545 +//# define HEADER_OMAP3530_HARDWARE_BASE_H_DO_COMPILE_TIME_CHECK_TESTS 1
1.546 +# ifdef HEADER_OMAP3530_HARDWARE_BASE_H_DO_COMPILE_TIME_CHECK_TESTS
1.547 + inline void CompileTimeChecks(void)
1.548 + {
1.549 + __ASSERT_COMPILE((Omap3530HwBase::TVirtual<0x48318000>::KIsL4Core)) ;
1.550 + __ASSERT_COMPILE((TI::Omap3530::TVirtual<0x48318000>::KIsL4WakeUp)) ;
1.551 + __ASSERT_COMPILE((!Omap3530HwBase::TVirtual<0x48318000>::KIsL4Emu)) ;
1.552 + __ASSERT_COMPILE((!Omap3530HwBase::TVirtual<0x0000FFFF>::KIsConvertable)) ;
1.553 + __ASSERT_COMPILE((Omap3530HwBase::TLinearCheck< Omap3530HwBase::TVirtual<0x48318000>::Value >::KIsMapped)) ;
1.554 + __ASSERT_COMPILE((!Omap3530HwBase::TLinearCheck< Omap3530HwBase::TVirtual<0x0000FFFF>::Value >::KIsMapped)) ;
1.555 + const TLinAddr mapped(Omap3530HwBase::TVirtual<0x48318000>::Value) ;
1.556 + const TLinAddr unmapped(Omap3530HwBase::TVirtual<0x0000FFFF>::Value) ;
1.557 + __ASSERT_COMPILE((Omap3530HwBase::TLinearCheck< mapped >::KIsMapped)) ;
1.558 + __ASSERT_COMPILE((!Omap3530HwBase::TLinearCheck< unmapped >::KIsMapped)) ;
1.559 + __ASSERT_COMPILE((0)) ; // Prove that testing is happening
1.560 + }
1.561 +# endif
1.562 +
1.563 +const TUint KSetNone = 0;
1.564 +const TUint KSetAll = 0xffffffff;
1.565 +const TUint KClearNone = 0;
1.566 +const TUint KClearAll = 0xffffffff;
1.567 +const TUint KHOmapClkULPD48Mhz = 48000000;
1.568 +
1.569 +#endif // !OMAP3530_HARDWARE_BASE_H__
1.570 +
1.571 +
1.572 +