Symaptic: os/kernelhwsrv/kerneltest/e32test/iic/t

     1 // Copyright (c) 1995-2009 Nokia Corporation and/or its subsidiary(-ies).

     2 // All rights reserved.

     3 // This component and the accompanying materials are made available

     4 // under the terms of the License "Eclipse Public License v1.0"

     5 // which accompanies this distribution, and is available

     6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".

     7 //

     8 // Initial Contributors:

     9 // Nokia Corporation - initial contribution.

    10 //

    11 // Contributors:

    12 //

    13 // Description:

    14 // e32test\iic\t_iic.h

    15 //

    17 #ifndef __T_IIC_H__

    18 #define __T_IIC_H__

    20 #include <e32ver.h>

    22 const TInt KIicClientMajorVersionNumber = 1;

    23 const TInt KIicClientMinorVersionNumber = 0;

    24 const TInt KIicClientBuildVersionNumber = KE32BuildVersionNumber;

    26 const TInt KPriorityTestNum = 6; // 1 blocking transaction + 5 test transactions

    28 // For IIC,

    29 // If bit 31 is set and bit 30 cleared it is used to extend the Master-Slave channel;

    30 // if bit 31 is cleared and bit 30 is set, it extends the Master channel;

    31 // if both bits 31 and 30 are cleared it extends the Slave channel interface.

    32 // However,

    33 // since the kernel-side proxy clients interpret the msb being set as indicative of an

    34 // asynchronous request, the values here will have the static extension pattern represented

    35 // in bits 30 and 29, instead. In addition, to support communication with the slave-side proxy,

    36 // the Slave extension value will be represented as bits 30 and 29 set, so that it can be distinguished

    37 // from 'normal' synchronous operations.

    38 //

    39 const TUint KTestControlIoMask =			0x60000000;

    40 const TUint KTestMasterControlIo =		0x20000000;

    41 const TUint KTestSlaveControlIo =		0x60000000;

    42 const TUint KTestMasterSlaveControlIo =	0x40000000;

    43 const TUint KTestControlIoPilOffset =	0x00000002;	// Corresponds to 1 higher than the number used by PIL

    44 const TUint KTestControlUnitTestOffset = 0x10000000;

    46 //

    47 // Enumerations TReqType and TBusType defined in kernel-side class TIicBusTransfer

    48 // The user-side test, and the kernel-side proxy client require access to this

    49 enum TReqType

    50 	{

    51 	EMasterRead,

    52 	EMasterWrite

    53 	};

    54 enum TBusType

    55 	{

    56 	EI2c	   = 0,

    57 	ESpi	   = 0x01,

    58 	EMicrowire = 0x02,

    59 	ECci	   = 0x03,

    60 	ESccb	   = 0x04,

    61 	EInvalidBus

    62 	};

    64 #define MAX_TRANS_LENGTH 20

    67 #ifndef __KERNEL_MODE__

    68 //

    69 //	For convenience, selected kernel-side information is replicated here

    70 //  to allow the user-side test to populate buffers accordingly

    71 //

    72 // Bus-specific configuration

    73 //

    74 enum TEndianness

    75 	{

    76 	EBigEndian,

    77 	ELittleEndian

    78 	};

    80 enum TBitOrder

    81 	{

    82 	ELsbFirst,

    83 	EMsbFirst

    84 	};

    86 //

    87 // Bus-specific configuration for SPI bus

    88 //

    90 enum TSpiWordWidth

    91 	{

    92 	ESpiWordWidth_8,

    93 	ESpiWordWidth_10,

    94 	ESpiWordWidth_12,

    95 	ESpiWordWidth_16

    96 	};

    98 enum TSpiClkMode

    99 	{

   100 	ESpiPolarityLowRisingEdge,		// Active high, odd edges

   101 	ESpiPolarityLowFallingEdge,		// Active high, even edges

   102 	ESpiPolarityHighFallingEdge,	// Active low,  odd edges

   103 	ESpiPolarityHighRisingEdge		// Active low,  even edges

   104 	};

   106 enum TSpiSsPinMode

   107     {

   108     ESpiCSPinActiveLow,      // Active low

   109     ESpiCSPinActiveHigh     // Active high

   110     };

   112 class TConfigSpiV01

   113 	{

   114 public:

   115 	TSpiWordWidth	iWordWidth;

   116 	TInt32			iClkSpeedHz;

   117 	TSpiClkMode		iClkMode;

   118 	TInt32			iTimeoutPeriod;

   119 	TEndianness		iEndianness;

   120 	TBitOrder		iBitOrder;

   121 	TUint			iTransactionWaitCycles;

   122 	TSpiSsPinMode	iSSPinActiveMode;

   123 	};

   125 typedef TPckgBuf <TConfigSpiV01> TConfigSpiBufV01;

   128 //

   129 // Bus-specific configuration for I2C bus

   130 //

   132 enum TI2cAddrType

   133 	{

   134 	EI2cAddr7Bit,

   135 	EI2cAddr10Bit

   136 	};

   138 class TConfigI2cV01

   139 	{

   140 	public:

   141 	TI2cAddrType	iAddrType;		// 7 or 10-bit addressing

   142 	TInt32			iClkSpeedHz;

   143 	TEndianness		iEndianness;

   144 	TInt32			iTimeoutPeriod;

   145 	};

   147 typedef TPckgBuf <TConfigI2cV01> TConfigI2cBufV01;

   150 inline static TInt CreateSpiBuf(TConfigSpiBufV01*& aBuf,

   151 								TSpiWordWidth	aWordWidth,

   152 								TInt32			aClkSpeedHz,

   153 								TSpiClkMode		aClkMode,

   154 								TInt32			aTimeoutPeriod,

   155 								TEndianness		aEndianness,

   156 								TBitOrder		aBitOrder,

   157 								TUint			aTransactionWaitCycles,

   158 								TSpiSsPinMode	aSSPinActiveMode)

   159 // Utility function to create a buffer for the SPI bus

   160 	{

   161 	aBuf = new TConfigSpiBufV01();

   162 	if(aBuf==NULL)

   163 		return KErrNoMemory;

   164 	TConfigSpiV01 *buf = &((*aBuf)());

   165 	buf->iWordWidth = aWordWidth;

   166 	buf->iClkSpeedHz = aClkSpeedHz;

   167 	buf->iClkMode = aClkMode;

   168 	buf->iTimeoutPeriod = aTimeoutPeriod;

   169 	buf->iEndianness = aEndianness;

   170 	buf->iBitOrder = aBitOrder;

   171 	buf->iTransactionWaitCycles = aTransactionWaitCycles;

   172 	buf->iSSPinActiveMode = aSSPinActiveMode;

   173 	return KErrNone;

   174 	}

   176 inline static TInt CreateI2cBuf(TConfigI2cBufV01*& aBuf,

   177 								TI2cAddrType	aAddrType,

   178 								TInt32			aClkSpeedHz,

   179 								TEndianness		aEndianness,

   180 								TInt32			aTimeoutPeriod)

   181 // Utility function to create a buffer for the I2C bus

   182 	{

   183 	aBuf = new TConfigI2cBufV01();

   184 	if(aBuf==NULL)

   185 		return KErrNoMemory;

   186 	TConfigI2cV01 *buf = &((*aBuf)());

   187 	buf->iAddrType = aAddrType;

   188 	buf->iClkSpeedHz = aClkSpeedHz;

   189 	buf->iEndianness = aEndianness;

   190 	buf->iTimeoutPeriod = aTimeoutPeriod;

   191 	return KErrNone;

   192 	}

   194 //

   195 // Enumerations for channel type and channel duplex defined in kernel-side class DIicBusChannel

   196 // duplicated for temporary test

   197 enum TChannelType

   198 	{

   199 	EMaster			= 0,

   200 	ESlave			= 0x01,

   201 	EMasterSlave	= 0x02,

   202 	EInvalidType

   203 	};

   204 enum TChannelDuplex

   205 	{

   206 	EHalfDuplex = 0,	// supports only half duplex transactions (even if bus spec supports full duplex)

   207 	EFullDuplex = 0x1,	// supports full duplex transactions (queud transactions may still be half duplex)

   208 	EInvalidDuplex

   209 	};

   210 //

   211 // Bus realisation configuration

   212 //

   213 // 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10  9  8 |  7  6  5  4 |  3  2  1  0

   214 //

   215 // 31:29 - HS Master address (I2C only)

   216 // 28    - HS address valid bit

   217 // 27:23 - Reserved

   218 // 22:20 - Bus type

   219 // 19:15 - Channel number

   220 // 14:10 - Transaction speed

   221 //  9:0  - Slave address

   222 #define HS_MASTER_ADDR_SHIFT 29

   223 #define HS_MASTER_ADDR_MASK 0x7

   224 #define HS_ADDR_VALID_SHIFT 28

   225 #define HS_ADDR_VALID_MASK 0x1

   226 #define BUS_TYPE_SHIFT 20

   227 #define BUS_TYPE_MASK 0x7

   228 #define CHANNEL_NO_SHIFT 15

   229 #define CHANNEL_NO_MASK 0x1F

   230 #define TRANS_SPEED_SHIFT 10

   231 #define TRANS_SPEED_MASK 0x1F

   232 #define SLAVE_ADDR_SHIFT 0

   233 #define SLAVE_ADDR_MASK 0x3FF

   234 //

   235 // Macros to access fields within Bus Realisation Configuration data, used on a per-transaction basis with IIC

   236 #define SET_CONFIG_FIELD(aBusId,aField,aMask,aShift) aBusId=(aBusId&~(aMask<<aShift))|((aField&aMask)<<aShift);

   237 #define GET_CONFIG_FIELD(aBusId,aMask,aShift) (((aBusId)>>(aShift))&(aMask))

   239 #define GET_HS_MASTER_ADDR(aBusId) GET_CONFIG_FIELD(aBusId,HS_MASTER_ADDR_MASK,HS_MASTER_ADDR_SHIFT)

   240 #define SET_HS_MASTER_ADDR(aBusId,aHsMasterAddr) SET_CONFIG_FIELD(aBusId,aHsMasterAddr,HS_MASTER_ADDR_MASK,HS_MASTER_ADDR_SHIFT)

   241 #define GET_HS_VALID(aBusId) GET_CONFIG_FIELD(aBusId,HS_ADDR_VALID_MASK,HS_ADDR_VALID_SHIFT)

   242 #define SET_HS_VALID(aBusId,aHsValid) SET_CONFIG_FIELD(aBusId,aHsValid,HS_ADDR_VALID_MASK,HS_ADDR_VALID_SHIFT)

   243 #define GET_BUS_TYPE(aBusId) GET_CONFIG_FIELD(aBusId,BUS_TYPE_MASK,BUS_TYPE_SHIFT)

   244 #define SET_BUS_TYPE(aBusId,aBusType) SET_CONFIG_FIELD(aBusId,aBusType,BUS_TYPE_MASK,BUS_TYPE_SHIFT)

   245 #define GET_CHAN_NUM(aBusId) GET_CONFIG_FIELD(aBusId,CHANNEL_NO_MASK,CHANNEL_NO_SHIFT)

   246 #define SET_CHAN_NUM(aBusId,aChanNum) SET_CONFIG_FIELD(aBusId,aChanNum,CHANNEL_NO_MASK,CHANNEL_NO_SHIFT)

   247 #define SET_TRANS_SPEED(aBusId,aTransSpeed) SET_CONFIG_FIELD(aBusId,aTransSpeed,TRANS_SPEED_MASK,TRANS_SPEED_SHIFT)

   248 #define GET_TRANS_SPEED(aBusId) GET_CONFIG_FIELD(aBusId,TRANS_SPEED_MASK,TRANS_SPEED_SHIFT)

   249 #define SET_SLAVE_ADDR(aBusId,aSlaveAddr) SET_CONFIG_FIELD(aBusId,aSlaveAddr,SLAVE_ADDR_MASK,SLAVE_ADDR_SHIFT)

   250 #define GET_SLAVE_ADDR(aBusId) GET_CONFIG_FIELD(aBusId,SLAVE_ADDR_MASK,SLAVE_ADDR_SHIFT)

   252 static const TUint8 KTransactionWithPreamble = 0x80;

   253 static const TUint8 KTransactionWithMultiTransc = 0x40;

   255 enum TIicBusSlaveTrigger

   256 	{

   257 	ERxAllBytes			= 0x01,

   258 	ERxUnderrun			= 0x02,

   259 	ERxOverrun			= 0x04,

   260 	ETxAllBytes			= 0x08,

   261 	ETxUnderrun			= 0x10,

   262 	ETxOverrun			= 0x20,

   263 	EGeneralBusError	= 0x40,

   264 	EAsyncCaptChan		= 0x80

   265 	};

   267 #endif // #ifndef __KERNEL_MODE__

   269 //

   270 // User-Side abbreviation of kernel side classes TIicBusTransfer and TIicBusTransaction

   271 //

   272 struct TUsideTferDesc

   273 	{

   274 	TInt8 iType;			// as one of TReqType

   275 	TInt8 iBufGranularity;	// width of a transfer word in bits

   276 	TDes8* iBuffer;	// the data for this transfer (packed into 8-bit words with padding)

   277 	TUsideTferDesc* iNext;

   278 	};

   280 struct TUsideTracnDesc

   281 	{

   282 	TBusType iType;

   283 	TDes8* iHeader;

   284 	TUsideTferDesc* iHalfDuplexTrans;

   285 	TUsideTferDesc* iFullDuplexTrans;

   286 	TUint8 iFlags;				// used to indicate if it supports a preamble

   287 	TAny* iPreambleArg;			// used for preamble argument

   288 	TAny* iMultiTranscArg;		// used for multi transc argument

   289 	};

   291 class RBusDevIicClient : public RBusLogicalChannel

   292 	{

   293     public:

   294 	enum TControl

   295 		{

   296 // Master mode operations

   297 		EQTransSync=1,						/**< Queue Transaction (Synchronous version)					*/

   298 // Slave mode operations

   299 		EInitSlaveClient,					/**< Instigate Slave initialisation required to support testing	*/

   300 		ECaptureChanSync,					/**< Capture Channel (Synchronous version)						*/

   301 		EReleaseChan,						/**< ReleaseChannel												*/

   302 		ERegisterRxBuffer,					/**< Register a buffer for receiving data						*/

   303 		ERegisterTxBuffer,					/**< Register a buffer for transmitting data					*/

   304 		ESetNotifTrigger					/**< Set the notification triggers                               */

   305 		};

   307 	enum TStaticExt

   308 		{

   309 		ECtlIoNone = 0,

   310 		ECtlIoDumpChan = 1, // KCtrlIoDumpChan - defined only for UDEB

   311 // ControlIO codes for Master follow

   312 		ECtlIoBlockReqCompletion=(KTestMasterControlIo+KTestControlIoPilOffset),

   313 		ECtlIoUnblockReqCompletion,

   314 		ECtlIoDeRegChan,

   315 		ECtlIoTracnOne,

   316 		ECtlIoPriorityTest,

   317 		EGetTestResult,

   318 		ECtlIoSetTimeOutFlag,

   319 		ECtlIoTestFullDuplexTrans,

   320 // ControlIO codes for Slave follow

   321 		ECtrlIoRxWords=(KTestSlaveControlIo+KTestControlIoPilOffset),

   322 		ECtrlIoTxWords,

   323 		ECtrlIoRxTxWords,

   324 		ECtrlIoTxChkBuf,

   325 		ECtlIoBusError,

   326 		ECtrlIoBlockNotification,

   327 		ECtrlIoUnblockNotification,

   328 		ECtrlIoUpdTimeout,

   329 		ECtrlIoNotifNoTrigger

   330 		};

   332 	enum TTestFullDuplexTrans

   333 		{

   334 		ETestValidFullDuplexTrans=1,

   335 		ETestInvalidFullDuplexTrans1,

   336 		ETestInvalidFullDuplexTrans2,

   337 		ETestLastNodeFullDuplexTrans,

   338 		ETestDiffNodeNoFullDuplexTrans,

   339 		ETestNone

   340 		};

   342 	enum TRequest

   343 		{

   344 // Master mode operations

   345 		EQTransAsync=1,						/**< Queue Transaction (Asynchronous version)					*/

   346 		ECtrlIoTestBufReUse,

   347 // Slave mode operations

   348 		ECaptureChanAsync,					/**< Capture Channel (Asynchronous version)						*/

   349 		ECtrlIoOvUndRunRxTx

   350 		};

   352 	enum TTestMessages

   353 	    {

   354 	    ETestIicChannelInlineFunc=KTestControlUnitTestOffset

   355 	    };

   357 #ifndef __KERNEL_MODE__

   358 	public:

   359 	inline TInt TestIiicChannelInlineFunc(){return DoControl (ETestIicChannelInlineFunc, NULL, NULL);}

   360 	// Master mode functions

   361 	inline TInt Open(TDesC& aProxyName) {return (DoCreate(aProxyName,TVersion(KIicClientMajorVersionNumber,KIicClientMinorVersionNumber,KIicClientBuildVersionNumber),-1,NULL,NULL,EOwnerThread));}

   363 	inline TInt QueueTransaction(TInt aBusId, TUsideTracnDesc* aTransaction) {return(DoControl(EQTransSync,(TAny*)aBusId,(TAny*)aTransaction));}

   365 	inline void QueueTransaction(TRequestStatus& aStatus, TInt aBusId, TUsideTracnDesc* aTransaction) {DoRequest(EQTransAsync,aStatus,(TAny*)aBusId,(TAny*)aTransaction);}

   367 	inline void CancelAsyncOperation(TRequestStatus* aStatus, TInt aBusId)	{TInt* parms[2]; parms[0]=(TInt*)aStatus; parms[1]=(TInt*)aBusId;DoCancel((TInt)&parms[0]);}

   369 	// Slave mode functions

   370 	inline TInt InitSlaveClient() {return(DoControl(EInitSlaveClient,NULL,NULL));}

   371 	inline TInt CaptureChannel(TInt aBusId, TDes8* aConfigHdr, TInt& aChannelId) {TInt* parms[2]; parms[0]=(TInt*)aBusId; parms[1]=&aChannelId;return(DoControl(ECaptureChanSync,(TAny*)aConfigHdr,(TAny*)(&parms[0])));}

   373 	inline TInt CaptureChannel(TInt aBusId, TDes8* aConfigHdr, TInt& aChannelId, TRequestStatus& aStatus) {TInt* parms[2]; parms[0]=(TInt*)aBusId; parms[1]=&aChannelId;DoRequest(ECaptureChanAsync,aStatus,(TAny*)aConfigHdr,(TAny*)(&parms[0]));return KErrNone;}

   375 	inline TInt ReleaseChannel(TInt aChannelId){return(DoControl(EReleaseChan,(TAny*)aChannelId,NULL));};

   376 	inline TInt RegisterRxBuffer(TInt aChannelId, TInt8 aBufGranularity, TInt8 aNumWords, TInt8 aOffset){TInt8 parms[3]; parms[0]=aBufGranularity; parms[1]=aNumWords; parms[2]=aOffset;return(DoControl(ERegisterRxBuffer,(TAny*)aChannelId,(TAny*)(&parms[0])));};

   377 	inline TInt RegisterTxBuffer(TInt aChannelId, TInt8 aBufGranularity, TInt8 aNumWords, TInt8 aOffset){TInt8 parms[3]; parms[0]=aBufGranularity; parms[1]=aNumWords; parms[2]=aOffset;return(DoControl(ERegisterTxBuffer,(TAny*)aChannelId,(TAny*)(&parms[0])));};

   378 	inline TInt SetNotificationTrigger(TInt aChannelId, TInt aTrigger, TRequestStatus* aStatus){TInt parms[2]; parms[0]=aChannelId; parms[1]=aTrigger;return(DoControl(ESetNotifTrigger,(TAny*)aStatus,(TAny*)(&parms[0])));};

   380 	// ControlIO functions follow

   381 	inline TInt BlockReqCompletion(TInt aBusId) {return(DoControl(ECtlIoBlockReqCompletion,(TAny*)aBusId));}

   382 	inline TInt UnblockReqCompletion(TInt aBusId) {return(DoControl(ECtlIoUnblockReqCompletion,(TAny*)aBusId));}

   383 	inline TInt DeRegisterChan(TInt aBusId) {return(DoControl(ECtlIoDeRegChan,(TAny*)aBusId));}

   384 	inline TInt TestTracnOne(TInt aBusId) {return(DoControl(ECtlIoTracnOne, (TAny*)aBusId));}

   385 	inline TInt SetTimeOutFlag(TInt aBusId){return(DoControl(ECtlIoSetTimeOutFlag,(TAny*)aBusId));}

   386 	inline TInt CancelTimeOutFlag(TInt aBusId){return(DoControl(ECtlIoNone,(TAny*)aBusId));}

   387 	inline TInt TestPriority(TInt aBusId) {return(DoControl(ECtlIoPriorityTest, (TAny*)aBusId));}

   389 	inline TInt TestValidFullDuplexTrans(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestValidFullDuplexTrans));}

   390 	inline TInt TestInvalidFullDuplexTrans1(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestInvalidFullDuplexTrans1));}

   391 	inline TInt TestInvalidFullDuplexTrans2(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestInvalidFullDuplexTrans2));}

   393 	inline TInt TestLastNodeFullDuplexTrans(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestLastNodeFullDuplexTrans));}

   394 	inline TInt TestDiffNodeNumFullDuplexTrans(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestDiffNodeNoFullDuplexTrans));}

   396 	inline void TestBufferReUse(TInt aBusId, TRequestStatus& aStatus) {DoRequest(ECtrlIoTestBufReUse,aStatus,(TAny*)aBusId,NULL);}

   398 	inline TInt SimulateRxNWords(TInt aBusId, TInt aChannelId, TInt aNumWords){TInt parms[2]; parms[0]=aChannelId; parms[1]=aNumWords;return(DoControl(ECtrlIoRxWords,(TAny*)aBusId,(TAny*)(&parms[0])));};

   399 	inline TInt SimulateTxNWords(TInt aBusId, TInt aChannelId, TInt aNumWords){TInt parms[2]; parms[0]=aChannelId; parms[1]=aNumWords;return(DoControl(ECtrlIoTxWords,(TAny*)aBusId,(TAny*)(&parms[0])));};

   400 	inline TInt SimulateRxTxNWords(TInt aBusId, TInt aChannelId, TInt aNumRxWords, TInt aNumTxWords){TInt parms[3]; parms[0]=aChannelId; parms[1]=aNumRxWords; parms[2]=aNumTxWords;return(DoControl(ECtrlIoRxTxWords,(TAny*)aBusId,(TAny*)(&parms[0])));};

   401 	inline TInt SimulateBusErr(TInt aBusId, TInt aChannelId) {return(DoControl(ECtlIoBusError,(TAny*)aBusId,(TAny*)aChannelId));}

   402 	inline TInt BlockNotification(TInt aBusId, TInt aChannelId) {return(DoControl(ECtrlIoBlockNotification,(TAny*)aBusId,(TAny*)aChannelId));}

   403 	inline TInt UnblockNotification(TInt aBusId, TInt aChannelId) {return(DoControl(ECtrlIoUnblockNotification,(TAny*)aBusId,(TAny*)aChannelId));}

   404 	inline TInt UpdateTimeoutValues(TInt aBusId, TInt aChannelId) {return(DoControl(ECtrlIoUpdTimeout,(TAny*)aBusId,(TAny*)aChannelId));}

   405 	inline TInt SetNotifNoTrigger(TInt aChannelId, TInt aTrigger){return(DoControl(ECtrlIoNotifNoTrigger,(TAny*)aChannelId,(TAny*)aTrigger));};

   407 	inline void TestOverrunUnderrun(TInt aBusId, TInt aChannelId, TRequestStatus& aStatus) {DoRequest(ECtrlIoOvUndRunRxTx,aStatus,(TAny*)aBusId,(TAny*)aChannelId);}

   409 #endif

   410 	};

   413 #ifdef __KERNEL_MODE__

   415 // Definition of function prototype for a callback function provided by the PSL

   416 // to be invoked when the part played by the hardware in processing a transfer

   417 // has completed.

   418 typedef void (*THwDoneCbFn)(TAny* );

   420 #endif

   422 // Data used to support tests

   424 // Transaction One

   425 //

   426 const TUint8 KTransOneTferOne[21] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20};

   427 const TUint8 KTransOneTferTwo[8] = {17,18,19,20,21,22,23,24};

   428 const TUint8 KTransOneTferThree[6] = {87,85,83,81,79,77};

   429 const TUint8 KPriorityTestHeader[6] = {0,1,2,3,4,10};

   430 const TInt KPriorityTestPrio[6] = {1,2,3,4,5,0};

   432 const TInt KRxBufSizeInBytes = 64;

   433 const TInt KTxBufSizeInBytes = 64;

   435 #endif

author	sl
	Tue, 10 Jun 2014 14:32:02 +0200
changeset 1	260cb5ec6c19
permissions	-rw-r--r--