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// Copyright (c) 1995-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// e32test\iic\t_iic.h
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//
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#ifndef __T_IIC_H__
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#define __T_IIC_H__
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#include <e32ver.h>
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const TInt KIicClientMajorVersionNumber = 1;
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const TInt KIicClientMinorVersionNumber = 0;
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const TInt KIicClientBuildVersionNumber = KE32BuildVersionNumber;
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const TInt KPriorityTestNum = 6; // 1 blocking transaction + 5 test transactions
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// For IIC,
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// If bit 31 is set and bit 30 cleared it is used to extend the Master-Slave channel;
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// if bit 31 is cleared and bit 30 is set, it extends the Master channel;
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// if both bits 31 and 30 are cleared it extends the Slave channel interface.
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// However,
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// since the kernel-side proxy clients interpret the msb being set as indicative of an
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// asynchronous request, the values here will have the static extension pattern represented
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// in bits 30 and 29, instead. In addition, to support communication with the slave-side proxy,
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// the Slave extension value will be represented as bits 30 and 29 set, so that it can be distinguished
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// from 'normal' synchronous operations.
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//
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const TUint KTestControlIoMask = 0x60000000;
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const TUint KTestMasterControlIo = 0x20000000;
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const TUint KTestSlaveControlIo = 0x60000000;
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const TUint KTestMasterSlaveControlIo = 0x40000000;
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const TUint KTestControlIoPilOffset = 0x00000002; // Corresponds to 1 higher than the number used by PIL
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const TUint KTestControlUnitTestOffset = 0x10000000;
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//
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// Enumerations TReqType and TBusType defined in kernel-side class TIicBusTransfer
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// The user-side test, and the kernel-side proxy client require access to this
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enum TReqType
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{
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EMasterRead,
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EMasterWrite
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};
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enum TBusType
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{
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EI2c = 0,
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ESpi = 0x01,
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EMicrowire = 0x02,
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ECci = 0x03,
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ESccb = 0x04,
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EInvalidBus
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};
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#define MAX_TRANS_LENGTH 20
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#ifndef __KERNEL_MODE__
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//
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// For convenience, selected kernel-side information is replicated here
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// to allow the user-side test to populate buffers accordingly
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//
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// Bus-specific configuration
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//
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enum TEndianness
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{
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EBigEndian,
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ELittleEndian
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};
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enum TBitOrder
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{
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ELsbFirst,
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EMsbFirst
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};
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//
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// Bus-specific configuration for SPI bus
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//
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enum TSpiWordWidth
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{
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ESpiWordWidth_8,
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ESpiWordWidth_10,
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ESpiWordWidth_12,
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ESpiWordWidth_16
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};
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enum TSpiClkMode
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{
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ESpiPolarityLowRisingEdge, // Active high, odd edges
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ESpiPolarityLowFallingEdge, // Active high, even edges
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ESpiPolarityHighFallingEdge, // Active low, odd edges
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ESpiPolarityHighRisingEdge // Active low, even edges
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};
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enum TSpiSsPinMode
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{
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ESpiCSPinActiveLow, // Active low
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ESpiCSPinActiveHigh // Active high
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};
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class TConfigSpiV01
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{
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public:
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TSpiWordWidth iWordWidth;
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TInt32 iClkSpeedHz;
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TSpiClkMode iClkMode;
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TInt32 iTimeoutPeriod;
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TEndianness iEndianness;
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TBitOrder iBitOrder;
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TUint iTransactionWaitCycles;
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TSpiSsPinMode iSSPinActiveMode;
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};
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typedef TPckgBuf <TConfigSpiV01> TConfigSpiBufV01;
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//
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// Bus-specific configuration for I2C bus
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//
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enum TI2cAddrType
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{
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EI2cAddr7Bit,
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EI2cAddr10Bit
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};
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class TConfigI2cV01
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{
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public:
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TI2cAddrType iAddrType; // 7 or 10-bit addressing
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TInt32 iClkSpeedHz;
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TEndianness iEndianness;
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TInt32 iTimeoutPeriod;
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};
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typedef TPckgBuf <TConfigI2cV01> TConfigI2cBufV01;
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inline static TInt CreateSpiBuf(TConfigSpiBufV01*& aBuf,
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TSpiWordWidth aWordWidth,
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TInt32 aClkSpeedHz,
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TSpiClkMode aClkMode,
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TInt32 aTimeoutPeriod,
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TEndianness aEndianness,
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TBitOrder aBitOrder,
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TUint aTransactionWaitCycles,
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TSpiSsPinMode aSSPinActiveMode)
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// Utility function to create a buffer for the SPI bus
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{
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aBuf = new TConfigSpiBufV01();
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if(aBuf==NULL)
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return KErrNoMemory;
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TConfigSpiV01 *buf = &((*aBuf)());
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buf->iWordWidth = aWordWidth;
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buf->iClkSpeedHz = aClkSpeedHz;
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buf->iClkMode = aClkMode;
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buf->iTimeoutPeriod = aTimeoutPeriod;
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buf->iEndianness = aEndianness;
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buf->iBitOrder = aBitOrder;
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buf->iTransactionWaitCycles = aTransactionWaitCycles;
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buf->iSSPinActiveMode = aSSPinActiveMode;
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return KErrNone;
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}
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inline static TInt CreateI2cBuf(TConfigI2cBufV01*& aBuf,
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TI2cAddrType aAddrType,
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TInt32 aClkSpeedHz,
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TEndianness aEndianness,
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TInt32 aTimeoutPeriod)
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// Utility function to create a buffer for the I2C bus
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{
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aBuf = new TConfigI2cBufV01();
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if(aBuf==NULL)
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return KErrNoMemory;
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TConfigI2cV01 *buf = &((*aBuf)());
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buf->iAddrType = aAddrType;
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buf->iClkSpeedHz = aClkSpeedHz;
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buf->iEndianness = aEndianness;
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buf->iTimeoutPeriod = aTimeoutPeriod;
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return KErrNone;
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}
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//
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// Enumerations for channel type and channel duplex defined in kernel-side class DIicBusChannel
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// duplicated for temporary test
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enum TChannelType
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{
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EMaster = 0,
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ESlave = 0x01,
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EMasterSlave = 0x02,
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EInvalidType
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};
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enum TChannelDuplex
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{
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EHalfDuplex = 0, // supports only half duplex transactions (even if bus spec supports full duplex)
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EFullDuplex = 0x1, // supports full duplex transactions (queud transactions may still be half duplex)
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EInvalidDuplex
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};
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//
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// Bus realisation configuration
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//
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// 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0
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//
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// 31:29 - HS Master address (I2C only)
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// 28 - HS address valid bit
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// 27:23 - Reserved
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// 22:20 - Bus type
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// 19:15 - Channel number
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// 14:10 - Transaction speed
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// 9:0 - Slave address
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#define HS_MASTER_ADDR_SHIFT 29
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#define HS_MASTER_ADDR_MASK 0x7
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#define HS_ADDR_VALID_SHIFT 28
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#define HS_ADDR_VALID_MASK 0x1
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#define BUS_TYPE_SHIFT 20
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#define BUS_TYPE_MASK 0x7
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#define CHANNEL_NO_SHIFT 15
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#define CHANNEL_NO_MASK 0x1F
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#define TRANS_SPEED_SHIFT 10
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#define TRANS_SPEED_MASK 0x1F
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#define SLAVE_ADDR_SHIFT 0
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#define SLAVE_ADDR_MASK 0x3FF
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//
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// Macros to access fields within Bus Realisation Configuration data, used on a per-transaction basis with IIC
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#define SET_CONFIG_FIELD(aBusId,aField,aMask,aShift) aBusId=(aBusId&~(aMask<<aShift))|((aField&aMask)<<aShift);
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#define GET_CONFIG_FIELD(aBusId,aMask,aShift) (((aBusId)>>(aShift))&(aMask))
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#define GET_HS_MASTER_ADDR(aBusId) GET_CONFIG_FIELD(aBusId,HS_MASTER_ADDR_MASK,HS_MASTER_ADDR_SHIFT)
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#define SET_HS_MASTER_ADDR(aBusId,aHsMasterAddr) SET_CONFIG_FIELD(aBusId,aHsMasterAddr,HS_MASTER_ADDR_MASK,HS_MASTER_ADDR_SHIFT)
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#define GET_HS_VALID(aBusId) GET_CONFIG_FIELD(aBusId,HS_ADDR_VALID_MASK,HS_ADDR_VALID_SHIFT)
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#define SET_HS_VALID(aBusId,aHsValid) SET_CONFIG_FIELD(aBusId,aHsValid,HS_ADDR_VALID_MASK,HS_ADDR_VALID_SHIFT)
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#define GET_BUS_TYPE(aBusId) GET_CONFIG_FIELD(aBusId,BUS_TYPE_MASK,BUS_TYPE_SHIFT)
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#define SET_BUS_TYPE(aBusId,aBusType) SET_CONFIG_FIELD(aBusId,aBusType,BUS_TYPE_MASK,BUS_TYPE_SHIFT)
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#define GET_CHAN_NUM(aBusId) GET_CONFIG_FIELD(aBusId,CHANNEL_NO_MASK,CHANNEL_NO_SHIFT)
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#define SET_CHAN_NUM(aBusId,aChanNum) SET_CONFIG_FIELD(aBusId,aChanNum,CHANNEL_NO_MASK,CHANNEL_NO_SHIFT)
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#define SET_TRANS_SPEED(aBusId,aTransSpeed) SET_CONFIG_FIELD(aBusId,aTransSpeed,TRANS_SPEED_MASK,TRANS_SPEED_SHIFT)
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#define GET_TRANS_SPEED(aBusId) GET_CONFIG_FIELD(aBusId,TRANS_SPEED_MASK,TRANS_SPEED_SHIFT)
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#define SET_SLAVE_ADDR(aBusId,aSlaveAddr) SET_CONFIG_FIELD(aBusId,aSlaveAddr,SLAVE_ADDR_MASK,SLAVE_ADDR_SHIFT)
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#define GET_SLAVE_ADDR(aBusId) GET_CONFIG_FIELD(aBusId,SLAVE_ADDR_MASK,SLAVE_ADDR_SHIFT)
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static const TUint8 KTransactionWithPreamble = 0x80;
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static const TUint8 KTransactionWithMultiTransc = 0x40;
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enum TIicBusSlaveTrigger
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{
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ERxAllBytes = 0x01,
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ERxUnderrun = 0x02,
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ERxOverrun = 0x04,
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ETxAllBytes = 0x08,
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ETxUnderrun = 0x10,
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ETxOverrun = 0x20,
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EGeneralBusError = 0x40,
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EAsyncCaptChan = 0x80
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};
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#endif // #ifndef __KERNEL_MODE__
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//
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// User-Side abbreviation of kernel side classes TIicBusTransfer and TIicBusTransaction
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//
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struct TUsideTferDesc
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{
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TInt8 iType; // as one of TReqType
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TInt8 iBufGranularity; // width of a transfer word in bits
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TDes8* iBuffer; // the data for this transfer (packed into 8-bit words with padding)
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TUsideTferDesc* iNext;
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};
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struct TUsideTracnDesc
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{
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TBusType iType;
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|
sl@0
|
283 |
TDes8* iHeader;
|
|
sl@0
|
284 |
TUsideTferDesc* iHalfDuplexTrans;
|
|
sl@0
|
285 |
TUsideTferDesc* iFullDuplexTrans;
|
|
sl@0
|
286 |
TUint8 iFlags; // used to indicate if it supports a preamble
|
|
sl@0
|
287 |
TAny* iPreambleArg; // used for preamble argument
|
|
sl@0
|
288 |
TAny* iMultiTranscArg; // used for multi transc argument
|
|
sl@0
|
289 |
};
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|
sl@0
|
290 |
|
|
sl@0
|
291 |
class RBusDevIicClient : public RBusLogicalChannel
|
|
sl@0
|
292 |
{
|
|
sl@0
|
293 |
public:
|
|
sl@0
|
294 |
enum TControl
|
|
sl@0
|
295 |
{
|
|
sl@0
|
296 |
// Master mode operations
|
|
sl@0
|
297 |
EQTransSync=1, /**< Queue Transaction (Synchronous version) */
|
|
sl@0
|
298 |
// Slave mode operations
|
|
sl@0
|
299 |
EInitSlaveClient, /**< Instigate Slave initialisation required to support testing */
|
|
sl@0
|
300 |
ECaptureChanSync, /**< Capture Channel (Synchronous version) */
|
|
sl@0
|
301 |
EReleaseChan, /**< ReleaseChannel */
|
|
sl@0
|
302 |
ERegisterRxBuffer, /**< Register a buffer for receiving data */
|
|
sl@0
|
303 |
ERegisterTxBuffer, /**< Register a buffer for transmitting data */
|
|
sl@0
|
304 |
ESetNotifTrigger /**< Set the notification triggers */
|
|
sl@0
|
305 |
};
|
|
sl@0
|
306 |
|
|
sl@0
|
307 |
enum TStaticExt
|
|
sl@0
|
308 |
{
|
|
sl@0
|
309 |
ECtlIoNone = 0,
|
|
sl@0
|
310 |
ECtlIoDumpChan = 1, // KCtrlIoDumpChan - defined only for UDEB
|
|
sl@0
|
311 |
// ControlIO codes for Master follow
|
|
sl@0
|
312 |
ECtlIoBlockReqCompletion=(KTestMasterControlIo+KTestControlIoPilOffset),
|
|
sl@0
|
313 |
ECtlIoUnblockReqCompletion,
|
|
sl@0
|
314 |
ECtlIoDeRegChan,
|
|
sl@0
|
315 |
ECtlIoTracnOne,
|
|
sl@0
|
316 |
ECtlIoPriorityTest,
|
|
sl@0
|
317 |
EGetTestResult,
|
|
sl@0
|
318 |
ECtlIoSetTimeOutFlag,
|
|
sl@0
|
319 |
ECtlIoTestFullDuplexTrans,
|
|
sl@0
|
320 |
// ControlIO codes for Slave follow
|
|
sl@0
|
321 |
ECtrlIoRxWords=(KTestSlaveControlIo+KTestControlIoPilOffset),
|
|
sl@0
|
322 |
ECtrlIoTxWords,
|
|
sl@0
|
323 |
ECtrlIoRxTxWords,
|
|
sl@0
|
324 |
ECtrlIoTxChkBuf,
|
|
sl@0
|
325 |
ECtlIoBusError,
|
|
sl@0
|
326 |
ECtrlIoBlockNotification,
|
|
sl@0
|
327 |
ECtrlIoUnblockNotification,
|
|
sl@0
|
328 |
ECtrlIoUpdTimeout,
|
|
sl@0
|
329 |
ECtrlIoNotifNoTrigger
|
|
sl@0
|
330 |
};
|
|
sl@0
|
331 |
|
|
sl@0
|
332 |
enum TTestFullDuplexTrans
|
|
sl@0
|
333 |
{
|
|
sl@0
|
334 |
ETestValidFullDuplexTrans=1,
|
|
sl@0
|
335 |
ETestInvalidFullDuplexTrans1,
|
|
sl@0
|
336 |
ETestInvalidFullDuplexTrans2,
|
|
sl@0
|
337 |
ETestLastNodeFullDuplexTrans,
|
|
sl@0
|
338 |
ETestDiffNodeNoFullDuplexTrans,
|
|
sl@0
|
339 |
ETestNone
|
|
sl@0
|
340 |
};
|
|
sl@0
|
341 |
|
|
sl@0
|
342 |
enum TRequest
|
|
sl@0
|
343 |
{
|
|
sl@0
|
344 |
// Master mode operations
|
|
sl@0
|
345 |
EQTransAsync=1, /**< Queue Transaction (Asynchronous version) */
|
|
sl@0
|
346 |
ECtrlIoTestBufReUse,
|
|
sl@0
|
347 |
// Slave mode operations
|
|
sl@0
|
348 |
ECaptureChanAsync, /**< Capture Channel (Asynchronous version) */
|
|
sl@0
|
349 |
ECtrlIoOvUndRunRxTx
|
|
sl@0
|
350 |
};
|
|
sl@0
|
351 |
|
|
sl@0
|
352 |
enum TTestMessages
|
|
sl@0
|
353 |
{
|
|
sl@0
|
354 |
ETestIicChannelInlineFunc=KTestControlUnitTestOffset
|
|
sl@0
|
355 |
};
|
|
sl@0
|
356 |
|
|
sl@0
|
357 |
#ifndef __KERNEL_MODE__
|
|
sl@0
|
358 |
public:
|
|
sl@0
|
359 |
inline TInt TestIiicChannelInlineFunc(){return DoControl (ETestIicChannelInlineFunc, NULL, NULL);}
|
|
sl@0
|
360 |
// Master mode functions
|
|
sl@0
|
361 |
inline TInt Open(TDesC& aProxyName) {return (DoCreate(aProxyName,TVersion(KIicClientMajorVersionNumber,KIicClientMinorVersionNumber,KIicClientBuildVersionNumber),-1,NULL,NULL,EOwnerThread));}
|
|
sl@0
|
362 |
|
|
sl@0
|
363 |
inline TInt QueueTransaction(TInt aBusId, TUsideTracnDesc* aTransaction) {return(DoControl(EQTransSync,(TAny*)aBusId,(TAny*)aTransaction));}
|
|
sl@0
|
364 |
|
|
sl@0
|
365 |
inline void QueueTransaction(TRequestStatus& aStatus, TInt aBusId, TUsideTracnDesc* aTransaction) {DoRequest(EQTransAsync,aStatus,(TAny*)aBusId,(TAny*)aTransaction);}
|
|
sl@0
|
366 |
|
|
sl@0
|
367 |
inline void CancelAsyncOperation(TRequestStatus* aStatus, TInt aBusId) {TInt* parms[2]; parms[0]=(TInt*)aStatus; parms[1]=(TInt*)aBusId;DoCancel((TInt)&parms[0]);}
|
|
sl@0
|
368 |
|
|
sl@0
|
369 |
// Slave mode functions
|
|
sl@0
|
370 |
inline TInt InitSlaveClient() {return(DoControl(EInitSlaveClient,NULL,NULL));}
|
|
sl@0
|
371 |
inline TInt CaptureChannel(TInt aBusId, TDes8* aConfigHdr, TInt& aChannelId) {TInt* parms[2]; parms[0]=(TInt*)aBusId; parms[1]=&aChannelId;return(DoControl(ECaptureChanSync,(TAny*)aConfigHdr,(TAny*)(&parms[0])));}
|
|
sl@0
|
372 |
|
|
sl@0
|
373 |
inline TInt CaptureChannel(TInt aBusId, TDes8* aConfigHdr, TInt& aChannelId, TRequestStatus& aStatus) {TInt* parms[2]; parms[0]=(TInt*)aBusId; parms[1]=&aChannelId;DoRequest(ECaptureChanAsync,aStatus,(TAny*)aConfigHdr,(TAny*)(&parms[0]));return KErrNone;}
|
|
sl@0
|
374 |
|
|
sl@0
|
375 |
inline TInt ReleaseChannel(TInt aChannelId){return(DoControl(EReleaseChan,(TAny*)aChannelId,NULL));};
|
|
sl@0
|
376 |
inline TInt RegisterRxBuffer(TInt aChannelId, TInt8 aBufGranularity, TInt8 aNumWords, TInt8 aOffset){TInt8 parms[3]; parms[0]=aBufGranularity; parms[1]=aNumWords; parms[2]=aOffset;return(DoControl(ERegisterRxBuffer,(TAny*)aChannelId,(TAny*)(&parms[0])));};
|
|
sl@0
|
377 |
inline TInt RegisterTxBuffer(TInt aChannelId, TInt8 aBufGranularity, TInt8 aNumWords, TInt8 aOffset){TInt8 parms[3]; parms[0]=aBufGranularity; parms[1]=aNumWords; parms[2]=aOffset;return(DoControl(ERegisterTxBuffer,(TAny*)aChannelId,(TAny*)(&parms[0])));};
|
|
sl@0
|
378 |
inline TInt SetNotificationTrigger(TInt aChannelId, TInt aTrigger, TRequestStatus* aStatus){TInt parms[2]; parms[0]=aChannelId; parms[1]=aTrigger;return(DoControl(ESetNotifTrigger,(TAny*)aStatus,(TAny*)(&parms[0])));};
|
|
sl@0
|
379 |
|
|
sl@0
|
380 |
// ControlIO functions follow
|
|
sl@0
|
381 |
inline TInt BlockReqCompletion(TInt aBusId) {return(DoControl(ECtlIoBlockReqCompletion,(TAny*)aBusId));}
|
|
sl@0
|
382 |
inline TInt UnblockReqCompletion(TInt aBusId) {return(DoControl(ECtlIoUnblockReqCompletion,(TAny*)aBusId));}
|
|
sl@0
|
383 |
inline TInt DeRegisterChan(TInt aBusId) {return(DoControl(ECtlIoDeRegChan,(TAny*)aBusId));}
|
|
sl@0
|
384 |
inline TInt TestTracnOne(TInt aBusId) {return(DoControl(ECtlIoTracnOne, (TAny*)aBusId));}
|
|
sl@0
|
385 |
inline TInt SetTimeOutFlag(TInt aBusId){return(DoControl(ECtlIoSetTimeOutFlag,(TAny*)aBusId));}
|
|
sl@0
|
386 |
inline TInt CancelTimeOutFlag(TInt aBusId){return(DoControl(ECtlIoNone,(TAny*)aBusId));}
|
|
sl@0
|
387 |
inline TInt TestPriority(TInt aBusId) {return(DoControl(ECtlIoPriorityTest, (TAny*)aBusId));}
|
|
sl@0
|
388 |
|
|
sl@0
|
389 |
inline TInt TestValidFullDuplexTrans(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestValidFullDuplexTrans));}
|
|
sl@0
|
390 |
inline TInt TestInvalidFullDuplexTrans1(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestInvalidFullDuplexTrans1));}
|
|
sl@0
|
391 |
inline TInt TestInvalidFullDuplexTrans2(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestInvalidFullDuplexTrans2));}
|
|
sl@0
|
392 |
|
|
sl@0
|
393 |
inline TInt TestLastNodeFullDuplexTrans(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestLastNodeFullDuplexTrans));}
|
|
sl@0
|
394 |
inline TInt TestDiffNodeNumFullDuplexTrans(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestDiffNodeNoFullDuplexTrans));}
|
|
sl@0
|
395 |
|
|
sl@0
|
396 |
inline void TestBufferReUse(TInt aBusId, TRequestStatus& aStatus) {DoRequest(ECtrlIoTestBufReUse,aStatus,(TAny*)aBusId,NULL);}
|
|
sl@0
|
397 |
|
|
sl@0
|
398 |
inline TInt SimulateRxNWords(TInt aBusId, TInt aChannelId, TInt aNumWords){TInt parms[2]; parms[0]=aChannelId; parms[1]=aNumWords;return(DoControl(ECtrlIoRxWords,(TAny*)aBusId,(TAny*)(&parms[0])));};
|
|
sl@0
|
399 |
inline TInt SimulateTxNWords(TInt aBusId, TInt aChannelId, TInt aNumWords){TInt parms[2]; parms[0]=aChannelId; parms[1]=aNumWords;return(DoControl(ECtrlIoTxWords,(TAny*)aBusId,(TAny*)(&parms[0])));};
|
|
sl@0
|
400 |
inline TInt SimulateRxTxNWords(TInt aBusId, TInt aChannelId, TInt aNumRxWords, TInt aNumTxWords){TInt parms[3]; parms[0]=aChannelId; parms[1]=aNumRxWords; parms[2]=aNumTxWords;return(DoControl(ECtrlIoRxTxWords,(TAny*)aBusId,(TAny*)(&parms[0])));};
|
|
sl@0
|
401 |
inline TInt SimulateBusErr(TInt aBusId, TInt aChannelId) {return(DoControl(ECtlIoBusError,(TAny*)aBusId,(TAny*)aChannelId));}
|
|
sl@0
|
402 |
inline TInt BlockNotification(TInt aBusId, TInt aChannelId) {return(DoControl(ECtrlIoBlockNotification,(TAny*)aBusId,(TAny*)aChannelId));}
|
|
sl@0
|
403 |
inline TInt UnblockNotification(TInt aBusId, TInt aChannelId) {return(DoControl(ECtrlIoUnblockNotification,(TAny*)aBusId,(TAny*)aChannelId));}
|
|
sl@0
|
404 |
inline TInt UpdateTimeoutValues(TInt aBusId, TInt aChannelId) {return(DoControl(ECtrlIoUpdTimeout,(TAny*)aBusId,(TAny*)aChannelId));}
|
|
sl@0
|
405 |
inline TInt SetNotifNoTrigger(TInt aChannelId, TInt aTrigger){return(DoControl(ECtrlIoNotifNoTrigger,(TAny*)aChannelId,(TAny*)aTrigger));};
|
|
sl@0
|
406 |
|
|
sl@0
|
407 |
inline void TestOverrunUnderrun(TInt aBusId, TInt aChannelId, TRequestStatus& aStatus) {DoRequest(ECtrlIoOvUndRunRxTx,aStatus,(TAny*)aBusId,(TAny*)aChannelId);}
|
|
sl@0
|
408 |
|
|
sl@0
|
409 |
#endif
|
|
sl@0
|
410 |
};
|
|
sl@0
|
411 |
|
|
sl@0
|
412 |
|
|
sl@0
|
413 |
#ifdef __KERNEL_MODE__
|
|
sl@0
|
414 |
|
|
sl@0
|
415 |
// Definition of function prototype for a callback function provided by the PSL
|
|
sl@0
|
416 |
// to be invoked when the part played by the hardware in processing a transfer
|
|
sl@0
|
417 |
// has completed.
|
|
sl@0
|
418 |
typedef void (*THwDoneCbFn)(TAny* );
|
|
sl@0
|
419 |
|
|
sl@0
|
420 |
#endif
|
|
sl@0
|
421 |
|
|
sl@0
|
422 |
// Data used to support tests
|
|
sl@0
|
423 |
|
|
sl@0
|
424 |
// Transaction One
|
|
sl@0
|
425 |
//
|
|
sl@0
|
426 |
const TUint8 KTransOneTferOne[21] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20};
|
|
sl@0
|
427 |
const TUint8 KTransOneTferTwo[8] = {17,18,19,20,21,22,23,24};
|
|
sl@0
|
428 |
const TUint8 KTransOneTferThree[6] = {87,85,83,81,79,77};
|
|
sl@0
|
429 |
const TUint8 KPriorityTestHeader[6] = {0,1,2,3,4,10};
|
|
sl@0
|
430 |
const TInt KPriorityTestPrio[6] = {1,2,3,4,5,0};
|
|
sl@0
|
431 |
|
|
sl@0
|
432 |
const TInt KRxBufSizeInBytes = 64;
|
|
sl@0
|
433 |
const TInt KTxBufSizeInBytes = 64;
|
|
sl@0
|
434 |
|
|
sl@0
|
435 |
#endif
|