First public contribution.
2 * Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies).
4 * This component and the accompanying materials are made available
5 * under the terms of the License "Eclipse Public License v1.0"
6 * which accompanies this distribution, and is available
7 * at the URL "http://www.eclipse.org/legal/epl-v10.html".
9 * Initial Contributors:
10 * Nokia Corporation - initial contribution.
20 // Add here a definition for your CPU (list in CONFIG.INC)
26 // Add here a definition for your Memory Model
32 // Macro which generates the names for the binaries for this platform
35 #define VariantTarget(name,ext) _ne1_tb_##name##.##ext
38 #ifndef VariantMediaDefIncludePath
39 #define VariantMediaDefIncludePath /epoc32/include/ne1_tb
42 // Used in MMP files for include paths e.g. to hcrconfig.h header
43 #ifndef VariantIncludePath
44 #define VariantIncludePath /epoc32/include/ne1_tb
48 //Include debug support
49 macro __DEBUGGER_SUPPORT__
54 // If euser is built from the variant, uncomment the following line to build it
55 // as ARM rather than Thumb
57 //#define __BUILD_VARIANT_EUSER_AS_ARM__
61 // To replace some of the generic utility functions with variant specific
62 // versions (eg to replace memcpy with a version optimised for the hardware),
63 // uncomment the two lines below and edit the files in the replacementUtils
66 //#define REPLACE_GENERIC_UTILS
67 //#define VariantReplacementUtilsPath ne1_tb/replacement_utils
71 // Enable BTrace support in release versions of the kernel by adding
72 // the following BTRACE macro declarations
74 macro BTRACE_KERNEL_ALL
78 // Uncomment the following line if using the r1p0 release or later of the ARM1136 processor.
80 //#define __CPU_ARM1136_IS_R1__
83 // Include the following line if default memory mapping should use shared memory.
84 // Should be on for multicore (SMP) devices.
86 macro __CPU_USE_SHARED_MEMORY
88 // Include the following line if CPU cannot tolerate the presence of nonshared
89 // cached memory. This seems to be the case for the ARM11 MPCore - corruption
90 // of data is observed in non-shared cached regions if __CPU_USE_SHARED_MEMORY
93 macro __CPU_FORCE_SHARED_MEMORY_IF_CACHED
99 // Uncomment the next line if using the ARM1136 processor and ARM1136 Erratum 406973
100 // "CLREX instruction might be ignored during data cache line fill"
101 // is fixed on this hardware.
103 //#define __CPU_ARM1136_ERRATUM_406973_FIXED
105 // Uncomment next line if using the ARM1136 processor and ARM1136 Erratum 408022
106 // "Cancelled write to CONTEXTID register might update ASID"
107 // is fixed on this hardware.
109 //#define __CPU_ARM1136_ERRATUM_408022_FIXED
113 // 1) using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache
114 // operation might fail to invalidate some lines if coincident with linefill"
115 // is fixed on this hardware, or
116 // 2) using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache
117 // operation might fail to invalidate some lines if coincident with linefill
118 // is fixed on this hardware.
120 // 1) Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg.
121 // 2) Replaces Invalidate ICache operation with the sequence defined in the errata document.
122 // If this macro is enabled, it should be accompanied by:
123 // "GBLL CFG_CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh
125 // #define __CPU_ARM1136_ERRATUM_411920_FIXED
127 macro FAULTY_NONSHARED_DEVICE_MEMORY
129 #define AsspNKernIncludePath /epoc32/include/assp/naviengine/nkern
131 // FIQ can not be disabled on naviengine, tell kernel to ignore it...
132 macro __FIQ_IS_UNCONTROLLED__
134 macro MONITOR_THREAD_CPU_TIME
136 #if defined(__USING_USING_ASSP_REGISTER_API__) || defined(__USING_INTERRUPT_API__) || defined(__USING_ASSP_REGISTER_API__)
137 library VariantTarget(kanaviengine,lib)