1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/kerneltest/e32test/smr/ne1/variant.mmh Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,139 @@
1.4 +/*
1.5 +* Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies).
1.6 +* All rights reserved.
1.7 +* This component and the accompanying materials are made available
1.8 +* under the terms of the License "Eclipse Public License v1.0"
1.9 +* which accompanies this distribution, and is available
1.10 +* at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.11 +*
1.12 +* Initial Contributors:
1.13 +* Nokia Corporation - initial contribution.
1.14 +*
1.15 +* Contributors:
1.16 +*
1.17 +* Description:
1.18 +*
1.19 +*/
1.20 +//
1.21 +// TO DO: (mandatory)
1.22 +//
1.23 +// Add here a definition for your CPU (list in CONFIG.INC)
1.24 +//
1.25 +macro __CPU_ARM11MP__
1.26 +//
1.27 +// TO DO: (mandatory)
1.28 +//
1.29 +// Add here a definition for your Memory Model
1.30 +//
1.31 +#define MM_MULTIPLE
1.32 +//
1.33 +// TO DO: (mandatory)
1.34 +//
1.35 +// Macro which generates the names for the binaries for this platform
1.36 +//
1.37 +#ifndef VariantTarget
1.38 +#define VariantTarget(name,ext) _ne1_tb_##name##.##ext
1.39 +#endif
1.40 +
1.41 +#ifndef VariantMediaDefIncludePath
1.42 +#define VariantMediaDefIncludePath /epoc32/include/ne1_tb
1.43 +#endif
1.44 +
1.45 +// Used in MMP files for include paths e.g. to hcrconfig.h header
1.46 +#ifndef VariantIncludePath
1.47 +#define VariantIncludePath /epoc32/include/ne1_tb
1.48 +#endif
1.49 +
1.50 +
1.51 +//Include debug support
1.52 +macro __DEBUGGER_SUPPORT__
1.53 +
1.54 +//
1.55 +// TO DO:
1.56 +//
1.57 +// If euser is built from the variant, uncomment the following line to build it
1.58 +// as ARM rather than Thumb
1.59 +//
1.60 +//#define __BUILD_VARIANT_EUSER_AS_ARM__
1.61 +//
1.62 +// TO DO: (optional)
1.63 +//
1.64 +// To replace some of the generic utility functions with variant specific
1.65 +// versions (eg to replace memcpy with a version optimised for the hardware),
1.66 +// uncomment the two lines below and edit the files in the replacementUtils
1.67 +// directory.
1.68 +//
1.69 +//#define REPLACE_GENERIC_UTILS
1.70 +//#define VariantReplacementUtilsPath ne1_tb/replacement_utils
1.71 +//
1.72 +// TO DO: (optional)
1.73 +//
1.74 +// Enable BTrace support in release versions of the kernel by adding
1.75 +// the following BTRACE macro declarations
1.76 +//
1.77 +macro BTRACE_KERNEL_ALL
1.78 +//
1.79 +// TO DO:
1.80 +//
1.81 +// Uncomment the following line if using the r1p0 release or later of the ARM1136 processor.
1.82 +//
1.83 +//#define __CPU_ARM1136_IS_R1__
1.84 +//
1.85 +
1.86 +// Include the following line if default memory mapping should use shared memory.
1.87 +// Should be on for multicore (SMP) devices.
1.88 +
1.89 +macro __CPU_USE_SHARED_MEMORY
1.90 +
1.91 +// Include the following line if CPU cannot tolerate the presence of nonshared
1.92 +// cached memory. This seems to be the case for the ARM11 MPCore - corruption
1.93 +// of data is observed in non-shared cached regions if __CPU_USE_SHARED_MEMORY
1.94 +// is used.
1.95 +
1.96 +macro __CPU_FORCE_SHARED_MEMORY_IF_CACHED
1.97 +
1.98 +
1.99 +
1.100 +// TO DO:
1.101 +//
1.102 +// Uncomment the next line if using the ARM1136 processor and ARM1136 Erratum 406973
1.103 +// "CLREX instruction might be ignored during data cache line fill"
1.104 +// is fixed on this hardware.
1.105 +//
1.106 +//#define __CPU_ARM1136_ERRATUM_406973_FIXED
1.107 +
1.108 +// Uncomment next line if using the ARM1136 processor and ARM1136 Erratum 408022
1.109 +// "Cancelled write to CONTEXTID register might update ASID"
1.110 +// is fixed on this hardware.
1.111 +//
1.112 +//#define __CPU_ARM1136_ERRATUM_408022_FIXED
1.113 +
1.114 +
1.115 +// Uncomment if:
1.116 +// 1) using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache
1.117 +// operation might fail to invalidate some lines if coincident with linefill"
1.118 +// is fixed on this hardware, or
1.119 +// 2) using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache
1.120 +// operation might fail to invalidate some lines if coincident with linefill
1.121 +// is fixed on this hardware.
1.122 +// Workaround:
1.123 +// 1) Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg.
1.124 +// 2) Replaces Invalidate ICache operation with the sequence defined in the errata document.
1.125 +// If this macro is enabled, it should be accompanied by:
1.126 +// "GBLL CFG_CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh
1.127 +//
1.128 +// #define __CPU_ARM1136_ERRATUM_411920_FIXED
1.129 +
1.130 +macro FAULTY_NONSHARED_DEVICE_MEMORY
1.131 +
1.132 +#define AsspNKernIncludePath /epoc32/include/assp/naviengine/nkern
1.133 +
1.134 +// FIQ can not be disabled on naviengine, tell kernel to ignore it...
1.135 +macro __FIQ_IS_UNCONTROLLED__
1.136 +
1.137 +macro MONITOR_THREAD_CPU_TIME
1.138 +
1.139 +#if defined(__USING_USING_ASSP_REGISTER_API__) || defined(__USING_INTERRUPT_API__) || defined(__USING_ASSP_REGISTER_API__)
1.140 +library VariantTarget(kanaviengine,lib)
1.141 +#endif
1.142 +