os/kernelhwsrv/kerneltest/e32test/smr/ne1/variant.mmh
author sl
Tue, 10 Jun 2014 14:32:02 +0200
changeset 1 260cb5ec6c19
permissions -rw-r--r--
Update contrib.
     1 /*
     2 * Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies).
     3 * All rights reserved.
     4 * This component and the accompanying materials are made available
     5 * under the terms of the License "Eclipse Public License v1.0"
     6 * which accompanies this distribution, and is available
     7 * at the URL "http://www.eclipse.org/legal/epl-v10.html".
     8 *
     9 * Initial Contributors:
    10 * Nokia Corporation - initial contribution.
    11 *
    12 * Contributors:
    13 *
    14 * Description:
    15 *
    16 */
    17 //
    18 // TO DO: (mandatory)
    19 //
    20 // Add here a definition for your CPU (list in CONFIG.INC)
    21 //
    22 macro __CPU_ARM11MP__
    23 //
    24 // TO DO: (mandatory)
    25 //
    26 // Add here a definition for your Memory Model
    27 //
    28 #define MM_MULTIPLE
    29 //
    30 // TO DO: (mandatory)
    31 //
    32 // Macro which generates the names for the binaries for this platform
    33 //
    34 #ifndef VariantTarget
    35 #define VariantTarget(name,ext) _ne1_tb_##name##.##ext
    36 #endif
    37 
    38 #ifndef VariantMediaDefIncludePath
    39 #define VariantMediaDefIncludePath /epoc32/include/ne1_tb
    40 #endif
    41 
    42 // Used in MMP files for include paths e.g. to hcrconfig.h header
    43 #ifndef VariantIncludePath
    44 #define VariantIncludePath /epoc32/include/ne1_tb
    45 #endif
    46 
    47 
    48 //Include debug support
    49 macro __DEBUGGER_SUPPORT__
    50 
    51 //
    52 // TO DO: 
    53 //
    54 // If euser is built from the variant, uncomment the following line to build it
    55 // as ARM rather than Thumb
    56 // 
    57 //#define __BUILD_VARIANT_EUSER_AS_ARM__
    58 //
    59 // TO DO: (optional)
    60 //
    61 // To replace some of the generic utility functions with variant specific
    62 // versions (eg to replace memcpy with a version optimised for the hardware),
    63 // uncomment the two lines below and edit the files in the replacementUtils
    64 // directory.
    65 //
    66 //#define REPLACE_GENERIC_UTILS
    67 //#define VariantReplacementUtilsPath ne1_tb/replacement_utils
    68 //
    69 // TO DO: (optional)
    70 //
    71 // Enable BTrace support in release versions of the kernel by adding
    72 // the following BTRACE macro declarations
    73 //
    74 macro BTRACE_KERNEL_ALL
    75 //
    76 // TO DO:
    77 //
    78 // Uncomment the following line if using the r1p0 release or later of the ARM1136 processor.
    79 // 
    80 //#define __CPU_ARM1136_IS_R1__
    81 //
    82 
    83 // Include the following line if default memory mapping should use shared memory.
    84 // Should be on for multicore (SMP) devices.
    85 
    86 macro	__CPU_USE_SHARED_MEMORY
    87 
    88 // Include the following line if CPU cannot tolerate the presence of nonshared
    89 // cached memory. This seems to be the case for the ARM11 MPCore - corruption
    90 // of data is observed in non-shared cached regions if __CPU_USE_SHARED_MEMORY
    91 // is used.
    92 
    93 macro	__CPU_FORCE_SHARED_MEMORY_IF_CACHED
    94 
    95 
    96 
    97 // TO DO:
    98 //
    99 // Uncomment the next line if using the ARM1136 processor and ARM1136 Erratum 406973
   100 // "CLREX instruction might be ignored during data cache line fill"
   101 // is fixed on this hardware.
   102 // 
   103 //#define __CPU_ARM1136_ERRATUM_406973_FIXED
   104 
   105 // Uncomment next line if using the ARM1136 processor and ARM1136 Erratum 408022 
   106 // "Cancelled write to CONTEXTID register might update ASID" 
   107 // is fixed on this hardware.
   108 //
   109 //#define __CPU_ARM1136_ERRATUM_408022_FIXED
   110 
   111 
   112 // Uncomment if:
   113 //	1)	using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache
   114 //	  	operation might fail to invalidate some lines if coincident with linefill"
   115 //  	  	is fixed on this hardware, or
   116 //	2)	using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache
   117 // 	  	operation might fail to invalidate some lines if coincident with linefill
   118 //	  	is fixed on this hardware.
   119 // Workaround:
   120 //	1)	Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg.
   121 //	2)	Replaces Invalidate ICache operation with the sequence defined in the errata document.
   122 // If this macro is enabled, it should be accompanied by:
   123 // 	"GBLL CFG_CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh
   124 //
   125 // #define __CPU_ARM1136_ERRATUM_411920_FIXED
   126 
   127 macro FAULTY_NONSHARED_DEVICE_MEMORY
   128 
   129 #define AsspNKernIncludePath		/epoc32/include/assp/naviengine/nkern
   130 
   131 // FIQ can not be disabled on naviengine, tell kernel to ignore it...
   132 macro __FIQ_IS_UNCONTROLLED__
   133 
   134 macro MONITOR_THREAD_CPU_TIME
   135 
   136 #if defined(__USING_USING_ASSP_REGISTER_API__) || defined(__USING_INTERRUPT_API__) || defined(__USING_ASSP_REGISTER_API__)
   137 library	VariantTarget(kanaviengine,lib)
   138 #endif
   139