os/kernelhwsrv/kernel/eka/memmodel/epoc/flexible/mmu/arm/xmmu.cia
author sl@SLION-WIN7.fritz.box
Fri, 15 Jun 2012 03:10:57 +0200
changeset 0 bde4ae8d615e
permissions -rw-r--r--
First public contribution.
     1 // Copyright (c) 1997-2009 Nokia Corporation and/or its subsidiary(-ies).
     2 // All rights reserved.
     3 // This component and the accompanying materials are made available
     4 // under the terms of the License "Eclipse Public License v1.0"
     5 // which accompanies this distribution, and is available
     6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".
     7 //
     8 // Initial Contributors:
     9 // Nokia Corporation - initial contribution.
    10 //
    11 // Contributors:
    12 //
    13 // Description:
    14 //
    15 
    16 #include <arm_mem.h>
    17 #include "execs.h"
    18 
    19 
    20 __NAKED__ TUint32 TTCR()
    21 	{
    22 	asm("mrc p15, 0, r0, c2, c0, 2 ");
    23 	asm("and r0, r0, #7 ");	// only bottom 3 bits are defined
    24 	__JUMP(,lr);
    25 	}
    26 
    27 
    28 __NAKED__ TUint32 CPUID(TInt /*aRegNum*/)
    29 	{
    30 	asm("movs r1, r0");
    31 	asm("mrcmi p15, 0, r0, c0, c0, 0 "); // for -ve reg, return old CPUID register
    32 	asm("mrceq p15, 0, r0, c0, c1, 0 ");
    33 	asm("subs r1, r1, #1");
    34 	asm("mrceq p15, 0, r0, c0, c1, 1 ");
    35 	asm("subs r1, r1, #1");
    36 	asm("mrceq p15, 0, r0, c0, c1, 2 ");
    37 	asm("subs r1, r1, #1");
    38 	asm("mrceq p15, 0, r0, c0, c1, 3 ");
    39 	asm("subs r1, r1, #1");
    40 	asm("mrceq p15, 0, r0, c0, c1, 4 ");
    41 	asm("subs r1, r1, #1");
    42 	asm("mrceq p15, 0, r0, c0, c1, 5 ");
    43 	asm("subs r1, r1, #1");
    44 	asm("mrceq p15, 0, r0, c0, c1, 6 ");
    45 	asm("subs r1, r1, #1");
    46 	asm("mrceq p15, 0, r0, c0, c1, 7 ");
    47 	asm("subs r1, r1, #1");
    48 	asm("mrceq p15, 0, r0, c0, c2, 0 ");
    49 	asm("subs r1, r1, #1");
    50 	asm("mrceq p15, 0, r0, c0, c2, 1 ");
    51 	asm("subs r1, r1, #1");
    52 	asm("mrceq p15, 0, r0, c0, c2, 2 ");
    53 	asm("subs r1, r1, #1");
    54 	asm("mrceq p15, 0, r0, c0, c2, 3 ");
    55 	asm("subs r1, r1, #1");
    56 	asm("mrceq p15, 0, r0, c0, c2, 4 ");
    57 	asm("subs r1, r1, #1");
    58 	asm("mrceq p15, 0, r0, c0, c2, 5 ");
    59 	asm("subs r1, r1, #1");
    60 	asm("mrceq p15, 0, r0, c0, c2, 6 ");
    61 	asm("subs r1, r1, #1");
    62 	asm("mrceq p15, 0, r0, c0, c2, 7 ");
    63 	__JUMP(,lr);
    64 	}
    65 
    66 
    67 __NAKED__ void UnlockIPCAlias()
    68 	{
    69 	asm("mrc p15, 0, r0, c3, c0, 0 ");
    70 	asm("orr r0, r0, #%a0 " : : "i" (1 << (2*KIPCAliasDomain)));	// Allow client access to Alias mappings
    71 	asm("mcr p15, 0, r0, c3, c0, 0 ");
    72 	__INST_SYNC_BARRIER_Z__(r0);
    73 	__JUMP(,lr);
    74 	}
    75 
    76 __NAKED__ void LockIPCAlias()
    77 	{
    78 	asm("mrc p15, 0, r0, c3, c0, 0 ");
    79 	asm("bic r0, r0, #%a0 " : : "i" (3 << (2*KIPCAliasDomain)));	// Prevent access to Alias mappings
    80 	asm("mcr p15, 0, r0, c3, c0, 0 ");
    81 	__INST_SYNC_BARRIER_Z__(r0);
    82 	__JUMP(,lr);
    83 	}
    84 
    85 
    86 __NAKED__ void M::LockUserMemory()
    87 	{
    88 	USER_MEMORY_GUARD_ON(,r0,r0);		// Prevent access to User mappings in domain 15
    89 	__JUMP(,lr);
    90 	}
    91 
    92 
    93 __NAKED__ void M::UnlockUserMemory()
    94 	{
    95 	USER_MEMORY_GUARD_OFF(,r0,r0);		// Allow access to User mappings in domain 15
    96 	__JUMP(,lr);
    97 	}
    98 
    99 
   100 __NAKED__ void UserWriteFault(TLinAddr /*aAddr*/)
   101 	{
   102 	asm("strbt r1,[r0]");
   103 	__JUMP(,lr);
   104 	}
   105 
   106 __NAKED__ void UserReadFault(TLinAddr  /*aAddr*/)
   107 	{	
   108 	asm("ldrbt r1,[r0]");
   109 	__JUMP(,lr);
   110 	}
   111 
   112 
   113 extern "C" __NAKED__ void __e32_instruction_barrier()
   114 	{
   115 	__INST_SYNC_BARRIER_Z__(r0);
   116 	__JUMP(,lr);
   117 	}
   118