1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/os/kernelhwsrv/kernel/eka/memmodel/epoc/flexible/mmu/arm/xmmu.cia	Fri Jun 15 03:10:57 2012 +0200
     1.3 @@ -0,0 +1,118 @@
     1.4 +// Copyright (c) 1997-2009 Nokia Corporation and/or its subsidiary(-ies).
     1.5 +// All rights reserved.
     1.6 +// This component and the accompanying materials are made available
     1.7 +// under the terms of the License "Eclipse Public License v1.0"
     1.8 +// which accompanies this distribution, and is available
     1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
    1.10 +//
    1.11 +// Initial Contributors:
    1.12 +// Nokia Corporation - initial contribution.
    1.13 +//
    1.14 +// Contributors:
    1.15 +//
    1.16 +// Description:
    1.17 +//
    1.18 +
    1.19 +#include <arm_mem.h>
    1.20 +#include "execs.h"
    1.21 +
    1.22 +
    1.23 +__NAKED__ TUint32 TTCR()
    1.24 +	{
    1.25 +	asm("mrc p15, 0, r0, c2, c0, 2 ");
    1.26 +	asm("and r0, r0, #7 ");	// only bottom 3 bits are defined
    1.27 +	__JUMP(,lr);
    1.28 +	}
    1.29 +
    1.30 +
    1.31 +__NAKED__ TUint32 CPUID(TInt /*aRegNum*/)
    1.32 +	{
    1.33 +	asm("movs r1, r0");
    1.34 +	asm("mrcmi p15, 0, r0, c0, c0, 0 "); // for -ve reg, return old CPUID register
    1.35 +	asm("mrceq p15, 0, r0, c0, c1, 0 ");
    1.36 +	asm("subs r1, r1, #1");
    1.37 +	asm("mrceq p15, 0, r0, c0, c1, 1 ");
    1.38 +	asm("subs r1, r1, #1");
    1.39 +	asm("mrceq p15, 0, r0, c0, c1, 2 ");
    1.40 +	asm("subs r1, r1, #1");
    1.41 +	asm("mrceq p15, 0, r0, c0, c1, 3 ");
    1.42 +	asm("subs r1, r1, #1");
    1.43 +	asm("mrceq p15, 0, r0, c0, c1, 4 ");
    1.44 +	asm("subs r1, r1, #1");
    1.45 +	asm("mrceq p15, 0, r0, c0, c1, 5 ");
    1.46 +	asm("subs r1, r1, #1");
    1.47 +	asm("mrceq p15, 0, r0, c0, c1, 6 ");
    1.48 +	asm("subs r1, r1, #1");
    1.49 +	asm("mrceq p15, 0, r0, c0, c1, 7 ");
    1.50 +	asm("subs r1, r1, #1");
    1.51 +	asm("mrceq p15, 0, r0, c0, c2, 0 ");
    1.52 +	asm("subs r1, r1, #1");
    1.53 +	asm("mrceq p15, 0, r0, c0, c2, 1 ");
    1.54 +	asm("subs r1, r1, #1");
    1.55 +	asm("mrceq p15, 0, r0, c0, c2, 2 ");
    1.56 +	asm("subs r1, r1, #1");
    1.57 +	asm("mrceq p15, 0, r0, c0, c2, 3 ");
    1.58 +	asm("subs r1, r1, #1");
    1.59 +	asm("mrceq p15, 0, r0, c0, c2, 4 ");
    1.60 +	asm("subs r1, r1, #1");
    1.61 +	asm("mrceq p15, 0, r0, c0, c2, 5 ");
    1.62 +	asm("subs r1, r1, #1");
    1.63 +	asm("mrceq p15, 0, r0, c0, c2, 6 ");
    1.64 +	asm("subs r1, r1, #1");
    1.65 +	asm("mrceq p15, 0, r0, c0, c2, 7 ");
    1.66 +	__JUMP(,lr);
    1.67 +	}
    1.68 +
    1.69 +
    1.70 +__NAKED__ void UnlockIPCAlias()
    1.71 +	{
    1.72 +	asm("mrc p15, 0, r0, c3, c0, 0 ");
    1.73 +	asm("orr r0, r0, #%a0 " : : "i" (1 << (2*KIPCAliasDomain)));	// Allow client access to Alias mappings
    1.74 +	asm("mcr p15, 0, r0, c3, c0, 0 ");
    1.75 +	__INST_SYNC_BARRIER_Z__(r0);
    1.76 +	__JUMP(,lr);
    1.77 +	}
    1.78 +
    1.79 +__NAKED__ void LockIPCAlias()
    1.80 +	{
    1.81 +	asm("mrc p15, 0, r0, c3, c0, 0 ");
    1.82 +	asm("bic r0, r0, #%a0 " : : "i" (3 << (2*KIPCAliasDomain)));	// Prevent access to Alias mappings
    1.83 +	asm("mcr p15, 0, r0, c3, c0, 0 ");
    1.84 +	__INST_SYNC_BARRIER_Z__(r0);
    1.85 +	__JUMP(,lr);
    1.86 +	}
    1.87 +
    1.88 +
    1.89 +__NAKED__ void M::LockUserMemory()
    1.90 +	{
    1.91 +	USER_MEMORY_GUARD_ON(,r0,r0);		// Prevent access to User mappings in domain 15
    1.92 +	__JUMP(,lr);
    1.93 +	}
    1.94 +
    1.95 +
    1.96 +__NAKED__ void M::UnlockUserMemory()
    1.97 +	{
    1.98 +	USER_MEMORY_GUARD_OFF(,r0,r0);		// Allow access to User mappings in domain 15
    1.99 +	__JUMP(,lr);
   1.100 +	}
   1.101 +
   1.102 +
   1.103 +__NAKED__ void UserWriteFault(TLinAddr /*aAddr*/)
   1.104 +	{
   1.105 +	asm("strbt r1,[r0]");
   1.106 +	__JUMP(,lr);
   1.107 +	}
   1.108 +
   1.109 +__NAKED__ void UserReadFault(TLinAddr  /*aAddr*/)
   1.110 +	{	
   1.111 +	asm("ldrbt r1,[r0]");
   1.112 +	__JUMP(,lr);
   1.113 +	}
   1.114 +
   1.115 +
   1.116 +extern "C" __NAKED__ void __e32_instruction_barrier()
   1.117 +	{
   1.118 +	__INST_SYNC_BARRIER_Z__(r0);
   1.119 +	__JUMP(,lr);
   1.120 +	}
   1.121 +