sl@0: // Copyright (c) 1995-2009 Nokia Corporation and/or its subsidiary(-ies).
sl@0: // All rights reserved.
sl@0: // This component and the accompanying materials are made available
sl@0: // under the terms of the License "Eclipse Public License v1.0"
sl@0: // which accompanies this distribution, and is available
sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
sl@0: //
sl@0: // Initial Contributors:
sl@0: // Nokia Corporation - initial contribution.
sl@0: //
sl@0: // Contributors:
sl@0: //
sl@0: // Description:
sl@0: // e32test\iic\t_iic.h
sl@0: //
sl@0: 
sl@0: #ifndef __T_IIC_H__
sl@0: #define __T_IIC_H__
sl@0: 
sl@0: #include <e32ver.h>
sl@0: 
sl@0: const TInt KIicClientMajorVersionNumber = 1;
sl@0: const TInt KIicClientMinorVersionNumber = 0;
sl@0: const TInt KIicClientBuildVersionNumber = KE32BuildVersionNumber;
sl@0: 
sl@0: const TInt KPriorityTestNum = 6; // 1 blocking transaction + 5 test transactions
sl@0: 
sl@0: // For IIC,
sl@0: // If bit 31 is set and bit 30 cleared it is used to extend the Master-Slave channel;
sl@0: // if bit 31 is cleared and bit 30 is set, it extends the Master channel; 
sl@0: // if both bits 31 and 30 are cleared it extends the Slave channel interface.
sl@0: // However,
sl@0: // since the kernel-side proxy clients interpret the msb being set as indicative of an
sl@0: // asynchronous request, the values here will have the static extension pattern represented
sl@0: // in bits 30 and 29, instead. In addition, to support communication with the slave-side proxy,
sl@0: // the Slave extension value will be represented as bits 30 and 29 set, so that it can be distinguished
sl@0: // from 'normal' synchronous operations.
sl@0: //
sl@0: const TUint KTestControlIoMask =			0x60000000;
sl@0: const TUint KTestMasterControlIo =		0x20000000;
sl@0: const TUint KTestSlaveControlIo =		0x60000000;
sl@0: const TUint KTestMasterSlaveControlIo =	0x40000000;
sl@0: const TUint KTestControlIoPilOffset =	0x00000002;	// Corresponds to 1 higher than the number used by PIL
sl@0: const TUint KTestControlUnitTestOffset = 0x10000000;
sl@0: 
sl@0: //
sl@0: // Enumerations TReqType and TBusType defined in kernel-side class TIicBusTransfer
sl@0: // The user-side test, and the kernel-side proxy client require access to this
sl@0: enum TReqType
sl@0: 	{
sl@0: 	EMasterRead,
sl@0: 	EMasterWrite
sl@0: 	};
sl@0: enum TBusType
sl@0: 	{
sl@0: 	EI2c	   = 0,
sl@0: 	ESpi	   = 0x01,
sl@0: 	EMicrowire = 0x02,
sl@0: 	ECci	   = 0x03,
sl@0: 	ESccb	   = 0x04,
sl@0: 	EInvalidBus
sl@0: 	};
sl@0: 
sl@0: #define MAX_TRANS_LENGTH 20	
sl@0: 
sl@0: 
sl@0: #ifndef __KERNEL_MODE__
sl@0: //
sl@0: //	For convenience, selected kernel-side information is replicated here
sl@0: //  to allow the user-side test to populate buffers accordingly
sl@0: //
sl@0: // Bus-specific configuration
sl@0: //
sl@0: enum TEndianness
sl@0: 	{
sl@0: 	EBigEndian,
sl@0: 	ELittleEndian
sl@0: 	};
sl@0: 
sl@0: enum TBitOrder
sl@0: 	{
sl@0: 	ELsbFirst,
sl@0: 	EMsbFirst
sl@0: 	};
sl@0: 
sl@0: //
sl@0: // Bus-specific configuration for SPI bus
sl@0: //
sl@0: 
sl@0: enum TSpiWordWidth
sl@0: 	{
sl@0: 	ESpiWordWidth_8,
sl@0: 	ESpiWordWidth_10,
sl@0: 	ESpiWordWidth_12,
sl@0: 	ESpiWordWidth_16
sl@0: 	};
sl@0: 
sl@0: enum TSpiClkMode
sl@0: 	{
sl@0: 	ESpiPolarityLowRisingEdge,		// Active high, odd edges
sl@0: 	ESpiPolarityLowFallingEdge,		// Active high, even edges
sl@0: 	ESpiPolarityHighFallingEdge,	// Active low,  odd edges
sl@0: 	ESpiPolarityHighRisingEdge		// Active low,  even edges
sl@0: 	};
sl@0: 
sl@0: enum TSpiSsPinMode
sl@0:     {
sl@0:     ESpiCSPinActiveLow,      // Active low
sl@0:     ESpiCSPinActiveHigh     // Active high
sl@0:     };
sl@0: 
sl@0: class TConfigSpiV01
sl@0: 	{
sl@0: public:
sl@0: 	TSpiWordWidth	iWordWidth;
sl@0: 	TInt32			iClkSpeedHz;
sl@0: 	TSpiClkMode		iClkMode;
sl@0: 	TInt32			iTimeoutPeriod;
sl@0: 	TEndianness		iEndianness;
sl@0: 	TBitOrder		iBitOrder;
sl@0: 	TUint			iTransactionWaitCycles;
sl@0: 	TSpiSsPinMode	iSSPinActiveMode;
sl@0: 	};
sl@0: 
sl@0: typedef TPckgBuf <TConfigSpiV01> TConfigSpiBufV01;
sl@0: 
sl@0: 
sl@0: //
sl@0: // Bus-specific configuration for I2C bus
sl@0: //
sl@0: 
sl@0: enum TI2cAddrType
sl@0: 	{
sl@0: 	EI2cAddr7Bit,
sl@0: 	EI2cAddr10Bit
sl@0: 	};
sl@0: 
sl@0: class TConfigI2cV01
sl@0: 	{
sl@0: 	public:
sl@0: 	TI2cAddrType	iAddrType;		// 7 or 10-bit addressing
sl@0: 	TInt32			iClkSpeedHz;
sl@0: 	TEndianness		iEndianness;
sl@0: 	TInt32			iTimeoutPeriod;
sl@0: 	};
sl@0: 
sl@0: typedef TPckgBuf <TConfigI2cV01> TConfigI2cBufV01;
sl@0: 
sl@0: 
sl@0: inline static TInt CreateSpiBuf(TConfigSpiBufV01*& aBuf,
sl@0: 								TSpiWordWidth	aWordWidth,
sl@0: 								TInt32			aClkSpeedHz,
sl@0: 								TSpiClkMode		aClkMode,
sl@0: 								TInt32			aTimeoutPeriod,
sl@0: 								TEndianness		aEndianness,
sl@0: 								TBitOrder		aBitOrder,
sl@0: 								TUint			aTransactionWaitCycles,
sl@0: 								TSpiSsPinMode	aSSPinActiveMode)
sl@0: // Utility function to create a buffer for the SPI bus
sl@0: 	{
sl@0: 	aBuf = new TConfigSpiBufV01();
sl@0: 	if(aBuf==NULL)
sl@0: 		return KErrNoMemory;
sl@0: 	TConfigSpiV01 *buf = &((*aBuf)());
sl@0: 	buf->iWordWidth = aWordWidth;
sl@0: 	buf->iClkSpeedHz = aClkSpeedHz;
sl@0: 	buf->iClkMode = aClkMode;
sl@0: 	buf->iTimeoutPeriod = aTimeoutPeriod;
sl@0: 	buf->iEndianness = aEndianness;
sl@0: 	buf->iBitOrder = aBitOrder;
sl@0: 	buf->iTransactionWaitCycles = aTransactionWaitCycles;
sl@0: 	buf->iSSPinActiveMode = aSSPinActiveMode;
sl@0: 	return KErrNone;
sl@0: 	}
sl@0: 
sl@0: inline static TInt CreateI2cBuf(TConfigI2cBufV01*& aBuf,
sl@0: 								TI2cAddrType	aAddrType,
sl@0: 								TInt32			aClkSpeedHz,
sl@0: 								TEndianness		aEndianness,
sl@0: 								TInt32			aTimeoutPeriod)
sl@0: // Utility function to create a buffer for the I2C bus
sl@0: 	{
sl@0: 	aBuf = new TConfigI2cBufV01();
sl@0: 	if(aBuf==NULL)
sl@0: 		return KErrNoMemory;
sl@0: 	TConfigI2cV01 *buf = &((*aBuf)());
sl@0: 	buf->iAddrType = aAddrType;
sl@0: 	buf->iClkSpeedHz = aClkSpeedHz;
sl@0: 	buf->iEndianness = aEndianness;
sl@0: 	buf->iTimeoutPeriod = aTimeoutPeriod;
sl@0: 	return KErrNone;
sl@0: 	}
sl@0: 
sl@0: //
sl@0: // Enumerations for channel type and channel duplex defined in kernel-side class DIicBusChannel
sl@0: // duplicated for temporary test
sl@0: enum TChannelType
sl@0: 	{
sl@0: 	EMaster			= 0,
sl@0: 	ESlave			= 0x01,
sl@0: 	EMasterSlave	= 0x02,
sl@0: 	EInvalidType
sl@0: 	};
sl@0: enum TChannelDuplex
sl@0: 	{
sl@0: 	EHalfDuplex = 0,	// supports only half duplex transactions (even if bus spec supports full duplex)
sl@0: 	EFullDuplex = 0x1,	// supports full duplex transactions (queud transactions may still be half duplex)
sl@0: 	EInvalidDuplex
sl@0: 	};
sl@0: //
sl@0: // Bus realisation configuration
sl@0: //
sl@0: // 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10  9  8 |  7  6  5  4 |  3  2  1  0
sl@0: //
sl@0: // 31:29 - HS Master address (I2C only)
sl@0: // 28    - HS address valid bit
sl@0: // 27:23 - Reserved
sl@0: // 22:20 - Bus type
sl@0: // 19:15 - Channel number
sl@0: // 14:10 - Transaction speed
sl@0: //  9:0  - Slave address
sl@0: #define HS_MASTER_ADDR_SHIFT 29
sl@0: #define HS_MASTER_ADDR_MASK 0x7
sl@0: #define HS_ADDR_VALID_SHIFT 28
sl@0: #define HS_ADDR_VALID_MASK 0x1
sl@0: #define BUS_TYPE_SHIFT 20
sl@0: #define BUS_TYPE_MASK 0x7
sl@0: #define CHANNEL_NO_SHIFT 15
sl@0: #define CHANNEL_NO_MASK 0x1F
sl@0: #define TRANS_SPEED_SHIFT 10
sl@0: #define TRANS_SPEED_MASK 0x1F
sl@0: #define SLAVE_ADDR_SHIFT 0
sl@0: #define SLAVE_ADDR_MASK 0x3FF
sl@0: //
sl@0: // Macros to access fields within Bus Realisation Configuration data, used on a per-transaction basis with IIC
sl@0: #define SET_CONFIG_FIELD(aBusId,aField,aMask,aShift) aBusId=(aBusId&~(aMask<<aShift))|((aField&aMask)<<aShift);
sl@0: #define GET_CONFIG_FIELD(aBusId,aMask,aShift) (((aBusId)>>(aShift))&(aMask))
sl@0: 
sl@0: #define GET_HS_MASTER_ADDR(aBusId) GET_CONFIG_FIELD(aBusId,HS_MASTER_ADDR_MASK,HS_MASTER_ADDR_SHIFT)
sl@0: #define SET_HS_MASTER_ADDR(aBusId,aHsMasterAddr) SET_CONFIG_FIELD(aBusId,aHsMasterAddr,HS_MASTER_ADDR_MASK,HS_MASTER_ADDR_SHIFT)
sl@0: #define GET_HS_VALID(aBusId) GET_CONFIG_FIELD(aBusId,HS_ADDR_VALID_MASK,HS_ADDR_VALID_SHIFT)
sl@0: #define SET_HS_VALID(aBusId,aHsValid) SET_CONFIG_FIELD(aBusId,aHsValid,HS_ADDR_VALID_MASK,HS_ADDR_VALID_SHIFT)
sl@0: #define GET_BUS_TYPE(aBusId) GET_CONFIG_FIELD(aBusId,BUS_TYPE_MASK,BUS_TYPE_SHIFT)
sl@0: #define SET_BUS_TYPE(aBusId,aBusType) SET_CONFIG_FIELD(aBusId,aBusType,BUS_TYPE_MASK,BUS_TYPE_SHIFT)
sl@0: #define GET_CHAN_NUM(aBusId) GET_CONFIG_FIELD(aBusId,CHANNEL_NO_MASK,CHANNEL_NO_SHIFT)
sl@0: #define SET_CHAN_NUM(aBusId,aChanNum) SET_CONFIG_FIELD(aBusId,aChanNum,CHANNEL_NO_MASK,CHANNEL_NO_SHIFT)
sl@0: #define SET_TRANS_SPEED(aBusId,aTransSpeed) SET_CONFIG_FIELD(aBusId,aTransSpeed,TRANS_SPEED_MASK,TRANS_SPEED_SHIFT)
sl@0: #define GET_TRANS_SPEED(aBusId) GET_CONFIG_FIELD(aBusId,TRANS_SPEED_MASK,TRANS_SPEED_SHIFT)
sl@0: #define SET_SLAVE_ADDR(aBusId,aSlaveAddr) SET_CONFIG_FIELD(aBusId,aSlaveAddr,SLAVE_ADDR_MASK,SLAVE_ADDR_SHIFT)
sl@0: #define GET_SLAVE_ADDR(aBusId) GET_CONFIG_FIELD(aBusId,SLAVE_ADDR_MASK,SLAVE_ADDR_SHIFT)
sl@0: 
sl@0: static const TUint8 KTransactionWithPreamble = 0x80;
sl@0: static const TUint8 KTransactionWithMultiTransc = 0x40;
sl@0: 
sl@0: enum TIicBusSlaveTrigger
sl@0: 	{
sl@0: 	ERxAllBytes			= 0x01,
sl@0: 	ERxUnderrun			= 0x02,
sl@0: 	ERxOverrun			= 0x04,
sl@0: 	ETxAllBytes			= 0x08,
sl@0: 	ETxUnderrun			= 0x10,
sl@0: 	ETxOverrun			= 0x20,
sl@0: 	EGeneralBusError	= 0x40,
sl@0: 	EAsyncCaptChan		= 0x80
sl@0: 	};
sl@0: 
sl@0: #endif // #ifndef __KERNEL_MODE__
sl@0: 
sl@0: //
sl@0: // User-Side abbreviation of kernel side classes TIicBusTransfer and TIicBusTransaction
sl@0: //
sl@0: struct TUsideTferDesc
sl@0: 	{
sl@0: 	TInt8 iType;			// as one of TReqType
sl@0: 	TInt8 iBufGranularity;	// width of a transfer word in bits
sl@0: 	TDes8* iBuffer;	// the data for this transfer (packed into 8-bit words with padding)
sl@0: 	TUsideTferDesc* iNext;
sl@0: 	};
sl@0: 
sl@0: struct TUsideTracnDesc
sl@0: 	{
sl@0: 	TBusType iType;
sl@0: 	TDes8* iHeader;
sl@0: 	TUsideTferDesc* iHalfDuplexTrans;
sl@0: 	TUsideTferDesc* iFullDuplexTrans;
sl@0: 	TUint8 iFlags;				// used to indicate if it supports a preamble
sl@0: 	TAny* iPreambleArg;			// used for preamble argument
sl@0: 	TAny* iMultiTranscArg;		// used for multi transc argument
sl@0: 	};
sl@0: 
sl@0: class RBusDevIicClient : public RBusLogicalChannel
sl@0: 	{
sl@0:     public:
sl@0: 	enum TControl
sl@0: 		{
sl@0: // Master mode operations
sl@0: 		EQTransSync=1,						/**< Queue Transaction (Synchronous version)					*/
sl@0: // Slave mode operations
sl@0: 		EInitSlaveClient,					/**< Instigate Slave initialisation required to support testing	*/
sl@0: 		ECaptureChanSync,					/**< Capture Channel (Synchronous version)						*/
sl@0: 		EReleaseChan,						/**< ReleaseChannel												*/
sl@0: 		ERegisterRxBuffer,					/**< Register a buffer for receiving data						*/
sl@0: 		ERegisterTxBuffer,					/**< Register a buffer for transmitting data					*/
sl@0: 		ESetNotifTrigger					/**< Set the notification triggers                               */									
sl@0: 		};
sl@0: 
sl@0: 	enum TStaticExt
sl@0: 		{
sl@0: 		ECtlIoNone = 0,
sl@0: 		ECtlIoDumpChan = 1, // KCtrlIoDumpChan - defined only for UDEB
sl@0: // ControlIO codes for Master follow
sl@0: 		ECtlIoBlockReqCompletion=(KTestMasterControlIo+KTestControlIoPilOffset),
sl@0: 		ECtlIoUnblockReqCompletion,
sl@0: 		ECtlIoDeRegChan,
sl@0: 		ECtlIoTracnOne,
sl@0: 		ECtlIoPriorityTest,
sl@0: 		EGetTestResult,
sl@0: 		ECtlIoSetTimeOutFlag,
sl@0: 		ECtlIoTestFullDuplexTrans,
sl@0: // ControlIO codes for Slave follow
sl@0: 		ECtrlIoRxWords=(KTestSlaveControlIo+KTestControlIoPilOffset),
sl@0: 		ECtrlIoTxWords,
sl@0: 		ECtrlIoRxTxWords,
sl@0: 		ECtrlIoTxChkBuf,
sl@0: 		ECtlIoBusError,
sl@0: 		ECtrlIoBlockNotification,
sl@0: 		ECtrlIoUnblockNotification,
sl@0: 		ECtrlIoUpdTimeout,
sl@0: 		ECtrlIoNotifNoTrigger
sl@0: 		};
sl@0: 	
sl@0: 	enum TTestFullDuplexTrans
sl@0: 		{
sl@0: 		ETestValidFullDuplexTrans=1,
sl@0: 		ETestInvalidFullDuplexTrans1,
sl@0: 		ETestInvalidFullDuplexTrans2,
sl@0: 		ETestLastNodeFullDuplexTrans,
sl@0: 		ETestDiffNodeNoFullDuplexTrans,
sl@0: 		ETestNone
sl@0: 		};
sl@0: 
sl@0: 	enum TRequest
sl@0: 		{
sl@0: // Master mode operations
sl@0: 		EQTransAsync=1,						/**< Queue Transaction (Asynchronous version)					*/
sl@0: 		ECtrlIoTestBufReUse,
sl@0: // Slave mode operations
sl@0: 		ECaptureChanAsync,					/**< Capture Channel (Asynchronous version)						*/
sl@0: 		ECtrlIoOvUndRunRxTx
sl@0: 		};
sl@0: 		
sl@0: 	enum TTestMessages
sl@0: 	    {
sl@0: 	    ETestIicChannelInlineFunc=KTestControlUnitTestOffset    
sl@0: 	    };
sl@0: 	
sl@0: #ifndef __KERNEL_MODE__
sl@0: 	public:   
sl@0: 	inline TInt TestIiicChannelInlineFunc(){return DoControl (ETestIicChannelInlineFunc, NULL, NULL);}	
sl@0: 	// Master mode functions
sl@0: 	inline TInt Open(TDesC& aProxyName) {return (DoCreate(aProxyName,TVersion(KIicClientMajorVersionNumber,KIicClientMinorVersionNumber,KIicClientBuildVersionNumber),-1,NULL,NULL,EOwnerThread));}
sl@0: 
sl@0: 	inline TInt QueueTransaction(TInt aBusId, TUsideTracnDesc* aTransaction) {return(DoControl(EQTransSync,(TAny*)aBusId,(TAny*)aTransaction));}
sl@0: 
sl@0: 	inline void QueueTransaction(TRequestStatus& aStatus, TInt aBusId, TUsideTracnDesc* aTransaction) {DoRequest(EQTransAsync,aStatus,(TAny*)aBusId,(TAny*)aTransaction);}
sl@0: 
sl@0: 	inline void CancelAsyncOperation(TRequestStatus* aStatus, TInt aBusId)	{TInt* parms[2]; parms[0]=(TInt*)aStatus; parms[1]=(TInt*)aBusId;DoCancel((TInt)&parms[0]);} 
sl@0: 
sl@0: 	// Slave mode functions
sl@0: 	inline TInt InitSlaveClient() {return(DoControl(EInitSlaveClient,NULL,NULL));}
sl@0: 	inline TInt CaptureChannel(TInt aBusId, TDes8* aConfigHdr, TInt& aChannelId) {TInt* parms[2]; parms[0]=(TInt*)aBusId; parms[1]=&aChannelId;return(DoControl(ECaptureChanSync,(TAny*)aConfigHdr,(TAny*)(&parms[0])));}
sl@0: 
sl@0: 	inline TInt CaptureChannel(TInt aBusId, TDes8* aConfigHdr, TInt& aChannelId, TRequestStatus& aStatus) {TInt* parms[2]; parms[0]=(TInt*)aBusId; parms[1]=&aChannelId;DoRequest(ECaptureChanAsync,aStatus,(TAny*)aConfigHdr,(TAny*)(&parms[0]));return KErrNone;}
sl@0: 
sl@0: 	inline TInt ReleaseChannel(TInt aChannelId){return(DoControl(EReleaseChan,(TAny*)aChannelId,NULL));};
sl@0: 	inline TInt RegisterRxBuffer(TInt aChannelId, TInt8 aBufGranularity, TInt8 aNumWords, TInt8 aOffset){TInt8 parms[3]; parms[0]=aBufGranularity; parms[1]=aNumWords; parms[2]=aOffset;return(DoControl(ERegisterRxBuffer,(TAny*)aChannelId,(TAny*)(&parms[0])));};
sl@0: 	inline TInt RegisterTxBuffer(TInt aChannelId, TInt8 aBufGranularity, TInt8 aNumWords, TInt8 aOffset){TInt8 parms[3]; parms[0]=aBufGranularity; parms[1]=aNumWords; parms[2]=aOffset;return(DoControl(ERegisterTxBuffer,(TAny*)aChannelId,(TAny*)(&parms[0])));};
sl@0: 	inline TInt SetNotificationTrigger(TInt aChannelId, TInt aTrigger, TRequestStatus* aStatus){TInt parms[2]; parms[0]=aChannelId; parms[1]=aTrigger;return(DoControl(ESetNotifTrigger,(TAny*)aStatus,(TAny*)(&parms[0])));};
sl@0: 
sl@0: 	// ControlIO functions follow
sl@0: 	inline TInt BlockReqCompletion(TInt aBusId) {return(DoControl(ECtlIoBlockReqCompletion,(TAny*)aBusId));}
sl@0: 	inline TInt UnblockReqCompletion(TInt aBusId) {return(DoControl(ECtlIoUnblockReqCompletion,(TAny*)aBusId));}
sl@0: 	inline TInt DeRegisterChan(TInt aBusId) {return(DoControl(ECtlIoDeRegChan,(TAny*)aBusId));}
sl@0: 	inline TInt TestTracnOne(TInt aBusId) {return(DoControl(ECtlIoTracnOne, (TAny*)aBusId));}
sl@0: 	inline TInt SetTimeOutFlag(TInt aBusId){return(DoControl(ECtlIoSetTimeOutFlag,(TAny*)aBusId));}
sl@0: 	inline TInt CancelTimeOutFlag(TInt aBusId){return(DoControl(ECtlIoNone,(TAny*)aBusId));}
sl@0: 	inline TInt TestPriority(TInt aBusId) {return(DoControl(ECtlIoPriorityTest, (TAny*)aBusId));}
sl@0: 
sl@0: 	inline TInt TestValidFullDuplexTrans(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestValidFullDuplexTrans));}
sl@0: 	inline TInt TestInvalidFullDuplexTrans1(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestInvalidFullDuplexTrans1));}
sl@0: 	inline TInt TestInvalidFullDuplexTrans2(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestInvalidFullDuplexTrans2));}
sl@0: 	
sl@0: 	inline TInt TestLastNodeFullDuplexTrans(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestLastNodeFullDuplexTrans));}
sl@0: 	inline TInt TestDiffNodeNumFullDuplexTrans(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestDiffNodeNoFullDuplexTrans));}
sl@0: 
sl@0: 	inline void TestBufferReUse(TInt aBusId, TRequestStatus& aStatus) {DoRequest(ECtrlIoTestBufReUse,aStatus,(TAny*)aBusId,NULL);}
sl@0: 
sl@0: 	inline TInt SimulateRxNWords(TInt aBusId, TInt aChannelId, TInt aNumWords){TInt parms[2]; parms[0]=aChannelId; parms[1]=aNumWords;return(DoControl(ECtrlIoRxWords,(TAny*)aBusId,(TAny*)(&parms[0])));};
sl@0: 	inline TInt SimulateTxNWords(TInt aBusId, TInt aChannelId, TInt aNumWords){TInt parms[2]; parms[0]=aChannelId; parms[1]=aNumWords;return(DoControl(ECtrlIoTxWords,(TAny*)aBusId,(TAny*)(&parms[0])));};
sl@0: 	inline TInt SimulateRxTxNWords(TInt aBusId, TInt aChannelId, TInt aNumRxWords, TInt aNumTxWords){TInt parms[3]; parms[0]=aChannelId; parms[1]=aNumRxWords; parms[2]=aNumTxWords;return(DoControl(ECtrlIoRxTxWords,(TAny*)aBusId,(TAny*)(&parms[0])));};
sl@0: 	inline TInt SimulateBusErr(TInt aBusId, TInt aChannelId) {return(DoControl(ECtlIoBusError,(TAny*)aBusId,(TAny*)aChannelId));}
sl@0: 	inline TInt BlockNotification(TInt aBusId, TInt aChannelId) {return(DoControl(ECtrlIoBlockNotification,(TAny*)aBusId,(TAny*)aChannelId));}
sl@0: 	inline TInt UnblockNotification(TInt aBusId, TInt aChannelId) {return(DoControl(ECtrlIoUnblockNotification,(TAny*)aBusId,(TAny*)aChannelId));}
sl@0: 	inline TInt UpdateTimeoutValues(TInt aBusId, TInt aChannelId) {return(DoControl(ECtrlIoUpdTimeout,(TAny*)aBusId,(TAny*)aChannelId));}
sl@0: 	inline TInt SetNotifNoTrigger(TInt aChannelId, TInt aTrigger){return(DoControl(ECtrlIoNotifNoTrigger,(TAny*)aChannelId,(TAny*)aTrigger));};
sl@0: 
sl@0: 	inline void TestOverrunUnderrun(TInt aBusId, TInt aChannelId, TRequestStatus& aStatus) {DoRequest(ECtrlIoOvUndRunRxTx,aStatus,(TAny*)aBusId,(TAny*)aChannelId);}
sl@0: 
sl@0: #endif
sl@0: 	};
sl@0: 
sl@0: 
sl@0: #ifdef __KERNEL_MODE__
sl@0: 
sl@0: // Definition of function prototype for a callback function provided by the PSL
sl@0: // to be invoked when the part played by the hardware in processing a transfer
sl@0: // has completed.
sl@0: typedef void (*THwDoneCbFn)(TAny* );
sl@0: 
sl@0: #endif
sl@0: 
sl@0: // Data used to support tests
sl@0: 
sl@0: // Transaction One
sl@0: //
sl@0: const TUint8 KTransOneTferOne[21] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20};
sl@0: const TUint8 KTransOneTferTwo[8] = {17,18,19,20,21,22,23,24};
sl@0: const TUint8 KTransOneTferThree[6] = {87,85,83,81,79,77};
sl@0: const TUint8 KPriorityTestHeader[6] = {0,1,2,3,4,10}; 
sl@0: const TInt KPriorityTestPrio[6] = {1,2,3,4,5,0};
sl@0: 
sl@0: const TInt KRxBufSizeInBytes = 64;
sl@0: const TInt KTxBufSizeInBytes = 64;
sl@0: 
sl@0: #endif