| author | William Roberts <williamr@symbian.org> |
| Wed, 31 Mar 2010 12:33:34 +0100 | |
| branch | Symbian3 |
| changeset 4 | 837f303aceeb |
| permissions | -rw-r--r-- |
1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
2 // All rights reserved.
3 // This component and the accompanying materials are made available
4 // under the terms of the License "Eclipse Public License v1.0"
5 // which accompanies this distribution, and is available
6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".
7 //
8 // Initial Contributors:
9 // Nokia Corporation - initial contribution.
10 //
11 // Contributors:
12 //
13 // Description:
14 // omap3530/omap3530_drivers/gpio/omap3530_gpio.h
15 // This file is part of the Beagle Base port
16 //
18 #ifndef __OMAP3530_GPIO_H__
19 #define __OMAP3530_GPIO_H__
21 #include <assp/omap3530_assp/omap3530_hardware_base.h>
22 #include <assp/omap3530_assp/omap3530_irqmap.h>
23 //#include <drivers/gpio.h>
25 #include <assp/omap3530_assp/gpio.h>
26 #include <assp.h>
28 const TUint KGPIO1 = Omap3530HwBase::TVirtual<0x48310000>::Value;
29 const TUint KGPIO2 = Omap3530HwBase::TVirtual<0x49050000>::Value;
30 const TUint KGPIO3 = Omap3530HwBase::TVirtual<0x49052000>::Value;
31 const TUint KGPIO4 = Omap3530HwBase::TVirtual<0x49054000>::Value;
32 const TUint KGPIO5 = Omap3530HwBase::TVirtual<0x49056000>::Value;
33 const TUint KGPIO6 = Omap3530HwBase::TVirtual<0x49058000>::Value;
36 const TUint KGPIO_REVISION = 0x000;
37 const TUint KGPIO_SYSCONFIG = 0x010;
38 const TUint KGPIO_SYSSTATUS = 0x014;
39 const TUint KGPIO_IRQSTATUS1 = 0x018;
40 const TUint KGPIO_IRQENABLE1 = 0x01C;
41 const TUint KGPIO_WAKEUPENABLE = 0x020;
42 const TUint KGPIO_IRQSTATUS2 = 0x028;
43 const TUint KGPIO_IRQENABLE2 = 0x02C;
44 const TUint KGPIO_CTRL = 0x030;
45 const TUint KGPIO_OE = 0x034;
46 const TUint KGPIO_DATAIN = 0x038;
47 const TUint KGPIO_DATAOUT = 0x03C;
48 const TUint KGPIO_LEVELDETECT0 = 0x040;
49 const TUint KGPIO_LEVELDETECT1 = 0x044;
50 const TUint KGPIO_RISINGDETECT = 0x048;
51 const TUint KGPIO_FALLINGDETECT = 0x04C;
52 const TUint KGPIO_DEBOUNCENABLE = 0x050;
53 const TUint KGPIO_DEBOUNCINGTIME = 0x054;
54 const TUint KGPIO_CLEARIRQENABLE1 = 0x060;
55 const TUint KGPIO_SETIRQENABLE1 = 0x064;
56 const TUint KGPIO_CLEARIRQENABLE2 = 0x070;
57 const TUint KGPIO_SETIRQENABLE2 = 0x074;
58 const TUint KGPIO_CLEARWKUENA = 0x080;
59 const TUint KGPIO_SETWKUENA = 0x084;
60 const TUint KGPIO_CLEARDATAOUT = 0x090;
61 const TUint KGPIO_SETDATAOUT = 0x094;
63 const TUint KGPIO_DEBOUNCE_TIME_MASK = 0xF;
66 enum TGPIO_InterruptId
67 {
68 EGPIOIRQ_FIRST = (EIrqRangeBaseGpio << KIrqRangeIndexShift),
69 EGPIOIRQ_PIN_0 = EGPIOIRQ_FIRST,
70 EGPIOIRQ_PIN_1,
71 EGPIOIRQ_PIN_2,
72 EGPIOIRQ_PIN_3,
73 EGPIOIRQ_PIN_4,
74 EGPIOIRQ_PIN_5,
75 EGPIOIRQ_PIN_6,
76 EGPIOIRQ_PIN_7,
77 EGPIOIRQ_PIN_8,
78 EGPIOIRQ_PIN_9,
79 EGPIOIRQ_PIN_10,
80 EGPIOIRQ_PIN_11,
81 EGPIOIRQ_PIN_12,
82 EGPIOIRQ_PIN_13,
83 EGPIOIRQ_PIN_14,
84 EGPIOIRQ_PIN_15,
85 EGPIOIRQ_PIN_16,
86 EGPIOIRQ_PIN_17,
87 EGPIOIRQ_PIN_18,
88 EGPIOIRQ_PIN_19,
89 EGPIOIRQ_PIN_20,
90 EGPIOIRQ_PIN_21,
91 EGPIOIRQ_PIN_22,
92 EGPIOIRQ_PIN_23,
93 EGPIOIRQ_PIN_24,
94 EGPIOIRQ_PIN_25,
95 EGPIOIRQ_PIN_26,
96 EGPIOIRQ_PIN_27,
97 EGPIOIRQ_PIN_28,
98 EGPIOIRQ_PIN_29,
99 EGPIOIRQ_PIN_30,
100 EGPIOIRQ_PIN_31,
101 EGPIOIRQ_PIN_32,
102 EGPIOIRQ_PIN_33,
103 EGPIOIRQ_PIN_34,
104 EGPIOIRQ_PIN_35,
105 EGPIOIRQ_PIN_36,
106 EGPIOIRQ_PIN_37,
107 EGPIOIRQ_PIN_38,
108 EGPIOIRQ_PIN_39,
109 EGPIOIRQ_PIN_40,
110 EGPIOIRQ_PIN_41,
111 EGPIOIRQ_PIN_42,
112 EGPIOIRQ_PIN_43,
113 EGPIOIRQ_PIN_44,
114 EGPIOIRQ_PIN_45,
115 EGPIOIRQ_PIN_46,
116 EGPIOIRQ_PIN_47,
117 EGPIOIRQ_PIN_48,
118 EGPIOIRQ_PIN_49,
119 EGPIOIRQ_PIN_50,
120 EGPIOIRQ_PIN_51,
121 EGPIOIRQ_PIN_52,
122 EGPIOIRQ_PIN_53,
123 EGPIOIRQ_PIN_54,
124 EGPIOIRQ_PIN_55,
125 EGPIOIRQ_PIN_56,
126 EGPIOIRQ_PIN_57,
127 EGPIOIRQ_PIN_58,
128 EGPIOIRQ_PIN_59,
129 EGPIOIRQ_PIN_60,
130 EGPIOIRQ_PIN_61,
131 EGPIOIRQ_PIN_62,
132 EGPIOIRQ_PIN_63,
133 EGPIOIRQ_PIN_64,
134 EGPIOIRQ_PIN_65,
135 EGPIOIRQ_PIN_66,
136 EGPIOIRQ_PIN_67,
137 EGPIOIRQ_PIN_68,
138 EGPIOIRQ_PIN_69,
139 EGPIOIRQ_PIN_70,
140 EGPIOIRQ_PIN_71,
141 EGPIOIRQ_PIN_72,
142 EGPIOIRQ_PIN_73,
143 EGPIOIRQ_PIN_74,
144 EGPIOIRQ_PIN_75,
145 EGPIOIRQ_PIN_76,
146 EGPIOIRQ_PIN_77,
147 EGPIOIRQ_PIN_78,
148 EGPIOIRQ_PIN_79,
149 EGPIOIRQ_PIN_80,
150 EGPIOIRQ_PIN_81,
151 EGPIOIRQ_PIN_82,
152 EGPIOIRQ_PIN_83,
153 EGPIOIRQ_PIN_84,
154 EGPIOIRQ_PIN_85,
155 EGPIOIRQ_PIN_86,
156 EGPIOIRQ_PIN_87,
157 EGPIOIRQ_PIN_88,
158 EGPIOIRQ_PIN_89,
159 EGPIOIRQ_PIN_90,
160 EGPIOIRQ_PIN_91,
161 EGPIOIRQ_PIN_92,
162 EGPIOIRQ_PIN_93,
163 EGPIOIRQ_PIN_94,
164 EGPIOIRQ_PIN_95,
165 EGPIOIRQ_PIN_96,
166 EGPIOIRQ_PIN_97,
167 EGPIOIRQ_PIN_98,
168 EGPIOIRQ_PIN_99,
169 EGPIOIRQ_PIN_100,
170 EGPIOIRQ_PIN_101,
171 EGPIOIRQ_PIN_102,
172 EGPIOIRQ_PIN_103,
173 EGPIOIRQ_PIN_104,
174 EGPIOIRQ_PIN_105,
175 EGPIOIRQ_PIN_106,
176 EGPIOIRQ_PIN_107,
177 EGPIOIRQ_PIN_108,
178 EGPIOIRQ_PIN_109,
179 EGPIOIRQ_PIN_110,
180 EGPIOIRQ_PIN_111,
181 EGPIOIRQ_PIN_112,
182 EGPIOIRQ_PIN_113,
183 EGPIOIRQ_PIN_114,
184 EGPIOIRQ_PIN_115,
185 EGPIOIRQ_PIN_116,
186 EGPIOIRQ_PIN_117,
187 EGPIOIRQ_PIN_118,
188 EGPIOIRQ_PIN_119,
189 EGPIOIRQ_PIN_120,
190 EGPIOIRQ_PIN_121,
191 EGPIOIRQ_PIN_122,
192 EGPIOIRQ_PIN_123,
193 EGPIOIRQ_PIN_124,
194 EGPIOIRQ_PIN_125,
195 EGPIOIRQ_PIN_126,
196 EGPIOIRQ_PIN_127,
197 EGPIOIRQ_PIN_128,
198 EGPIOIRQ_PIN_129,
199 EGPIOIRQ_PIN_130,
200 EGPIOIRQ_PIN_131,
201 EGPIOIRQ_PIN_132,
202 EGPIOIRQ_PIN_133,
203 EGPIOIRQ_PIN_134,
204 EGPIOIRQ_PIN_135,
205 EGPIOIRQ_PIN_136,
206 EGPIOIRQ_PIN_137,
207 EGPIOIRQ_PIN_138,
208 EGPIOIRQ_PIN_139,
209 EGPIOIRQ_PIN_140,
210 EGPIOIRQ_PIN_141,
211 EGPIOIRQ_PIN_142,
212 EGPIOIRQ_PIN_143,
213 EGPIOIRQ_PIN_144,
214 EGPIOIRQ_PIN_145,
215 EGPIOIRQ_PIN_146,
216 EGPIOIRQ_PIN_147,
217 EGPIOIRQ_PIN_148,
218 EGPIOIRQ_PIN_149,
219 EGPIOIRQ_PIN_150,
220 EGPIOIRQ_PIN_151,
221 EGPIOIRQ_PIN_152,
222 EGPIOIRQ_PIN_153,
223 EGPIOIRQ_PIN_154,
224 EGPIOIRQ_PIN_155,
225 EGPIOIRQ_PIN_156,
226 EGPIOIRQ_PIN_157,
227 EGPIOIRQ_PIN_158,
228 EGPIOIRQ_PIN_159,
229 EGPIOIRQ_PIN_160,
230 EGPIOIRQ_PIN_161,
231 EGPIOIRQ_PIN_162,
232 EGPIOIRQ_PIN_163,
233 EGPIOIRQ_PIN_164,
234 EGPIOIRQ_PIN_165,
235 EGPIOIRQ_PIN_166,
236 EGPIOIRQ_PIN_167,
237 EGPIOIRQ_PIN_168,
238 EGPIOIRQ_PIN_169,
239 EGPIOIRQ_PIN_170,
240 EGPIOIRQ_PIN_171,
241 EGPIOIRQ_PIN_172,
242 EGPIOIRQ_PIN_173,
243 EGPIOIRQ_PIN_174,
244 EGPIOIRQ_PIN_175,
245 EGPIOIRQ_PIN_176,
246 EGPIOIRQ_PIN_177,
247 EGPIOIRQ_PIN_178,
248 EGPIOIRQ_PIN_179,
249 EGPIOIRQ_PIN_180,
250 EGPIOIRQ_PIN_181,
251 EGPIOIRQ_PIN_182,
252 EGPIOIRQ_PIN_183,
253 EGPIOIRQ_PIN_184,
254 EGPIOIRQ_PIN_185,
255 EGPIOIRQ_PIN_186,
256 EGPIOIRQ_PIN_187,
257 EGPIOIRQ_PIN_188,
258 EGPIOIRQ_PIN_189,
259 EGPIOIRQ_PIN_190,
260 EGPIOIRQ_PIN_191,
262 EGPIOIRQ_END
263 };
267 const TInt32 KHwGpioPinMax = 192; // 32*6 pins
268 const TInt32 KHwGpioPinsPerBank = 32;
269 const TInt32 KHwGpioBanks = KHwGpioPinMax / KHwGpioPinsPerBank ;
271 // Utility code to convert a pin number to a GPIO bank
272 const TUint KGPIO_BASE_ADDRESSES[] = { KGPIO1, KGPIO2, KGPIO3, KGPIO4, KGPIO5, KGPIO6 };
278 inline TUint GPIO_BASE_ADDRESS(TInt aPin) {return KGPIO_BASE_ADDRESSES[(TInt)(aPin/KHwGpioPinsPerBank)];};
279 #define GPIO_PIN_BANK(aId) ((aId)/KHwGpioPinsPerBank)
280 #define GPIO_PIN_OFFSET(aId) (1 << (aId%KHwGpioPinsPerBank))
281 #define GPIO_PIN_BOUNDS(aId)((aId > 0) && (aId <KHwGpioPinMax))
283 class GpioPin
284 {
285 public:
286 GPIO::TGpioMode iMode;
287 TUint iBankAddr;
288 TUint iBank;
289 SInterruptHandler irq;
290 TUint iIrqVector;
291 };
293 #endif // __OMAP3530_GPIO_H__