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epoc32/include/assp/omap3530_assp/omap3530_uart.h
author William Roberts <williamr@symbian.org>
Wed, 31 Mar 2010 12:33:34 +0100
branchSymbian3
changeset 4 837f303aceeb
permissions -rw-r--r--
Current Symbian^3 public API header files (from PDK 3.0.h)
This is the epoc32/include tree with the "platform" subtrees removed, and
all but a selected few mbg and rsg files removed. 
     1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).

     2 // All rights reserved.

     3 // This component and the accompanying materials are made available

     4 // under the terms of the License "Eclipse Public License v1.0"

     5 // which accompanies this distribution, and is available

     6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".

     7 //

     8 // Initial Contributors:

     9 // Nokia Corporation - initial contribution.

    10 //

    11 // Contributors:

    12 //

    13 // Description:

    14 // omap3530/omap3530_drivers/uart/omap3530_uart.h

    15 // This file is part of the Beagle Base port

    16 //

    17 

    18 #ifndef __OMAP3530_UART_H__

    19 #define __OMAP3530_UART_H__

    20 

    21 #include <assp/omap3530_assp/omap3530_hardware_base.h>

    22 #include <assp/omap3530_assp/omap3530_prcm.h>

    23 //#include "assp/omap3530_assp/omap3530_prm.h"

    24 #include <assp/omap3530_assp/omap3530_irqmap.h>

    25 

    26 //#include "omap3530_prm.h"

    27 

    28 

    29 namespace Omap3530Uart

    30 {

    31 using namespace TexasInstruments::Omap3530;

    32 

    33 enum TUartNumber

    34 	{

    35 	EUartNone = -1,

    36 	EUart0 = 0,

    37 	EUart1,

    38 	EUart2

    39 	};

    40 

    41 template< const TUartNumber aUartNumber >

    42 struct TUartTraits

    43 	{

    44 	};

    45 

    46 template<>

    47 struct TUartTraits< EUart0 >

    48 	{

    49 	static const TUint32 KBaseAddress = Omap3530HwBase::KL4_Core + 0x0006A000;

    50 	static const TInt KInterruptId = EOmap3530_IRQ72_UART1_IRQ;

    51 	static const Prcm::TClock	KInterfaceClock = Prcm::EClkUart1_I;

    52 	static const Prcm::TClock	KFunctionClock = Prcm::EClkUart1_F;

    53 //	static const Omap3530Prm::TPrmId	KPrmInterfaceClock = Omap3530Prm::EPrmClkUart1_I;

    54 //	static const Omap3530Prm::TPrmId	KPrmFunctionClock = Omap3530Prm::EPrmClkUart1_F;

    55 	};

    56 

    57 template<>

    58 struct TUartTraits< EUart1 >

    59 	{

    60 	static const TUint32 KBaseAddress = Omap3530HwBase::KL4_Core + 0x0006C000;

    61 	static const TInt KInterruptId = EOmap3530_IRQ73_UART2_IRQ;

    62 	static const Prcm::TClock	KInterfaceClock = Prcm::EClkUart2_I;

    63 	static const Prcm::TClock	KFunctionClock = Prcm::EClkUart2_F;

    64 //	static const Omap3530Prm::TPrmId	KPrmInterfaceClock = Omap3530Prm::EPrmClkUart2_I;

    65 //	static const Omap3530Prm::TPrmId	KPrmFunctionClock = Omap3530Prm::EPrmClkUart2_F;

    66 	};

    67 

    68 template<>

    69 struct TUartTraits< EUart2 >

    70 	{

    71 	static const TUint32 KBaseAddress = Omap3530HwBase::KL4_Per + 0x00020000;

    72 	static const TInt KInterruptId = EOmap3530_IRQ74_UART3_IRQ;

    73 	static const Prcm::TClock	KInterfaceClock = Prcm::EClkUart3_I;

    74 	static const Prcm::TClock	KFunctionClock = Prcm::EClkUart3_F;

    75 //	static const Omap3530Prm::TPrmId	KPrmInterfaceClock = Omap3530Prm::EPrmClkUart3_I;

    76 //	static const Omap3530Prm::TPrmId	KPrmFunctionClock = Omap3530Prm::EPrmClkUart3_F;

    77 	};

    78 

    79 // Forward declaration

    80 class TUart;

    81 

    82 

    83 /** Representation of general UART register set */

    84 struct DLL

    85 	{

    86 	static const TInt KOffset	= 0x00;

    87 	static TDynReg8_RW< TUart, KOffset >	iMem;

    88 	typedef TBitField<0,8>	CLOCK_LSB;

    89 	};

    90 

    91 struct RHR

    92 	{

    93 	static const TInt KOffset	= 0x00;

    94 	static TDynReg8_R< TUart, KOffset >	iMem;

    95 	typedef TBitField<0,8>	Value;

    96 	};

    97 

    98 struct THR

    99 	{

   100 	static const TInt KOffset	= 0x00;

   101 	static TDynReg8_W< TUart, KOffset >	iMem;

   102 	typedef TBitField<0,8>	Value;

   103 	};

   104 

   105 struct IER

   106 	{

   107 	static const TInt KOffset	= 0x04;

   108 	static TDynReg8_RW< TUart, KOffset >	iMem;

   109 	typedef TSingleBitField<7>	CTS_IT;

   110 	typedef TSingleBitField<6>	RTS_IT;

   111 	typedef TSingleBitField<5>	XOFF_IT;

   112 	typedef TSingleBitField<4>	SLEEP_MODE;

   113 	typedef TSingleBitField<3>	MODEM_STS_IT;

   114 	typedef TSingleBitField<2>	LINE_STS_IT;

   115 	typedef TSingleBitField<1>	THR_IT;

   116 	typedef TSingleBitField<0>	RHR_IT;

   117 	};

   118 

   119 struct IER_IRDA

   120 	{

   121 	static const TInt KOffset	= 0x04;

   122 	static TDynReg8_RW< TUart, KOffset >	iMem;

   123 	typedef TSingleBitField<7>	EOF_IT;

   124 	typedef TSingleBitField<6>	LINE_STS_IT;

   125 	typedef TSingleBitField<5>	TX_STATUS_IT;

   126 	typedef TSingleBitField<4>	STS_FIFO_TRIG_IT;

   127 	typedef TSingleBitField<3>	RX_OVERRUN_IT;

   128 	typedef TSingleBitField<2>	LAST_RX_BYTE_IT;

   129 	typedef TSingleBitField<1>	THR_IT;

   130 	typedef TSingleBitField<0>	RHR_IT;

   131 	};

   132 

   133 struct DLH

   134 	{

   135 	static const TInt KOffset	= 0x04;

   136 	static TDynReg8_RW< TUart, KOffset >	iMem;

   137 	typedef TBitField<0,6>	CLOCK_MSB;

   138 	};

   139 

   140 struct FCR

   141 	{

   142 	static const TInt KOffset	= 0x08;

   143 	static TDynReg8_W< TUart, KOffset >	iMem;

   144 	typedef TSingleBitField<0>	FIFO_EN;

   145 	typedef TSingleBitField<1>	RX_FIFO_CLEAR;

   146 	typedef	TSingleBitField<2>	TX_FIFO_CLEAR;

   147 	typedef TSingleBitField<3>	DMA_MODE;

   148 	struct TX_FIFO_TRIG : public TBitField<4,2>

   149 		{

   150 		enum TConstants

   151 			{

   152 			K8Char	= 0 << KShift,

   153 			K16Char	= 1 << KShift,

   154 			K32Char	= 2 << KShift,

   155 			K56Char	= 3 << KShift

   156 			};

   157 		};

   158 	struct RX_FIFO_TRIG : public TBitField<6,2>

   159 		{

   160 		static const TUint8	K8Char	= 0 << KShift;

   161 		static const TUint8	K16Char	= 1 << KShift;

   162 		static const TUint8	K56Char	= 2 << KShift;

   163 		static const TUint8	K60Char	= 3 << KShift;

   164 		};

   165 	};

   166 

   167 struct IIR

   168 	{

   169 	static const TInt KOffset	= 0x08;

   170 	static TDynReg8_R< TUart, KOffset >	iMem;

   171 	typedef TBitField<6,2>	FCR_MIRROR;

   172 	struct IT_TYPE : public TBitField<1,5>

   173 		{

   174 		enum TConstants

   175 			{

   176 			EModem	= 0 << KShift,

   177 			ETHR	= 1 << KShift,

   178 			ERHR	= 2 << KShift,

   179 			ERxLineStatus	= 3 << KShift,

   180 			ERxTimeout		= 6 << KShift,

   181 			EXoff			= 8 << KShift,

   182 			ECtsRts			= 16  << KShift

   183 			};

   184 		};

   185 	typedef TSingleBitField<0>	IT_PENDING;

   186 	};

   187 

   188 struct EFR

   189 	{

   190 	static const TInt KOffset	= 0x08;

   191 	static TDynReg8_RW< TUart, KOffset >	iMem;

   192 	typedef TSingleBitField<7>	AUTO_CTS_EN;

   193 	typedef TSingleBitField<6>	AUTO_RTS_EN;

   194 	typedef TSingleBitField<5>	SPEC_CHAR;

   195 	typedef TSingleBitField<4>	ENHANCED_EN;

   196 	struct SW_FLOW_CONTROL : public TBitField<0,4>

   197 		{

   198 		enum TFlowControl

   199 			{

   200 			ENone		= 0,

   201 			EXonXoff1	= 8,

   202 			EXonXoff2	= 4,

   203 			EXonXoffBoth = 8 + 4,

   204 			};

   205 		};

   206 	};

   207 

   208 struct LCR

   209 	{

   210 	static const TInt KOffset	= 0x0c;

   211 	static TDynReg8_RW< TUart, KOffset >	iMem;

   212 	typedef TSingleBitField<7>	DIV_EN;

   213 	typedef TSingleBitField<6>	BREAK_EN;

   214 	typedef TSingleBitField<5>	PARITY_TYPE2;

   215 	typedef TSingleBitField<4>	PARITY_TYPE1;

   216 	typedef TSingleBitField<3>	PARITY_EN;

   217 	struct NB_STOP : public TSingleBitField<2>

   218 		{

   219 		enum TConstants

   220 			{

   221 			E1Stop		= 0 << KShift,

   222 			E1_5Stop	= 1 << KShift,

   223 			E2Stop		= 1 << KShift

   224 			};

   225 		};

   226 	struct CHAR_LENGTH : public TBitField<0,2>

   227 		{

   228 		enum TConstants

   229 			{

   230 			E5Bits		= 0,

   231 			E6Bits		= 1,

   232 			E7Bits		= 2,

   233 			E8Bits		= 3

   234 			};

   235 		};

   236 

   237 	/** Special magic number to enter MODEA */

   238 	static const TUint8 KConfigModeA = 0x80;

   239 

   240 	/** Special magic number to enter MODEB */

   241 	static const TUint8 KConfigModeB = 0xBF;

   242 

   243 	/** Special magic number to enter operational mode */

   244 	static const TUint8 KConfigModeOperational = 0x00;

   245 	};

   246 

   247 struct MCR

   248 	{

   249 	static const TInt KOffset	= 0x10;

   250 	static TDynReg8_RW< TUart, KOffset >	iMem;

   251 	typedef TSingleBitField<6>	TCR_TLR;

   252 	typedef TSingleBitField<5>	XON_EN;

   253 	typedef TSingleBitField<4>	LOOPBACK_EN;

   254 	typedef TSingleBitField<3>	CD_STS_CH;

   255 	typedef TSingleBitField<2>	RI_STS_CH;

   256 	typedef TSingleBitField<1>	RTS;

   257 	typedef TSingleBitField<0>	DTR;

   258 	};

   259 

   260 struct XON1_ADDR1

   261 	{

   262 	static const TInt KOffset	= 0x10;

   263 	static TDynReg8_RW< TUart, KOffset >	iMem;

   264 	typedef TBitField<0,8>	Value;

   265 	};

   266 

   267 struct LSR

   268 	{

   269 	static const TInt KOffset	= 0x14;

   270 	static TDynReg8_R< TUart, KOffset >	iMem;

   271 	typedef TSingleBitField<7>	RX_FIFO_STS;

   272 	typedef TSingleBitField<6>	TX_SR_E;

   273 	typedef TSingleBitField<5>	TX_FIFO_E;

   274 	typedef TSingleBitField<4>	RX_BI;

   275 	typedef TSingleBitField<3>	RX_FE;

   276 	typedef TSingleBitField<2>	RX_PE;

   277 	typedef TSingleBitField<1>	RX_OE;

   278 	typedef TSingleBitField<0>	RX_FIFO_E;

   279 	};

   280 

   281 struct XON2_ADDR2

   282 	{

   283 	static const TInt KOffset	= 0x14;

   284 	static TDynReg8_RW< TUart, KOffset >	iMem;

   285 	typedef TBitField<0,8>	Value;

   286 	};

   287 

   288 struct XOFF1

   289 	{

   290 	static const TInt KOffset	= 0x18;

   291 	static TDynReg8_RW< TUart, KOffset >	iMem;

   292 	typedef TBitField<0,8>	Value;

   293 	};

   294 

   295 struct TCR

   296 	{

   297 	static const TInt KOffset	= 0x18;

   298 	static TDynReg8_RW< TUart, KOffset >	iMem;

   299 	typedef TBitField<4,4>	RX_FIFO_TRIG_START;

   300 	typedef TBitField<0,4>	RX_FIFO_TRIG_HALT;

   301 	};

   302 

   303 struct MSR

   304 	{

   305 	static const TInt KOffset	= 0x18;

   306 	static TDynReg8_R< TUart, KOffset >	iMem;

   307 	typedef TSingleBitField<7>	NCD_STS;

   308 	typedef TSingleBitField<6>	NRI_STS;

   309 	typedef TSingleBitField<5>	NDSR_STS;

   310 	typedef TSingleBitField<4>	NCTS_STS;

   311 	typedef TSingleBitField<3>	DCD_STS;

   312 	typedef TSingleBitField<2>	RI_STS;

   313 	typedef TSingleBitField<1>	DSR_STS;

   314 	typedef TSingleBitField<0>	CTS_STS;

   315 	};

   316 

   317 struct SPR

   318 	{

   319 	static const TInt KOffset	= 0x1c;

   320 	static TDynReg8_RW< TUart, KOffset >	iMem;

   321 	typedef TBitField<0,8>	SPR_WORD;

   322 	};

   323 

   324 struct XOFF2

   325 	{

   326 	static const TInt KOffset	= 0x1c;

   327 	static TDynReg8_RW< TUart, KOffset >	iMem;

   328 	typedef TBitField<0,8>	Value;

   329 	};

   330 

   331 struct TLR

   332 	{

   333 	static const TInt KOffset	= 0x1c;

   334 	static TDynReg8_RW< TUart, KOffset >	iMem;

   335 	typedef TBitField<4,4>	RX_FIFO_TRIG_DMA;

   336 	typedef TBitField<0,4>	TX_FIFO_TRIG_DMA;

   337 	};

   338 

   339 struct MDR1

   340 	{

   341 	static const TInt KOffset	= 0x20;

   342 	static TDynReg8_RW< TUart, KOffset >	iMem;

   343 	typedef TSingleBitField<7>	FRAME_END_MODE;

   344 	typedef TSingleBitField<6>	SIP_MODE;

   345 	typedef TSingleBitField<5>	SCT;

   346 	typedef TSingleBitField<4>	SET_TXIR;

   347 	typedef TSingleBitField<3>	IR_SLEEP;

   348 	struct MODE_SELECT : public TBitField<0,3>

   349 		{

   350 		enum TMode

   351 			{

   352 			EUart16x		= 0,

   353 			ESIR			= 1,

   354 			EUart16xAutoBaud = 2,

   355 			EUart13x		= 3,

   356 			EMIR			= 4,

   357 			EFIR			= 5,

   358 			ECIR			= 6,

   359 			EDisable		= 7

   360 			};

   361 		};

   362 	};

   363 

   364 struct MDR2

   365 	{

   366 	static const TInt KOffset	= 0x24;

   367 	static TDynReg8_RW< TUart, KOffset >	iMem;

   368 	typedef TSingleBitField<6>	IRRXINVERT;

   369 	struct CIR_PULSE_MODE : public TBitField<4,2>

   370 		{

   371 		enum TConstants

   372 			{

   373 			EPw3	= 0 << KShift,

   374 			EPw4	= 1 << KShift,

   375 			EPw5	= 2 << KShift,

   376 			EPw6	= 3 << KShift

   377 			};

   378 		};

   379 	typedef TSingleBitField<3>	UART_PULSE;

   380 	struct STS_FIFO_TRIG : public TBitField<1,2>

   381 		{

   382 		enum TConstants

   383 			{

   384 			E1Entry		= 0 << KShift,

   385 			E4Entry		= 1 << KShift,

   386 			E7Entry		= 2 << KShift,

   387 			E8Entry		= 3 << KShift

   388 			};

   389 		};

   390 	typedef TSingleBitField<0>	IRTX_UNDERRUN;

   391 	};

   392 

   393 struct TXFLL

   394 	{

   395 	static const TInt KOffset	= 0x28;

   396 	static TDynReg8_W< TUart, KOffset >	iMem;

   397 	typedef TBitField<0,8>	TX_FLL;

   398 	};

   399 

   400 struct SFLSR

   401 	{

   402 	static const TInt KOffset	= 0x28;

   403 	static TDynReg8_R< TUart, KOffset >	iMem;

   404 	typedef TSingleBitField<4>	OE_ERROR;

   405 	typedef TSingleBitField<3>	FTL_ERROR;

   406 	typedef TSingleBitField<2>	ABORT_DETECT;

   407 	typedef TSingleBitField<1>	CRC_ERROR;

   408 	};

   409 

   410 struct RESUME

   411 	{

   412 	static const TInt KOffset	= 0x2c;

   413 	static TDynReg8_R< TUart, KOffset >	iMem;

   414 	typedef TBitField<0,8>	Value;

   415 	};

   416 

   417 struct TXFLH

   418 	{

   419 	static const TInt KOffset	= 0x2c;

   420 	static TDynReg8_W< TUart, KOffset >	iMem;

   421 	typedef TBitField<0,5>	TX_FLH;

   422 	};

   423 

   424 struct RXFLL

   425 	{

   426 	static const TInt KOffset	= 0x30;

   427 	static TDynReg8_W< TUart, KOffset >	iMem;

   428 	typedef TBitField<0,8>	RX_FLL;

   429 	};

   430 

   431 struct SFREGL

   432 	{

   433 	static const TInt KOffset	= 0x30;

   434 	static TDynReg8_R< TUart, KOffset >	iMem;

   435 	typedef TBitField<0,8>	Value;

   436 	};

   437 

   438 struct SFREGH

   439 	{

   440 	static const TInt KOffset	= 0x34;

   441 	static TDynReg8_R< TUart, KOffset >	iMem;

   442 	typedef TBitField<0,4>	Value;

   443 	};

   444 

   445 struct RXFLH

   446 	{

   447 	static const TInt KOffset	= 0x34;

   448 	static TDynReg8_W< TUart, KOffset >	iMem;

   449 	typedef TBitField<0,4>	RX_FLH;

   450 	};

   451 

   452 struct BLR

   453 	{

   454 	typedef TSingleBitField<7>	STS_FIFO_RESET;

   455 	typedef TSingleBitField<6>	XBOF_TYPE;

   456 	};

   457 

   458 struct UASR

   459 	{

   460 	static const TInt KOffset	= 0x38;

   461 	static TDynReg8_R< TUart, KOffset >	iMem;

   462 	struct PARITY_TYPE : public TBitField<6,2>

   463 		{

   464 		enum TConstants

   465 			{

   466 			ENone	= 0 << KShift,

   467 			ESpace	= 1 << KShift,

   468 			EEven	= 2 << KShift,

   469 			EOdd	= 3 << KShift

   470 			};

   471 		};

   472 	struct BIT_BY_CHAR : public TSingleBitField<5>

   473 		{

   474 		enum TConstants

   475 			{

   476 			E7Bit	= 0 << KShift,

   477 			E8Bit	= 1 << KShift

   478 			};

   479 		};

   480 	struct SPEED : public TBitField<0,5>

   481 		{

   482 		enum TBaud

   483 			{

   484 			EUnknown	= 0,

   485 			E115200		= 1,

   486 			E57600		= 2,

   487 			E38400		= 3,

   488 			E28800		= 4,

   489 			E19200		= 5,

   490 			E14400		= 6,

   491 			E9600		= 7,

   492 			E4800		= 8,

   493 			E4800_2		= 9,

   494 			E1200		= 10

   495 			};

   496 		};

   497 	};

   498 

   499 struct ACREG

   500 	{

   501 	static const TInt KOffset	= 0x3c;

   502 	static TDynReg8_RW< TUart, KOffset >	iMem;

   503 	typedef TSingleBitField<7>	PULSE_TYPE;

   504 	typedef TSingleBitField<6>	SID_MOD;

   505 	typedef TSingleBitField<5>	DIS_IR_RX;

   506 	typedef TSingleBitField<4>	DIS_TX_UNDERRUN;

   507 	typedef TSingleBitField<3>	SEND_SIP;

   508 	typedef TSingleBitField<2>	SCTX_EN;

   509 	typedef TSingleBitField<1>	ABORT_EN;

   510 	typedef TSingleBitField<0>	EOT_EN;

   511 	};

   512 

   513 struct SCR

   514 	{

   515 	static const TInt KOffset	= 0x40;

   516 	static TDynReg8_RW< TUart, KOffset >	iMem;

   517 	typedef TSingleBitField<7>	RX_TRIG_GRANU1;

   518 	typedef TSingleBitField<6>	TX_TRIG_GRANU1;

   519 	typedef TSingleBitField<4>	RX_CTS_WU_EN;

   520 	typedef TSingleBitField<3>	TX_EMPTY_CTL_IT;

   521 	typedef TBitField<1,2>		DMA_MODE2;

   522 	typedef TSingleBitField<0>	DMA_MODE_CTL;

   523 	};

   524 

   525 struct SSR

   526 	{

   527 	static const TInt KOffset	= 0x44;

   528 	static TDynReg8_R< TUart, KOffset >	iMem;

   529 	typedef TSingleBitField<1>	RX_CTS_WU_STS;

   530 	typedef TSingleBitField<0>	TX_FIFO_FULL;

   531 	};

   532 

   533 struct EBLR

   534 	{

   535 	static const TInt KOffset	= 0x48;

   536 	static TDynReg8_RW< TUart, KOffset >	iMem;

   537 	typedef TBitField<0,8>	Value;

   538 	};

   539 

   540 struct SYSC

   541 	{

   542 	static const TInt KOffset	= 0x54;

   543 	static TDynReg8_RW< TUart, KOffset >	iMem;

   544 	struct IDLE_MODE : public TBitField<3,2>

   545 		{

   546 		enum TMode

   547 			{

   548 			EForceIdle	= 0 << KShift,

   549 			ENoIdle		= 1 << KShift,

   550 			ESmartIdle	= 2 << KShift

   551 			};

   552 		};

   553 	typedef TSingleBitField<2>	ENAWAKEUP;

   554 	typedef TSingleBitField<1>	SOFTRESET;

   555 	typedef TSingleBitField<0>	AUTOIDLE;

   556 	};

   557 

   558 struct SYSS

   559 	{

   560 	static const TInt KOffset	= 0x58;

   561 	static TDynReg8_R< TUart, KOffset >	iMem;

   562 	typedef TSingleBitField<0>	RESETDONE;

   563 	};

   564 

   565 struct WER

   566 	{

   567 	static const TInt KOffset	= 0x5c;

   568 	static TDynReg8_RW< TUart, KOffset >	iMem;

   569 	typedef TSingleBitField<6>	EVENT_6_RLS_INTERRUPT;

   570 	typedef TSingleBitField<5>	EVENT_5_RHR_INTERRUPT;

   571 	typedef TSingleBitField<4>	EVENT_4_RX_ACTIVITY;

   572 	typedef TSingleBitField<2>	EVENT_2_RI_ACTIVITY;

   573 	typedef TSingleBitField<0>	EVENT_0_CTS_ACTIVITY;

   574 	};

   575 

   576 struct CFPS

   577 	{

   578 	static const TInt KOffset	= 0x60;

   579 	static TDynReg8_RW< TUart, KOffset >	iMem;

   580 	typedef TBitField<0,8>	Value;

   581 	};

   582 

   583 

   584 class TUart

   585 	{

   586 	public:

   587 		enum TBaud

   588 			{

   589 			E1200,

   590 			E2400,

   591 			E4800,

   592 			E9600,

   593 			E14400,

   594 			E19200,

   595 			E28800,

   596 			E38400,

   597 			E57600,

   598 			E115200,

   599 			E230400,

   600 			E460800,

   601 			E921600,

   602 			E1843000,

   603 			E3688400,

   604 			E4000000,		// FIR

   605 

   606 			KSupportedBaudCount

   607 			};

   608 

   609 		enum TParity

   610 			{

   611 			ENone,

   612 			EOdd,

   613 			EEven,

   614 			EMark,

   615 			ESpace

   616 			};

   617 

   618 		enum TDataBits

   619 			{

   620 			E5Data = ::Omap3530Uart::LCR::CHAR_LENGTH::E5Bits,

   621 			E6Data = ::Omap3530Uart::LCR::CHAR_LENGTH::E6Bits,

   622 			E7Data = ::Omap3530Uart::LCR::CHAR_LENGTH::E7Bits,

   623 			E8Data = ::Omap3530Uart::LCR::CHAR_LENGTH::E8Bits,

   624 			};

   625 

   626 		enum TStopBits

   627 			{

   628 			E1Stop = ::Omap3530Uart::LCR::NB_STOP::E1Stop,

   629 			E1_5Stop = ::Omap3530Uart::LCR::NB_STOP::E1_5Stop,

   630 			E2Stop = ::Omap3530Uart::LCR::NB_STOP::E2Stop,

   631 			};

   632 

   633 		enum TUartMode

   634 			{

   635 			EUart,

   636 			EUartAutoBaud,

   637 			ESIR,

   638 			EMIR,

   639 			EFIR,

   640 			ECIR,

   641 

   642 			KSupportedUartModes

   643 			};

   644 

   645 		enum TFifoTrigger

   646 			{

   647 			ETrigger8,

   648 			ETrigger16,

   649 			ETrigger32,

   650 			ETrigger56,

   651 			ETrigger60,

   652 			ETriggerUnchanged

   653 			};

   654 

   655 		enum TEnableState

   656 			{

   657 			EDisabled,

   658 			EEnabled

   659 			};

   660 

   661 		enum TInterrupt

   662 			{

   663 			EIntRhr = 0,

   664 			EIntThr = 1,

   665 			EIntLineStatus = 2,

   666 			EIntModemStatus = 3,

   667 			EIntXoff = 5,

   668 			EIntRts = 6,

   669 			EIntCts = 7

   670 			};

   671 

   672 	public:

   673 		inline TUart( const TUartNumber aUartNumber )

   674 			: iBase(	(aUartNumber == EUart0 )	?	TUartTraits<EUart0>::KBaseAddress

   675 							:	(aUartNumber == EUart1 )	?	TUartTraits<EUart1>::KBaseAddress

   676 							:	(aUartNumber == EUart2 )	?	TUartTraits<EUart2>::KBaseAddress

   677 							:	0 ),

   678 				iUartNumber( aUartNumber )

   679 			{}

   680 

   681 		FORCE_INLINE TLinAddr Base() const

   682 			{ return iBase; }

   683 

   684 		IMPORT_C TInt InterruptId() const;

   685 

   686 		IMPORT_C Prcm::TClock PrcmInterfaceClk() const;

   687 		

   688 		IMPORT_C Prcm::TClock PrcmFunctionClk() const;

   689 

   690 //		IMPORT_C TInt PrmInterfaceClk() const;

   691 		

   692 //		IMPORT_C TInt PrmFunctionClk() const;

   693 

   694 		/** Reset and initialize the UART 

   695 		 * On return the UART will be in disable mode */

   696 		IMPORT_C void Init();

   697 

   698 		/** Defines which mode the UART will run in when enabled, but does not configure that mode

   699 		 * You must call this before calling SetBaud to ensure that correct baud rate multiplier is used */

   700 		IMPORT_C void DefineMode( const TUartMode aMode );

   701 

   702 		/** Enabled the UART in the defined mode

   703 		 * You must call DefineMode() and SetBaud() before calling Enable()

   704 		 */

   705 		IMPORT_C void Enable();

   706 

   707 		/** Disables the UART */

   708 		IMPORT_C void Disable();

   709 

   710 		/** Set the baud rate 

   711 		 * Do not call this while the UART is enabled

   712 		 * You must have previously called DefineMode()

   713 		 */

   714 		IMPORT_C void SetBaud( const TBaud aBaud );

   715 

   716 		/** Set the data length, parity and stop bits */

   717 		IMPORT_C void SetDataFormat( const TDataBits aDataBits, const TStopBits aStopBits, const TParity aParity );

   718 

   719 		/** Setup the FIFO configuration */

   720 		IMPORT_C void EnableFifo( const TEnableState aState, const TFifoTrigger aRxTrigger = ETriggerUnchanged, const TFifoTrigger aTxTrigger = ETriggerUnchanged );

   721 

   722 		/** Enable a particular interrupt source */

   723 		IMPORT_C void EnableInterrupt( const TInterrupt aWhich );

   724 

   725 		/** Disable a particular interrupt source */

   726 		IMPORT_C void DisableInterrupt( const TInterrupt aWhich );

   727 

   728 		/** Disable all interrupts */

   729 		IMPORT_C void DisableAllInterrupts();

   730 

   731 		inline TBool TxFifoFull()

   732 			{ return SSR::iMem.Read(*this) bitand SSR::TX_FIFO_FULL::KMask; }

   733 

   734 		inline TBool TxFifoEmpty()

   735 			{ return LSR::iMem.Read(*this) bitand LSR::TX_FIFO_E::KMask; }

   736 

   737 		inline TBool RxFifoEmpty()

   738 			{ return !(LSR::iMem.Read(*this) bitand LSR::RX_FIFO_E::KMask); }

   739 

   740 		inline void Write( TUint8 aByte )

   741 			{ THR::iMem.Write( *this, aByte ); }

   742 

   743 		inline TUint8 Read()

   744 			{ return RHR::iMem.Read( *this ); }

   745 

   746 	private:

   747 		TUart();

   748 

   749 	public:

   750 		const TLinAddr	iBase;

   751 		const TUartNumber	iUartNumber : 8;

   752 		TUartMode		iMode : 8;

   753 		::Omap3530Uart::MDR1::MODE_SELECT::TMode	iTargetMode : 8;

   754 	};

   755 

   756 

   757 } // Omap3530Uart

   758 

   759 #endif // ndef __OMAP3530_UART_H__

   760
test