1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/epoc32/include/assp/omap3530_assp/omap3530_uart.h Wed Mar 31 12:33:34 2010 +0100
1.3 @@ -0,0 +1,760 @@
1.4 +// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// omap3530/omap3530_drivers/uart/omap3530_uart.h
1.18 +// This file is part of the Beagle Base port
1.19 +//
1.20 +
1.21 +#ifndef __OMAP3530_UART_H__
1.22 +#define __OMAP3530_UART_H__
1.23 +
1.24 +#include <assp/omap3530_assp/omap3530_hardware_base.h>
1.25 +#include <assp/omap3530_assp/omap3530_prcm.h>
1.26 +//#include "assp/omap3530_assp/omap3530_prm.h"
1.27 +#include <assp/omap3530_assp/omap3530_irqmap.h>
1.28 +
1.29 +//#include "omap3530_prm.h"
1.30 +
1.31 +
1.32 +namespace Omap3530Uart
1.33 +{
1.34 +using namespace TexasInstruments::Omap3530;
1.35 +
1.36 +enum TUartNumber
1.37 + {
1.38 + EUartNone = -1,
1.39 + EUart0 = 0,
1.40 + EUart1,
1.41 + EUart2
1.42 + };
1.43 +
1.44 +template< const TUartNumber aUartNumber >
1.45 +struct TUartTraits
1.46 + {
1.47 + };
1.48 +
1.49 +template<>
1.50 +struct TUartTraits< EUart0 >
1.51 + {
1.52 + static const TUint32 KBaseAddress = Omap3530HwBase::KL4_Core + 0x0006A000;
1.53 + static const TInt KInterruptId = EOmap3530_IRQ72_UART1_IRQ;
1.54 + static const Prcm::TClock KInterfaceClock = Prcm::EClkUart1_I;
1.55 + static const Prcm::TClock KFunctionClock = Prcm::EClkUart1_F;
1.56 +// static const Omap3530Prm::TPrmId KPrmInterfaceClock = Omap3530Prm::EPrmClkUart1_I;
1.57 +// static const Omap3530Prm::TPrmId KPrmFunctionClock = Omap3530Prm::EPrmClkUart1_F;
1.58 + };
1.59 +
1.60 +template<>
1.61 +struct TUartTraits< EUart1 >
1.62 + {
1.63 + static const TUint32 KBaseAddress = Omap3530HwBase::KL4_Core + 0x0006C000;
1.64 + static const TInt KInterruptId = EOmap3530_IRQ73_UART2_IRQ;
1.65 + static const Prcm::TClock KInterfaceClock = Prcm::EClkUart2_I;
1.66 + static const Prcm::TClock KFunctionClock = Prcm::EClkUart2_F;
1.67 +// static const Omap3530Prm::TPrmId KPrmInterfaceClock = Omap3530Prm::EPrmClkUart2_I;
1.68 +// static const Omap3530Prm::TPrmId KPrmFunctionClock = Omap3530Prm::EPrmClkUart2_F;
1.69 + };
1.70 +
1.71 +template<>
1.72 +struct TUartTraits< EUart2 >
1.73 + {
1.74 + static const TUint32 KBaseAddress = Omap3530HwBase::KL4_Per + 0x00020000;
1.75 + static const TInt KInterruptId = EOmap3530_IRQ74_UART3_IRQ;
1.76 + static const Prcm::TClock KInterfaceClock = Prcm::EClkUart3_I;
1.77 + static const Prcm::TClock KFunctionClock = Prcm::EClkUart3_F;
1.78 +// static const Omap3530Prm::TPrmId KPrmInterfaceClock = Omap3530Prm::EPrmClkUart3_I;
1.79 +// static const Omap3530Prm::TPrmId KPrmFunctionClock = Omap3530Prm::EPrmClkUart3_F;
1.80 + };
1.81 +
1.82 +// Forward declaration
1.83 +class TUart;
1.84 +
1.85 +
1.86 +/** Representation of general UART register set */
1.87 +struct DLL
1.88 + {
1.89 + static const TInt KOffset = 0x00;
1.90 + static TDynReg8_RW< TUart, KOffset > iMem;
1.91 + typedef TBitField<0,8> CLOCK_LSB;
1.92 + };
1.93 +
1.94 +struct RHR
1.95 + {
1.96 + static const TInt KOffset = 0x00;
1.97 + static TDynReg8_R< TUart, KOffset > iMem;
1.98 + typedef TBitField<0,8> Value;
1.99 + };
1.100 +
1.101 +struct THR
1.102 + {
1.103 + static const TInt KOffset = 0x00;
1.104 + static TDynReg8_W< TUart, KOffset > iMem;
1.105 + typedef TBitField<0,8> Value;
1.106 + };
1.107 +
1.108 +struct IER
1.109 + {
1.110 + static const TInt KOffset = 0x04;
1.111 + static TDynReg8_RW< TUart, KOffset > iMem;
1.112 + typedef TSingleBitField<7> CTS_IT;
1.113 + typedef TSingleBitField<6> RTS_IT;
1.114 + typedef TSingleBitField<5> XOFF_IT;
1.115 + typedef TSingleBitField<4> SLEEP_MODE;
1.116 + typedef TSingleBitField<3> MODEM_STS_IT;
1.117 + typedef TSingleBitField<2> LINE_STS_IT;
1.118 + typedef TSingleBitField<1> THR_IT;
1.119 + typedef TSingleBitField<0> RHR_IT;
1.120 + };
1.121 +
1.122 +struct IER_IRDA
1.123 + {
1.124 + static const TInt KOffset = 0x04;
1.125 + static TDynReg8_RW< TUart, KOffset > iMem;
1.126 + typedef TSingleBitField<7> EOF_IT;
1.127 + typedef TSingleBitField<6> LINE_STS_IT;
1.128 + typedef TSingleBitField<5> TX_STATUS_IT;
1.129 + typedef TSingleBitField<4> STS_FIFO_TRIG_IT;
1.130 + typedef TSingleBitField<3> RX_OVERRUN_IT;
1.131 + typedef TSingleBitField<2> LAST_RX_BYTE_IT;
1.132 + typedef TSingleBitField<1> THR_IT;
1.133 + typedef TSingleBitField<0> RHR_IT;
1.134 + };
1.135 +
1.136 +struct DLH
1.137 + {
1.138 + static const TInt KOffset = 0x04;
1.139 + static TDynReg8_RW< TUart, KOffset > iMem;
1.140 + typedef TBitField<0,6> CLOCK_MSB;
1.141 + };
1.142 +
1.143 +struct FCR
1.144 + {
1.145 + static const TInt KOffset = 0x08;
1.146 + static TDynReg8_W< TUart, KOffset > iMem;
1.147 + typedef TSingleBitField<0> FIFO_EN;
1.148 + typedef TSingleBitField<1> RX_FIFO_CLEAR;
1.149 + typedef TSingleBitField<2> TX_FIFO_CLEAR;
1.150 + typedef TSingleBitField<3> DMA_MODE;
1.151 + struct TX_FIFO_TRIG : public TBitField<4,2>
1.152 + {
1.153 + enum TConstants
1.154 + {
1.155 + K8Char = 0 << KShift,
1.156 + K16Char = 1 << KShift,
1.157 + K32Char = 2 << KShift,
1.158 + K56Char = 3 << KShift
1.159 + };
1.160 + };
1.161 + struct RX_FIFO_TRIG : public TBitField<6,2>
1.162 + {
1.163 + static const TUint8 K8Char = 0 << KShift;
1.164 + static const TUint8 K16Char = 1 << KShift;
1.165 + static const TUint8 K56Char = 2 << KShift;
1.166 + static const TUint8 K60Char = 3 << KShift;
1.167 + };
1.168 + };
1.169 +
1.170 +struct IIR
1.171 + {
1.172 + static const TInt KOffset = 0x08;
1.173 + static TDynReg8_R< TUart, KOffset > iMem;
1.174 + typedef TBitField<6,2> FCR_MIRROR;
1.175 + struct IT_TYPE : public TBitField<1,5>
1.176 + {
1.177 + enum TConstants
1.178 + {
1.179 + EModem = 0 << KShift,
1.180 + ETHR = 1 << KShift,
1.181 + ERHR = 2 << KShift,
1.182 + ERxLineStatus = 3 << KShift,
1.183 + ERxTimeout = 6 << KShift,
1.184 + EXoff = 8 << KShift,
1.185 + ECtsRts = 16 << KShift
1.186 + };
1.187 + };
1.188 + typedef TSingleBitField<0> IT_PENDING;
1.189 + };
1.190 +
1.191 +struct EFR
1.192 + {
1.193 + static const TInt KOffset = 0x08;
1.194 + static TDynReg8_RW< TUart, KOffset > iMem;
1.195 + typedef TSingleBitField<7> AUTO_CTS_EN;
1.196 + typedef TSingleBitField<6> AUTO_RTS_EN;
1.197 + typedef TSingleBitField<5> SPEC_CHAR;
1.198 + typedef TSingleBitField<4> ENHANCED_EN;
1.199 + struct SW_FLOW_CONTROL : public TBitField<0,4>
1.200 + {
1.201 + enum TFlowControl
1.202 + {
1.203 + ENone = 0,
1.204 + EXonXoff1 = 8,
1.205 + EXonXoff2 = 4,
1.206 + EXonXoffBoth = 8 + 4,
1.207 + };
1.208 + };
1.209 + };
1.210 +
1.211 +struct LCR
1.212 + {
1.213 + static const TInt KOffset = 0x0c;
1.214 + static TDynReg8_RW< TUart, KOffset > iMem;
1.215 + typedef TSingleBitField<7> DIV_EN;
1.216 + typedef TSingleBitField<6> BREAK_EN;
1.217 + typedef TSingleBitField<5> PARITY_TYPE2;
1.218 + typedef TSingleBitField<4> PARITY_TYPE1;
1.219 + typedef TSingleBitField<3> PARITY_EN;
1.220 + struct NB_STOP : public TSingleBitField<2>
1.221 + {
1.222 + enum TConstants
1.223 + {
1.224 + E1Stop = 0 << KShift,
1.225 + E1_5Stop = 1 << KShift,
1.226 + E2Stop = 1 << KShift
1.227 + };
1.228 + };
1.229 + struct CHAR_LENGTH : public TBitField<0,2>
1.230 + {
1.231 + enum TConstants
1.232 + {
1.233 + E5Bits = 0,
1.234 + E6Bits = 1,
1.235 + E7Bits = 2,
1.236 + E8Bits = 3
1.237 + };
1.238 + };
1.239 +
1.240 + /** Special magic number to enter MODEA */
1.241 + static const TUint8 KConfigModeA = 0x80;
1.242 +
1.243 + /** Special magic number to enter MODEB */
1.244 + static const TUint8 KConfigModeB = 0xBF;
1.245 +
1.246 + /** Special magic number to enter operational mode */
1.247 + static const TUint8 KConfigModeOperational = 0x00;
1.248 + };
1.249 +
1.250 +struct MCR
1.251 + {
1.252 + static const TInt KOffset = 0x10;
1.253 + static TDynReg8_RW< TUart, KOffset > iMem;
1.254 + typedef TSingleBitField<6> TCR_TLR;
1.255 + typedef TSingleBitField<5> XON_EN;
1.256 + typedef TSingleBitField<4> LOOPBACK_EN;
1.257 + typedef TSingleBitField<3> CD_STS_CH;
1.258 + typedef TSingleBitField<2> RI_STS_CH;
1.259 + typedef TSingleBitField<1> RTS;
1.260 + typedef TSingleBitField<0> DTR;
1.261 + };
1.262 +
1.263 +struct XON1_ADDR1
1.264 + {
1.265 + static const TInt KOffset = 0x10;
1.266 + static TDynReg8_RW< TUart, KOffset > iMem;
1.267 + typedef TBitField<0,8> Value;
1.268 + };
1.269 +
1.270 +struct LSR
1.271 + {
1.272 + static const TInt KOffset = 0x14;
1.273 + static TDynReg8_R< TUart, KOffset > iMem;
1.274 + typedef TSingleBitField<7> RX_FIFO_STS;
1.275 + typedef TSingleBitField<6> TX_SR_E;
1.276 + typedef TSingleBitField<5> TX_FIFO_E;
1.277 + typedef TSingleBitField<4> RX_BI;
1.278 + typedef TSingleBitField<3> RX_FE;
1.279 + typedef TSingleBitField<2> RX_PE;
1.280 + typedef TSingleBitField<1> RX_OE;
1.281 + typedef TSingleBitField<0> RX_FIFO_E;
1.282 + };
1.283 +
1.284 +struct XON2_ADDR2
1.285 + {
1.286 + static const TInt KOffset = 0x14;
1.287 + static TDynReg8_RW< TUart, KOffset > iMem;
1.288 + typedef TBitField<0,8> Value;
1.289 + };
1.290 +
1.291 +struct XOFF1
1.292 + {
1.293 + static const TInt KOffset = 0x18;
1.294 + static TDynReg8_RW< TUart, KOffset > iMem;
1.295 + typedef TBitField<0,8> Value;
1.296 + };
1.297 +
1.298 +struct TCR
1.299 + {
1.300 + static const TInt KOffset = 0x18;
1.301 + static TDynReg8_RW< TUart, KOffset > iMem;
1.302 + typedef TBitField<4,4> RX_FIFO_TRIG_START;
1.303 + typedef TBitField<0,4> RX_FIFO_TRIG_HALT;
1.304 + };
1.305 +
1.306 +struct MSR
1.307 + {
1.308 + static const TInt KOffset = 0x18;
1.309 + static TDynReg8_R< TUart, KOffset > iMem;
1.310 + typedef TSingleBitField<7> NCD_STS;
1.311 + typedef TSingleBitField<6> NRI_STS;
1.312 + typedef TSingleBitField<5> NDSR_STS;
1.313 + typedef TSingleBitField<4> NCTS_STS;
1.314 + typedef TSingleBitField<3> DCD_STS;
1.315 + typedef TSingleBitField<2> RI_STS;
1.316 + typedef TSingleBitField<1> DSR_STS;
1.317 + typedef TSingleBitField<0> CTS_STS;
1.318 + };
1.319 +
1.320 +struct SPR
1.321 + {
1.322 + static const TInt KOffset = 0x1c;
1.323 + static TDynReg8_RW< TUart, KOffset > iMem;
1.324 + typedef TBitField<0,8> SPR_WORD;
1.325 + };
1.326 +
1.327 +struct XOFF2
1.328 + {
1.329 + static const TInt KOffset = 0x1c;
1.330 + static TDynReg8_RW< TUart, KOffset > iMem;
1.331 + typedef TBitField<0,8> Value;
1.332 + };
1.333 +
1.334 +struct TLR
1.335 + {
1.336 + static const TInt KOffset = 0x1c;
1.337 + static TDynReg8_RW< TUart, KOffset > iMem;
1.338 + typedef TBitField<4,4> RX_FIFO_TRIG_DMA;
1.339 + typedef TBitField<0,4> TX_FIFO_TRIG_DMA;
1.340 + };
1.341 +
1.342 +struct MDR1
1.343 + {
1.344 + static const TInt KOffset = 0x20;
1.345 + static TDynReg8_RW< TUart, KOffset > iMem;
1.346 + typedef TSingleBitField<7> FRAME_END_MODE;
1.347 + typedef TSingleBitField<6> SIP_MODE;
1.348 + typedef TSingleBitField<5> SCT;
1.349 + typedef TSingleBitField<4> SET_TXIR;
1.350 + typedef TSingleBitField<3> IR_SLEEP;
1.351 + struct MODE_SELECT : public TBitField<0,3>
1.352 + {
1.353 + enum TMode
1.354 + {
1.355 + EUart16x = 0,
1.356 + ESIR = 1,
1.357 + EUart16xAutoBaud = 2,
1.358 + EUart13x = 3,
1.359 + EMIR = 4,
1.360 + EFIR = 5,
1.361 + ECIR = 6,
1.362 + EDisable = 7
1.363 + };
1.364 + };
1.365 + };
1.366 +
1.367 +struct MDR2
1.368 + {
1.369 + static const TInt KOffset = 0x24;
1.370 + static TDynReg8_RW< TUart, KOffset > iMem;
1.371 + typedef TSingleBitField<6> IRRXINVERT;
1.372 + struct CIR_PULSE_MODE : public TBitField<4,2>
1.373 + {
1.374 + enum TConstants
1.375 + {
1.376 + EPw3 = 0 << KShift,
1.377 + EPw4 = 1 << KShift,
1.378 + EPw5 = 2 << KShift,
1.379 + EPw6 = 3 << KShift
1.380 + };
1.381 + };
1.382 + typedef TSingleBitField<3> UART_PULSE;
1.383 + struct STS_FIFO_TRIG : public TBitField<1,2>
1.384 + {
1.385 + enum TConstants
1.386 + {
1.387 + E1Entry = 0 << KShift,
1.388 + E4Entry = 1 << KShift,
1.389 + E7Entry = 2 << KShift,
1.390 + E8Entry = 3 << KShift
1.391 + };
1.392 + };
1.393 + typedef TSingleBitField<0> IRTX_UNDERRUN;
1.394 + };
1.395 +
1.396 +struct TXFLL
1.397 + {
1.398 + static const TInt KOffset = 0x28;
1.399 + static TDynReg8_W< TUart, KOffset > iMem;
1.400 + typedef TBitField<0,8> TX_FLL;
1.401 + };
1.402 +
1.403 +struct SFLSR
1.404 + {
1.405 + static const TInt KOffset = 0x28;
1.406 + static TDynReg8_R< TUart, KOffset > iMem;
1.407 + typedef TSingleBitField<4> OE_ERROR;
1.408 + typedef TSingleBitField<3> FTL_ERROR;
1.409 + typedef TSingleBitField<2> ABORT_DETECT;
1.410 + typedef TSingleBitField<1> CRC_ERROR;
1.411 + };
1.412 +
1.413 +struct RESUME
1.414 + {
1.415 + static const TInt KOffset = 0x2c;
1.416 + static TDynReg8_R< TUart, KOffset > iMem;
1.417 + typedef TBitField<0,8> Value;
1.418 + };
1.419 +
1.420 +struct TXFLH
1.421 + {
1.422 + static const TInt KOffset = 0x2c;
1.423 + static TDynReg8_W< TUart, KOffset > iMem;
1.424 + typedef TBitField<0,5> TX_FLH;
1.425 + };
1.426 +
1.427 +struct RXFLL
1.428 + {
1.429 + static const TInt KOffset = 0x30;
1.430 + static TDynReg8_W< TUart, KOffset > iMem;
1.431 + typedef TBitField<0,8> RX_FLL;
1.432 + };
1.433 +
1.434 +struct SFREGL
1.435 + {
1.436 + static const TInt KOffset = 0x30;
1.437 + static TDynReg8_R< TUart, KOffset > iMem;
1.438 + typedef TBitField<0,8> Value;
1.439 + };
1.440 +
1.441 +struct SFREGH
1.442 + {
1.443 + static const TInt KOffset = 0x34;
1.444 + static TDynReg8_R< TUart, KOffset > iMem;
1.445 + typedef TBitField<0,4> Value;
1.446 + };
1.447 +
1.448 +struct RXFLH
1.449 + {
1.450 + static const TInt KOffset = 0x34;
1.451 + static TDynReg8_W< TUart, KOffset > iMem;
1.452 + typedef TBitField<0,4> RX_FLH;
1.453 + };
1.454 +
1.455 +struct BLR
1.456 + {
1.457 + typedef TSingleBitField<7> STS_FIFO_RESET;
1.458 + typedef TSingleBitField<6> XBOF_TYPE;
1.459 + };
1.460 +
1.461 +struct UASR
1.462 + {
1.463 + static const TInt KOffset = 0x38;
1.464 + static TDynReg8_R< TUart, KOffset > iMem;
1.465 + struct PARITY_TYPE : public TBitField<6,2>
1.466 + {
1.467 + enum TConstants
1.468 + {
1.469 + ENone = 0 << KShift,
1.470 + ESpace = 1 << KShift,
1.471 + EEven = 2 << KShift,
1.472 + EOdd = 3 << KShift
1.473 + };
1.474 + };
1.475 + struct BIT_BY_CHAR : public TSingleBitField<5>
1.476 + {
1.477 + enum TConstants
1.478 + {
1.479 + E7Bit = 0 << KShift,
1.480 + E8Bit = 1 << KShift
1.481 + };
1.482 + };
1.483 + struct SPEED : public TBitField<0,5>
1.484 + {
1.485 + enum TBaud
1.486 + {
1.487 + EUnknown = 0,
1.488 + E115200 = 1,
1.489 + E57600 = 2,
1.490 + E38400 = 3,
1.491 + E28800 = 4,
1.492 + E19200 = 5,
1.493 + E14400 = 6,
1.494 + E9600 = 7,
1.495 + E4800 = 8,
1.496 + E4800_2 = 9,
1.497 + E1200 = 10
1.498 + };
1.499 + };
1.500 + };
1.501 +
1.502 +struct ACREG
1.503 + {
1.504 + static const TInt KOffset = 0x3c;
1.505 + static TDynReg8_RW< TUart, KOffset > iMem;
1.506 + typedef TSingleBitField<7> PULSE_TYPE;
1.507 + typedef TSingleBitField<6> SID_MOD;
1.508 + typedef TSingleBitField<5> DIS_IR_RX;
1.509 + typedef TSingleBitField<4> DIS_TX_UNDERRUN;
1.510 + typedef TSingleBitField<3> SEND_SIP;
1.511 + typedef TSingleBitField<2> SCTX_EN;
1.512 + typedef TSingleBitField<1> ABORT_EN;
1.513 + typedef TSingleBitField<0> EOT_EN;
1.514 + };
1.515 +
1.516 +struct SCR
1.517 + {
1.518 + static const TInt KOffset = 0x40;
1.519 + static TDynReg8_RW< TUart, KOffset > iMem;
1.520 + typedef TSingleBitField<7> RX_TRIG_GRANU1;
1.521 + typedef TSingleBitField<6> TX_TRIG_GRANU1;
1.522 + typedef TSingleBitField<4> RX_CTS_WU_EN;
1.523 + typedef TSingleBitField<3> TX_EMPTY_CTL_IT;
1.524 + typedef TBitField<1,2> DMA_MODE2;
1.525 + typedef TSingleBitField<0> DMA_MODE_CTL;
1.526 + };
1.527 +
1.528 +struct SSR
1.529 + {
1.530 + static const TInt KOffset = 0x44;
1.531 + static TDynReg8_R< TUart, KOffset > iMem;
1.532 + typedef TSingleBitField<1> RX_CTS_WU_STS;
1.533 + typedef TSingleBitField<0> TX_FIFO_FULL;
1.534 + };
1.535 +
1.536 +struct EBLR
1.537 + {
1.538 + static const TInt KOffset = 0x48;
1.539 + static TDynReg8_RW< TUart, KOffset > iMem;
1.540 + typedef TBitField<0,8> Value;
1.541 + };
1.542 +
1.543 +struct SYSC
1.544 + {
1.545 + static const TInt KOffset = 0x54;
1.546 + static TDynReg8_RW< TUart, KOffset > iMem;
1.547 + struct IDLE_MODE : public TBitField<3,2>
1.548 + {
1.549 + enum TMode
1.550 + {
1.551 + EForceIdle = 0 << KShift,
1.552 + ENoIdle = 1 << KShift,
1.553 + ESmartIdle = 2 << KShift
1.554 + };
1.555 + };
1.556 + typedef TSingleBitField<2> ENAWAKEUP;
1.557 + typedef TSingleBitField<1> SOFTRESET;
1.558 + typedef TSingleBitField<0> AUTOIDLE;
1.559 + };
1.560 +
1.561 +struct SYSS
1.562 + {
1.563 + static const TInt KOffset = 0x58;
1.564 + static TDynReg8_R< TUart, KOffset > iMem;
1.565 + typedef TSingleBitField<0> RESETDONE;
1.566 + };
1.567 +
1.568 +struct WER
1.569 + {
1.570 + static const TInt KOffset = 0x5c;
1.571 + static TDynReg8_RW< TUart, KOffset > iMem;
1.572 + typedef TSingleBitField<6> EVENT_6_RLS_INTERRUPT;
1.573 + typedef TSingleBitField<5> EVENT_5_RHR_INTERRUPT;
1.574 + typedef TSingleBitField<4> EVENT_4_RX_ACTIVITY;
1.575 + typedef TSingleBitField<2> EVENT_2_RI_ACTIVITY;
1.576 + typedef TSingleBitField<0> EVENT_0_CTS_ACTIVITY;
1.577 + };
1.578 +
1.579 +struct CFPS
1.580 + {
1.581 + static const TInt KOffset = 0x60;
1.582 + static TDynReg8_RW< TUart, KOffset > iMem;
1.583 + typedef TBitField<0,8> Value;
1.584 + };
1.585 +
1.586 +
1.587 +class TUart
1.588 + {
1.589 + public:
1.590 + enum TBaud
1.591 + {
1.592 + E1200,
1.593 + E2400,
1.594 + E4800,
1.595 + E9600,
1.596 + E14400,
1.597 + E19200,
1.598 + E28800,
1.599 + E38400,
1.600 + E57600,
1.601 + E115200,
1.602 + E230400,
1.603 + E460800,
1.604 + E921600,
1.605 + E1843000,
1.606 + E3688400,
1.607 + E4000000, // FIR
1.608 +
1.609 + KSupportedBaudCount
1.610 + };
1.611 +
1.612 + enum TParity
1.613 + {
1.614 + ENone,
1.615 + EOdd,
1.616 + EEven,
1.617 + EMark,
1.618 + ESpace
1.619 + };
1.620 +
1.621 + enum TDataBits
1.622 + {
1.623 + E5Data = ::Omap3530Uart::LCR::CHAR_LENGTH::E5Bits,
1.624 + E6Data = ::Omap3530Uart::LCR::CHAR_LENGTH::E6Bits,
1.625 + E7Data = ::Omap3530Uart::LCR::CHAR_LENGTH::E7Bits,
1.626 + E8Data = ::Omap3530Uart::LCR::CHAR_LENGTH::E8Bits,
1.627 + };
1.628 +
1.629 + enum TStopBits
1.630 + {
1.631 + E1Stop = ::Omap3530Uart::LCR::NB_STOP::E1Stop,
1.632 + E1_5Stop = ::Omap3530Uart::LCR::NB_STOP::E1_5Stop,
1.633 + E2Stop = ::Omap3530Uart::LCR::NB_STOP::E2Stop,
1.634 + };
1.635 +
1.636 + enum TUartMode
1.637 + {
1.638 + EUart,
1.639 + EUartAutoBaud,
1.640 + ESIR,
1.641 + EMIR,
1.642 + EFIR,
1.643 + ECIR,
1.644 +
1.645 + KSupportedUartModes
1.646 + };
1.647 +
1.648 + enum TFifoTrigger
1.649 + {
1.650 + ETrigger8,
1.651 + ETrigger16,
1.652 + ETrigger32,
1.653 + ETrigger56,
1.654 + ETrigger60,
1.655 + ETriggerUnchanged
1.656 + };
1.657 +
1.658 + enum TEnableState
1.659 + {
1.660 + EDisabled,
1.661 + EEnabled
1.662 + };
1.663 +
1.664 + enum TInterrupt
1.665 + {
1.666 + EIntRhr = 0,
1.667 + EIntThr = 1,
1.668 + EIntLineStatus = 2,
1.669 + EIntModemStatus = 3,
1.670 + EIntXoff = 5,
1.671 + EIntRts = 6,
1.672 + EIntCts = 7
1.673 + };
1.674 +
1.675 + public:
1.676 + inline TUart( const TUartNumber aUartNumber )
1.677 + : iBase( (aUartNumber == EUart0 ) ? TUartTraits<EUart0>::KBaseAddress
1.678 + : (aUartNumber == EUart1 ) ? TUartTraits<EUart1>::KBaseAddress
1.679 + : (aUartNumber == EUart2 ) ? TUartTraits<EUart2>::KBaseAddress
1.680 + : 0 ),
1.681 + iUartNumber( aUartNumber )
1.682 + {}
1.683 +
1.684 + FORCE_INLINE TLinAddr Base() const
1.685 + { return iBase; }
1.686 +
1.687 + IMPORT_C TInt InterruptId() const;
1.688 +
1.689 + IMPORT_C Prcm::TClock PrcmInterfaceClk() const;
1.690 +
1.691 + IMPORT_C Prcm::TClock PrcmFunctionClk() const;
1.692 +
1.693 +// IMPORT_C TInt PrmInterfaceClk() const;
1.694 +
1.695 +// IMPORT_C TInt PrmFunctionClk() const;
1.696 +
1.697 + /** Reset and initialize the UART
1.698 + * On return the UART will be in disable mode */
1.699 + IMPORT_C void Init();
1.700 +
1.701 + /** Defines which mode the UART will run in when enabled, but does not configure that mode
1.702 + * You must call this before calling SetBaud to ensure that correct baud rate multiplier is used */
1.703 + IMPORT_C void DefineMode( const TUartMode aMode );
1.704 +
1.705 + /** Enabled the UART in the defined mode
1.706 + * You must call DefineMode() and SetBaud() before calling Enable()
1.707 + */
1.708 + IMPORT_C void Enable();
1.709 +
1.710 + /** Disables the UART */
1.711 + IMPORT_C void Disable();
1.712 +
1.713 + /** Set the baud rate
1.714 + * Do not call this while the UART is enabled
1.715 + * You must have previously called DefineMode()
1.716 + */
1.717 + IMPORT_C void SetBaud( const TBaud aBaud );
1.718 +
1.719 + /** Set the data length, parity and stop bits */
1.720 + IMPORT_C void SetDataFormat( const TDataBits aDataBits, const TStopBits aStopBits, const TParity aParity );
1.721 +
1.722 + /** Setup the FIFO configuration */
1.723 + IMPORT_C void EnableFifo( const TEnableState aState, const TFifoTrigger aRxTrigger = ETriggerUnchanged, const TFifoTrigger aTxTrigger = ETriggerUnchanged );
1.724 +
1.725 + /** Enable a particular interrupt source */
1.726 + IMPORT_C void EnableInterrupt( const TInterrupt aWhich );
1.727 +
1.728 + /** Disable a particular interrupt source */
1.729 + IMPORT_C void DisableInterrupt( const TInterrupt aWhich );
1.730 +
1.731 + /** Disable all interrupts */
1.732 + IMPORT_C void DisableAllInterrupts();
1.733 +
1.734 + inline TBool TxFifoFull()
1.735 + { return SSR::iMem.Read(*this) bitand SSR::TX_FIFO_FULL::KMask; }
1.736 +
1.737 + inline TBool TxFifoEmpty()
1.738 + { return LSR::iMem.Read(*this) bitand LSR::TX_FIFO_E::KMask; }
1.739 +
1.740 + inline TBool RxFifoEmpty()
1.741 + { return !(LSR::iMem.Read(*this) bitand LSR::RX_FIFO_E::KMask); }
1.742 +
1.743 + inline void Write( TUint8 aByte )
1.744 + { THR::iMem.Write( *this, aByte ); }
1.745 +
1.746 + inline TUint8 Read()
1.747 + { return RHR::iMem.Read( *this ); }
1.748 +
1.749 + private:
1.750 + TUart();
1.751 +
1.752 + public:
1.753 + const TLinAddr iBase;
1.754 + const TUartNumber iUartNumber : 8;
1.755 + TUartMode iMode : 8;
1.756 + ::Omap3530Uart::MDR1::MODE_SELECT::TMode iTargetMode : 8;
1.757 + };
1.758 +
1.759 +
1.760 +} // Omap3530Uart
1.761 +
1.762 +#endif // ndef __OMAP3530_UART_H__
1.763 +