1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
2 // All rights reserved.
3 // This component and the accompanying materials are made available
4 // under the terms of the License "Eclipse Public License v1.0"
5 // which accompanies this distribution, and is available
6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".
8 // Initial Contributors:
9 // Nokia Corporation - initial contribution.
14 // \omap3530\omap3530_assp\prcm.h
16 // This file is part of the Beagle Base port
23 #include <assp/omap3530_assp/omap3530_irqmap.h>
29 ESetPllConfigBadPll, ///< bad PLL ID in SetPllConfiguration()
30 EGetPllConfigBadPll, ///< bad PLL ID in PllConfiguration()
31 ESetPllConfigBadFreqRange, ///< bad PLL frequency range in SetPllConfiguration()
32 ESetPllConfigBadRamp, ///< bad PLL ramp setting in SetPllConfiguration()
33 ESetPllConfigBadDrift, ///< bad PLL drift setting in SetPllConfiguration()
34 ESetPllConfigBadDivider, ///< bad divider setting in SetPllConfiguration()
35 ESetPllConfigBadMultiplier, ///< bad divider setting in SetPllConfiguration()
36 ESetPllLpBadPll, ///< bad PLL ID in SetPllLp()
37 EGetPllLpBadPll, ///< bad PLL ID in PllLp()
38 ESetPllLpBadMode, ///< bad PLL LP mode in SetPllLp()
39 ESetDividerBadClock, ///< bad clock ID in SetDivider()
40 EGetDividerBadClock, ///< bad clock ID in Divider()
41 ESetStateBadClock, ///< bad clock ID in SetClockState()
42 ESetWakeupBadClock, ///< bad clock ID in SetWakeupMode()
45 EGetStateBadClock, ///< bad clock ID in ClockState()
46 EGetWakeupBadClock, ///< bad clock ID in WakeupMode()
47 ESetGptClockBadGpt, ///< bad GPT ID in SetGptClockSource()
48 EGetWakeupGroupBadClock,
49 EGetWakeupGroupBadGroup,
50 EAddWakeupGroupBadClock,
51 EAddWakeupGroupBadGroup,
52 ERemoveWakeupGroupBadClock,
53 ERemoveWakeupGroupBadGroup,
54 EAddDomainBadClock, ///< bad clock in call to AddToWakeupDomain()
55 ERemoveDomainBadClock, ///< bad clock in call to RemoveFromWakeupDomain()
56 ECheckDomainBadClock, ///< bad clock in call to IsInWakeupDomain()
57 EAddDomainBadDomain, ///< bad domain in call to AddToWakeupDomain()
58 ERemoveDomainBadDomain, ///< bad domain in call to RemoveFromWakeupDomain()
59 ECheckDomainBadDomain, ///< bad domain in call to IsInWakeupDomain()
60 ESetDividerUnsupportedClock, ///< attempt to set divider on clock that does not have divider
61 ESetDividerBadDivider, ///< bad divider value in SetDivider()
62 EGetNameBadClock, ///< bad clock ID in PrmName()
63 EClockFrequencyBadClock, ///< bad clock ID in ClockFrequency()
64 ESetClockMuxBadClock, ///< bad clock ID in SetClockMux()
65 ESetClockMuxBadSource, ///< bad source clock ID in SetClockMux()
66 EGetClockMuxBadClock, ///< bad clock ID in ClockMux()
67 ESetDomainModeBadDomain, ///< bad domain in SetPowerDomainMode()
68 ESetDomainModeBadMode, ///< bad mode in SetPowerDomainMode()
69 EGetDomainModeBadDomain, ///< bad domain in PowerDomainMode()
70 ESetDomainModeUnsupportedMode, ///< mode requested in SetPowerDomainMode() not supported by that domain
71 EPllIsLockedBadPll, ///< bad PLL ID in PllIsLocked()
72 EWaitForPllLockBadPll, ///< bad PLL ID in WaitForPllLocked()
73 ESetPllBypassDividerBadPll, ///< bad PLL ID in SetPllBypassDivider()
74 EPllBypassDividerBadPll, ///< bad PLL ID in PllBypassDivider()
75 ESetPllBypassDividerBadDivider, ///< bad dividier value in SetPllBypassDivider()
76 EPllInternalFrequencyOutOfRange ///< PLL internal frequency out of range in AutoSetPllFrequencyRange()
82 EClkIva2Pll, ///< DPLL2
84 EClkPeriph, ///< DPLL4
85 EClkPeriph2, ///< DPLL5
89 EClkEmu, ///< Emulation clock
95 EClkMpuPll_Bypass, ///< DPLL1 bypass frequency
96 EClkIva2Pll_Bypass, ///< DPLL2 bypass frequency
97 EClkRM_F, ///< Reset manager functional clock
98 EClk96M, ///< 96MHz clock
99 EClk120M, ///< 120MHz clock
103 EClkTv_F, ///< TV functional clock, same as 54MHz FCLK
158 EClkUsb120_F, ///< USB host 120MHz functional clock
159 EClkUsb48_F, ///< USB host 48MHz functional clock
226 EClkUsb_I, ///< USB host interface clock
228 EClk48M, ///< 48MHz clock
229 EClk12M, ///< 12MHz clock
231 // These cannot be modified, they just represent the input clocks
232 // They must remain last in the table
233 EClkSysClk, ///< SYSCLK input clock
234 EClkAltClk, ///< SYSCLK32k input clock
235 EClkSysClk32k, ///< ALTCLK input clock
242 EIntWkUp = (EIrqRangeBasePrcm << KIrqRangeIndexShift),
269 KPrcmLastInterruptPlusOne
271 const TInt KInterruptCount = KPrcmLastInterruptPlusOne - EIrqRangeBasePrcm;
274 /** GPT reference enumeration */
293 /** Enumeration of supported PLLs */
313 EClkOff, ///< clock is disabled
314 EClkOn, ///< clock is enabled
315 EClkAuto ///< clock is in auto mode (enabled when required)
353 enum TPowerDomainMode
373 KSupportedPowerDomainCount
381 EWakeDomainPeripheral,
385 KSupportedWakeupDomainCount
393 KSupportedWakeupGroupCount
396 /** Indicates how to handle a request to set a clock frequency */
399 EExactOnly, ///< only set clock if requested frequency can be set exactly
400 ENearest, ///< always set clock to nearest possible frequency higher or lower than requested
401 ENearestLower, ///< set to nearest frequency <=requested, fail if no frequency <= requested is possible
402 ENearestHigher, ///< set to nearest frequency >=requested, fail if no frequency >= requested is possible
405 /** Enumeration of valid Pll frequency ranges */
406 enum TPllFrequencyRange
408 EPllRange_075_100 = 0x3, ///< 0.75 - 1.0 MHz
409 EPllRange_100_125 = 0x4, ///< <1.0 MHz - 1.25 MHz
410 EPllRange_125_150 = 0x5, ///< <1.25 MHz - 1.5 MHz
411 EPllRange_150_175 = 0x6, ///< <1.5 MHz - 1.75 MHz
412 EPllRange_175_210 = 0x7, ///< <1.75 MHz - 2.1 MHz
413 EPllRange_750_1000 = 0xB, ///< <7.5 MHz - 10 MHz
414 EPllRange_1000_1250 = 0xC, ///< <10 MHz - 12.5 MHz
415 EPllRange_1250_1500 = 0xD, ///< <12.5 MHz - 15 MHz
416 EPllRange_1500_1750 = 0xE, ///< <15 MHz - 17.5 MHz
417 EPllRange_1750_2100 = 0xF ///< <17.5 MHz - 21 MHz
420 /** Enumeration of valid PLL ramp settings */
423 EPllRampDisabled = 0x0,
429 /** Enumeration of vali PLL driftguard settings */
432 EPllDriftGuardDisabled,
433 EPllDriftGuardEnabled
436 /** Structure containing configuration for a PLL */
437 struct TPllConfiguration
439 TUint iMultiplier; ///< Multiple value
440 TUint iDivider; ///< Divider value (this is actual divider, hardware is programmed with iDivider-1)
441 TPllFrequencyRange iFreqRange : 8;
443 TPllDrift iDrift : 8;
447 /** Enumeration of supported SysClk frequency configurations */
448 enum TSysClkFrequency
458 // called during start-up
459 IMPORT_C void Init3(); // PRCM (disable every peripheral leaving DSS (and UART3 in debug) running)
461 IMPORT_C void SetPllConfig( TPll aPll, const TPllConfiguration& aConfig );
462 IMPORT_C void PllConfig( TPll aPll, TPllConfiguration& aConfigResult );
465 /** Configure PLL frequency */
466 IMPORT_C void SetPllMode( TPll aPll, TPllMode aPllMode );
468 /** Return PLL frequency configuration */
469 IMPORT_C TPllMode PllMode( TPll aPll );
471 /** Test whether a PLL is locked */
472 IMPORT_C TBool PllIsLocked( TPll aPll );
474 /** Wait for a PLL to lock */
475 IMPORT_C void WaitForPllLock( TPll aPll );
477 /** Calculate the correct FreqRange setting for the given pll
478 * Updates the iFreqRange parameter of the given TPllConfiguration
480 IMPORT_C void CalcPllFrequencyRange( TPll aPll, TPllConfiguration& aConfig );
482 /** Enable LP mode on a DLL if it is within LP frequency range */
483 IMPORT_C void AutoSetPllLpMode( TPll aPll );
485 /** Enable or disable PLL LP mode */
486 IMPORT_C void SetPllLp( TPll aPll, TLpMode aLpMode );
488 /** Get LP mode setting for a PLL */
489 IMPORT_C TLpMode PllLp( TPll aPll );
491 /** Set the bypass divider for a PLL */
492 IMPORT_C void SetPllBypassDivider( TPll aPll, TBypassDivider aDivider );
494 /** Get the current bypass divider for a PLL */
495 IMPORT_C TBypassDivider PllBypassDivider( TPll aPll );
497 /** Set the divider value for the given clock
498 * aDivider is the required divide value - e.g. to divide by 4
501 * Note that not all clocks support division by any number, and
502 * only some clocks have a divider. Attempting to set a divider
503 * on a clock without a divider will have no effect in UREL and
504 * will panic in UDEB with ESetDividerUnsupportedClock.
505 * Attempting to set a divider value not supported by the clock
506 * will have no effect in UREL and will panic in UDEB with
507 * ESetDividerBadDivider.
509 * Note 1: for EClkSgx_F the value valued of aDivide are 0, 3, 4, 6.
510 * 0 sets the clock to be the 96MHz clock
511 * 3, 4, 6 set it to be CORE_CLK divided by 3, 4, or 6
513 * Note 2: you cannot use this function to set EClkUsim_F, use
514 * SetUsimClockDivider().
516 IMPORT_C void SetDivider( TClock aClock, TUint aDivide );
518 /** Get the current divider value of the given clock */
519 IMPORT_C TUint Divider( TClock aClock );
521 //IMPORT_C void SetUsimClockDivider( TUint TUsimDivideMode aMode );
522 //IMPORT_C TUsimDivideMode UsimClockDivider();
524 /** Controls power to a power domain */
525 IMPORT_C void SetPowerDomainMode( TPowerDomain aDomain, TPowerDomainMode aMode );
527 /** Gets the current mode of a power domain power control */
528 IMPORT_C TPowerDomainMode PowerDomainMode( TPowerDomain aDomain );
530 //IMPORT_C void SetPowerSaveMode( TClock aClock, TPowerSaveMode aMode );
531 //IMPORT_C TPowerSaveMode PowerSaveMode( TClock aClock );
533 //IMPORT_C TBool DomainClockActive( TClock aClock );
535 // Set clock enable/disable
536 /** Set the clock state of a given clock */
537 IMPORT_C void SetClockState( TClock aClock, TClockState aState );
539 /** Get the configured clock state of a given clock */
540 IMPORT_C TClockState ClockState( TClock aClock );
542 // Configure wakeup mode for clocks
543 /** Configure wakeup mode for a clock
544 * Note - for peripheral blocks with an interface and functional clock, it is
545 * the interface clock which is configured for wakeup. Attempting to configure
546 * wakeup on the functional clock has no effect
548 IMPORT_C void SetWakeupMode( TClock aClock, TWakeupMode aMode );
550 /** Get configured wakeup mode for a clock */
551 IMPORT_C TWakeupMode WakeupMode( TClock aClock );
553 /** Add a peripheral interface clock to the specified wakeup group */
554 IMPORT_C void AddToWakeupGroup( TClock aClock, TWakeupGroup aGroup );
556 /** Remove a peripheral interface clock from the specified wakeup group */
557 IMPORT_C void RemoveFromWakeupGroup( TClock aClock, TWakeupGroup aGroup );
559 /** Test whether a peripheral interface clock is in the specified wakeup group */
560 IMPORT_C TBool IsInWakeupGroup( TClock aClock, TWakeupGroup aGroup );
562 /** Add a clock to the given wakeup domain */
563 IMPORT_C void AddToWakeupDomain( TClock aClock, TWakeupDomain aDomain );
565 /** Remove a clock from the given wakeup domain */
566 IMPORT_C void RemoveFromWakeupDomain( TClock aClock, TWakeupDomain aDomain );
568 /** Test whether a clock is in the specified wakeup domain */
569 IMPORT_C TBool IsInWakeupDomain( TClock aClock, TWakeupDomain aDomain );
572 // Functions for configuring clock sources
574 /** Set the clock source for a GPT timer */
575 IMPORT_C void SetGptClockSource( TGpt aGpt, TGptClockSource aSource );
577 /** Get the current clock source of a GPT */
578 IMPORT_C TGptClockSource GptClockSource( TGpt aGpt );
580 /** Get the USIM divider factor */
581 IMPORT_C TUint UsimDivider();
583 /** Get the USIM source clock */
584 IMPORT_C TClock UsimClockSource();
586 /** Sets the current input clock into the clock mux for the specified clock
587 * aClock must refer to a clock that has a mux for selecting input clock
588 * and aSource must be a possible input clock for aClock
590 IMPORT_C void SetClockMux( TClock aClock, TClock aSource );
593 /** Gets the current input clock into the clock mux for the specified clock
594 * aClock must refer to a clock that has a mux for selecting input clock
596 IMPORT_C TClock ClockMux( TClock aClock );
598 /** Get the currently configured frequency of the specified clock
599 * Note that this is regardless of whether the clock is currently running.
600 * That is, if a clock is configured to run at 8MHz, then this function
601 * will return 8000000 whether the clock is currently enabled or disabled.
603 * @param aClock clock required
604 * @return Frequency in Hz
606 IMPORT_C TUint ClockFrequency( TClock aClock );
608 /** Set the correct SysClock frequency */
609 IMPORT_C void SetSysClkFrequency( TSysClkFrequency aFrequency );
611 /** Get the currently configured SysClk frequency */
612 IMPORT_C TSysClkFrequency SysClkFrequency();
614 /** Function to get the name to be passed to the Power Resource Manager
615 * to refer to the given clock source
617 IMPORT_C const TDesC& PrmName( TClock aClock );
621 #endif // !defined PRCM_H__