1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/epoc32/include/assp/omap3530_assp/omap3530_prcm.h Wed Mar 31 12:33:34 2010 +0100
1.3 @@ -0,0 +1,621 @@
1.4 +// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// \omap3530\omap3530_assp\prcm.h
1.18 +// Access to PRCM.
1.19 +// This file is part of the Beagle Base port
1.20 +//
1.21 +
1.22 +#ifndef PRCM_H__
1.23 +#define PRCM_H__
1.24 +
1.25 +#include <e32cmn.h>
1.26 +#include <assp/omap3530_assp/omap3530_irqmap.h>
1.27 +
1.28 +namespace Prcm
1.29 +{
1.30 +enum TPanic
1.31 + {
1.32 + ESetPllConfigBadPll, ///< bad PLL ID in SetPllConfiguration()
1.33 + EGetPllConfigBadPll, ///< bad PLL ID in PllConfiguration()
1.34 + ESetPllConfigBadFreqRange, ///< bad PLL frequency range in SetPllConfiguration()
1.35 + ESetPllConfigBadRamp, ///< bad PLL ramp setting in SetPllConfiguration()
1.36 + ESetPllConfigBadDrift, ///< bad PLL drift setting in SetPllConfiguration()
1.37 + ESetPllConfigBadDivider, ///< bad divider setting in SetPllConfiguration()
1.38 + ESetPllConfigBadMultiplier, ///< bad divider setting in SetPllConfiguration()
1.39 + ESetPllLpBadPll, ///< bad PLL ID in SetPllLp()
1.40 + EGetPllLpBadPll, ///< bad PLL ID in PllLp()
1.41 + ESetPllLpBadMode, ///< bad PLL LP mode in SetPllLp()
1.42 + ESetDividerBadClock, ///< bad clock ID in SetDivider()
1.43 + EGetDividerBadClock, ///< bad clock ID in Divider()
1.44 + ESetStateBadClock, ///< bad clock ID in SetClockState()
1.45 + ESetWakeupBadClock, ///< bad clock ID in SetWakeupMode()
1.46 + ESetPllModeBadClock,
1.47 + ESetPllModeBadMode,
1.48 + EGetStateBadClock, ///< bad clock ID in ClockState()
1.49 + EGetWakeupBadClock, ///< bad clock ID in WakeupMode()
1.50 + ESetGptClockBadGpt, ///< bad GPT ID in SetGptClockSource()
1.51 + EGetWakeupGroupBadClock,
1.52 + EGetWakeupGroupBadGroup,
1.53 + EAddWakeupGroupBadClock,
1.54 + EAddWakeupGroupBadGroup,
1.55 + ERemoveWakeupGroupBadClock,
1.56 + ERemoveWakeupGroupBadGroup,
1.57 + EAddDomainBadClock, ///< bad clock in call to AddToWakeupDomain()
1.58 + ERemoveDomainBadClock, ///< bad clock in call to RemoveFromWakeupDomain()
1.59 + ECheckDomainBadClock, ///< bad clock in call to IsInWakeupDomain()
1.60 + EAddDomainBadDomain, ///< bad domain in call to AddToWakeupDomain()
1.61 + ERemoveDomainBadDomain, ///< bad domain in call to RemoveFromWakeupDomain()
1.62 + ECheckDomainBadDomain, ///< bad domain in call to IsInWakeupDomain()
1.63 + ESetDividerUnsupportedClock, ///< attempt to set divider on clock that does not have divider
1.64 + ESetDividerBadDivider, ///< bad divider value in SetDivider()
1.65 + EGetNameBadClock, ///< bad clock ID in PrmName()
1.66 + EClockFrequencyBadClock, ///< bad clock ID in ClockFrequency()
1.67 + ESetClockMuxBadClock, ///< bad clock ID in SetClockMux()
1.68 + ESetClockMuxBadSource, ///< bad source clock ID in SetClockMux()
1.69 + EGetClockMuxBadClock, ///< bad clock ID in ClockMux()
1.70 + ESetDomainModeBadDomain, ///< bad domain in SetPowerDomainMode()
1.71 + ESetDomainModeBadMode, ///< bad mode in SetPowerDomainMode()
1.72 + EGetDomainModeBadDomain, ///< bad domain in PowerDomainMode()
1.73 + ESetDomainModeUnsupportedMode, ///< mode requested in SetPowerDomainMode() not supported by that domain
1.74 + EPllIsLockedBadPll, ///< bad PLL ID in PllIsLocked()
1.75 + EWaitForPllLockBadPll, ///< bad PLL ID in WaitForPllLocked()
1.76 + ESetPllBypassDividerBadPll, ///< bad PLL ID in SetPllBypassDivider()
1.77 + EPllBypassDividerBadPll, ///< bad PLL ID in PllBypassDivider()
1.78 + ESetPllBypassDividerBadDivider, ///< bad dividier value in SetPllBypassDivider()
1.79 + EPllInternalFrequencyOutOfRange ///< PLL internal frequency out of range in AutoSetPllFrequencyRange()
1.80 + };
1.81 +
1.82 +enum TClock
1.83 + {
1.84 + EClkMpu, ///< DPLL1
1.85 + EClkIva2Pll, ///< DPLL2
1.86 + EClkCore, ///< DPLL3
1.87 + EClkPeriph, ///< DPLL4
1.88 + EClkPeriph2, ///< DPLL5
1.89 +
1.90 + EClkPrcmInterface,
1.91 +
1.92 + EClkEmu, ///< Emulation clock
1.93 + EClkNeon,
1.94 +
1.95 + EClkL3Domain,
1.96 + EClkL4Domain,
1.97 +
1.98 + EClkMpuPll_Bypass, ///< DPLL1 bypass frequency
1.99 + EClkIva2Pll_Bypass, ///< DPLL2 bypass frequency
1.100 + EClkRM_F, ///< Reset manager functional clock
1.101 + EClk96M, ///< 96MHz clock
1.102 + EClk120M, ///< 120MHz clock
1.103 + EClkSysOut,
1.104 +
1.105 + // Functional clocks
1.106 + EClkTv_F, ///< TV functional clock, same as 54MHz FCLK
1.107 + EClkDss1_F,
1.108 + EClkDss2_F,
1.109 + EClkCsi2_F,
1.110 + EClkCam_F,
1.111 + EClkIva2_F,
1.112 + EClkMmc1_F,
1.113 + EClkMmc2_F,
1.114 + EClkMmc3_F,
1.115 + EClkMsPro_F,
1.116 + EClkHdq_F,
1.117 + EClkMcBsp1_F,
1.118 + EClkMcBsp2_F,
1.119 + EClkMcBsp3_F,
1.120 + EClkMcBsp4_F,
1.121 + EClkMcBsp5_F,
1.122 + EClkMcSpi1_F,
1.123 + EClkMcSpi2_F,
1.124 + EClkMcSpi3_F,
1.125 + EClkMcSpi4_F,
1.126 + EClkI2c1_F,
1.127 + EClkI2c2_F,
1.128 + EClkI2c3_F,
1.129 + EClkUart1_F,
1.130 + EClkUart2_F,
1.131 + EClkUart3_F,
1.132 + EClkGpt1_F,
1.133 + EClkGpt2_F,
1.134 + EClkGpt3_F,
1.135 + EClkGpt4_F,
1.136 + EClkGpt5_F,
1.137 + EClkGpt6_F,
1.138 + EClkGpt7_F,
1.139 + EClkGpt8_F,
1.140 + EClkGpt9_F,
1.141 + EClkGpt10_F,
1.142 + EClkGpt11_F,
1.143 + EClkUsbTll_F,
1.144 + EClkTs_F,
1.145 + EClkCpeFuse_F,
1.146 +
1.147 + EClkSgx_F,
1.148 +
1.149 + EClkUsim_F,
1.150 + EClkSmartReflex2_F,
1.151 + EClkSmartReflex1_F,
1.152 + EClkWdt2_F,
1.153 + EClkWdt3_F,
1.154 + EClkGpio1_F,
1.155 + EClkGpio2_F,
1.156 + EClkGpio3_F,
1.157 + EClkGpio4_F,
1.158 + EClkGpio5_F,
1.159 + EClkGpio6_F,
1.160 +
1.161 + EClkUsb120_F, ///< USB host 120MHz functional clock
1.162 + EClkUsb48_F, ///< USB host 48MHz functional clock
1.163 +
1.164 +
1.165 + // Interface clocks
1.166 + EClkDss_I,
1.167 + EClkCam_I,
1.168 + EClkIcr_I,
1.169 + EClkMmc1_I,
1.170 + EClkMmc2_I,
1.171 + EClkMmc3_I,
1.172 + EClkMsPro_I,
1.173 + EClkHdq_I,
1.174 + EClkAes1_I,
1.175 + EClkAes2_I,
1.176 + EClkSha11_I,
1.177 + EClkSha12_I,
1.178 + EClkDes1_I,
1.179 + EClkDes2_I,
1.180 + EClkMcBsp1_I,
1.181 + EClkMcBsp2_I,
1.182 + EClkMcBsp3_I,
1.183 + EClkMcBsp4_I,
1.184 + EClkMcBsp5_I,
1.185 + EClkI2c1_I,
1.186 + EClkI2c2_I,
1.187 + EClkI2c3_I,
1.188 + EClkUart1_I,
1.189 + EClkUart2_I,
1.190 + EClkUart3_I,
1.191 + EClkMcSpi1_I,
1.192 + EClkMcSpi2_I,
1.193 + EClkMcSpi3_I,
1.194 + EClkMcSpi4_I,
1.195 + EClkGpt1_I,
1.196 + EClkGpt2_I,
1.197 + EClkGpt3_I,
1.198 + EClkGpt4_I,
1.199 + EClkGpt5_I,
1.200 + EClkGpt6_I,
1.201 + EClkGpt7_I,
1.202 + EClkGpt8_I,
1.203 + EClkGpt9_I,
1.204 + EClkGpt10_I,
1.205 + EClkGpt11_I,
1.206 + EClkGpt12_I,
1.207 + EClkMailboxes_I,
1.208 + EClkOmapSCM_I,
1.209 + EClkHsUsbOtg_I,
1.210 + EClkSdrc_I,
1.211 + EClkPka_I,
1.212 + EClkRng_I,
1.213 + EClkUsbTll_I,
1.214 +
1.215 + EClkSgx_I,
1.216 +
1.217 + EClkUsim_I,
1.218 + EClkWdt1_I,
1.219 + EClkWdt2_I,
1.220 + EClkWdt3_I,
1.221 + EClkGpio1_I,
1.222 + EClkGpio2_I,
1.223 + EClkGpio3_I,
1.224 + EClkGpio4_I,
1.225 + EClkGpio5_I,
1.226 + EClkGpio6_I,
1.227 + EClk32Sync_I,
1.228 +
1.229 + EClkUsb_I, ///< USB host interface clock
1.230 +
1.231 + EClk48M, ///< 48MHz clock
1.232 + EClk12M, ///< 12MHz clock
1.233 +
1.234 + // These cannot be modified, they just represent the input clocks
1.235 + // They must remain last in the table
1.236 + EClkSysClk, ///< SYSCLK input clock
1.237 + EClkAltClk, ///< SYSCLK32k input clock
1.238 + EClkSysClk32k, ///< ALTCLK input clock
1.239 +
1.240 + KSupportedClockCount
1.241 + };
1.242 +
1.243 +enum TInterruptIds
1.244 + {
1.245 + EIntWkUp = (EIrqRangeBasePrcm << KIrqRangeIndexShift),
1.246 + EIntUnused1,
1.247 + EIntEvGenOn,
1.248 + EIntEvGenOff,
1.249 + EIntTransition,
1.250 + EIntCoreDpll,
1.251 + EIntPeriphDpll,
1.252 + EIntMpuDpll,
1.253 + EIntIvaDpll,
1.254 + EIntIo,
1.255 + EIntVp1OpChangeDone,
1.256 + EIntVp1MinVdd,
1.257 + EIntVp1MaxVdd,
1.258 + EIntVp1NoSmpsAck,
1.259 + EIntVp1EqValue,
1.260 + EIntVp1TranDone,
1.261 + EIntVp2OpChangeDone,
1.262 + EIntVp2MinVdd,
1.263 + EIntVp2MaxVdd,
1.264 + EIntVp2NoSmpsAck,
1.265 + EIntVp2EqValue,
1.266 + EIntVp2TranDone,
1.267 + EIntVcSaErr,
1.268 + EIntVcRaErr,
1.269 + EIntVcTimeoutErr,
1.270 + EIntSndPeriphDpll,
1.271 +
1.272 + KPrcmLastInterruptPlusOne
1.273 + };
1.274 +const TInt KInterruptCount = KPrcmLastInterruptPlusOne - EIrqRangeBasePrcm;
1.275 +
1.276 +
1.277 +/** GPT reference enumeration */
1.278 +enum TGpt
1.279 + {
1.280 + EGpt1,
1.281 + EGpt2,
1.282 + EGpt3,
1.283 + EGpt4,
1.284 + EGpt5,
1.285 + EGpt6,
1.286 + EGpt7,
1.287 + EGpt8,
1.288 + EGpt9,
1.289 + EGpt10,
1.290 + EGpt11,
1.291 + EGpt12,
1.292 +
1.293 + KSupportedGptCount
1.294 + };
1.295 +
1.296 +/** Enumeration of supported PLLs */
1.297 +enum TPll
1.298 + {
1.299 + EDpll1,
1.300 + EDpll2,
1.301 + EDpll3,
1.302 + EDpll4,
1.303 + EDpll5,
1.304 +
1.305 + KSupportedPllCount
1.306 + };
1.307 +
1.308 +enum TGptClockSource
1.309 + {
1.310 + EGptClockSysClk,
1.311 + EGptClock32k
1.312 + };
1.313 +
1.314 +enum TClockState
1.315 + {
1.316 + EClkOff, ///< clock is disabled
1.317 + EClkOn, ///< clock is enabled
1.318 + EClkAuto ///< clock is in auto mode (enabled when required)
1.319 + };
1.320 +
1.321 +enum TWakeupMode
1.322 + {
1.323 + EWakeupDisabled,
1.324 + EWakeupEnabled,
1.325 + };
1.326 +
1.327 +enum TLpMode
1.328 + {
1.329 + ENormalMode,
1.330 + ELpMode
1.331 + };
1.332 +
1.333 +enum TPowerSaveMode
1.334 + {
1.335 + EPowerSaveOff,
1.336 + EPowerSaveIdle,
1.337 + EPowerSaveStandby
1.338 + };
1.339 +
1.340 +enum TPllMode
1.341 + {
1.342 + EPllStop,
1.343 + EPllBypass,
1.344 + EPllRun,
1.345 + EPllFastRelock,
1.346 + EPllAuto
1.347 + };
1.348 +
1.349 +enum TBypassDivider
1.350 + {
1.351 + EBypassDiv1,
1.352 + EBypassDiv2,
1.353 + EBypassDiv4
1.354 + };
1.355 +
1.356 +enum TPowerDomainMode
1.357 + {
1.358 + EPowerOff,
1.359 + EPowerRetention,
1.360 + EPowerReserved,
1.361 + EPowerOn,
1.362 + };
1.363 +
1.364 +enum TPowerDomain
1.365 + {
1.366 + EPowerDomainMpu,
1.367 + EPowerDomainIva2,
1.368 + EPowerDomainNeon,
1.369 + EPowerDomainCore,
1.370 + EPowerDomainSgx,
1.371 + EPowerDomainDss,
1.372 + EPowerDomainCamera,
1.373 + EPowerDomainUsb,
1.374 + EPowerDomainPer,
1.375 +
1.376 + KSupportedPowerDomainCount
1.377 + };
1.378 +
1.379 +enum TWakeupDomain
1.380 + {
1.381 + EWakeDomainMpu,
1.382 + EWakeDomainCore,
1.383 + EWakeDomainIva2,
1.384 + EWakeDomainPeripheral,
1.385 + EWakeDomainDss,
1.386 + EWakeDomainWakeup,
1.387 +
1.388 + KSupportedWakeupDomainCount
1.389 + };
1.390 +
1.391 +enum TWakeupGroup
1.392 + {
1.393 + EWakeGroupMpu,
1.394 + EWakeGroupIva2,
1.395 +
1.396 + KSupportedWakeupGroupCount
1.397 + };
1.398 +
1.399 +/** Indicates how to handle a request to set a clock frequency */
1.400 +enum TClockRoundMode
1.401 + {
1.402 + EExactOnly, ///< only set clock if requested frequency can be set exactly
1.403 + ENearest, ///< always set clock to nearest possible frequency higher or lower than requested
1.404 + ENearestLower, ///< set to nearest frequency <=requested, fail if no frequency <= requested is possible
1.405 + ENearestHigher, ///< set to nearest frequency >=requested, fail if no frequency >= requested is possible
1.406 + };
1.407 +
1.408 +/** Enumeration of valid Pll frequency ranges */
1.409 +enum TPllFrequencyRange
1.410 + {
1.411 + EPllRange_075_100 = 0x3, ///< 0.75 - 1.0 MHz
1.412 + EPllRange_100_125 = 0x4, ///< <1.0 MHz - 1.25 MHz
1.413 + EPllRange_125_150 = 0x5, ///< <1.25 MHz - 1.5 MHz
1.414 + EPllRange_150_175 = 0x6, ///< <1.5 MHz - 1.75 MHz
1.415 + EPllRange_175_210 = 0x7, ///< <1.75 MHz - 2.1 MHz
1.416 + EPllRange_750_1000 = 0xB, ///< <7.5 MHz - 10 MHz
1.417 + EPllRange_1000_1250 = 0xC, ///< <10 MHz - 12.5 MHz
1.418 + EPllRange_1250_1500 = 0xD, ///< <12.5 MHz - 15 MHz
1.419 + EPllRange_1500_1750 = 0xE, ///< <15 MHz - 17.5 MHz
1.420 + EPllRange_1750_2100 = 0xF ///< <17.5 MHz - 21 MHz
1.421 + };
1.422 +
1.423 +/** Enumeration of valid PLL ramp settings */
1.424 +enum TPllRamp
1.425 + {
1.426 + EPllRampDisabled = 0x0,
1.427 + EPllRamp4us = 0x1,
1.428 + EPllRam20us = 0x2,
1.429 + EPllRamp40us = 0x3
1.430 + };
1.431 +
1.432 +/** Enumeration of vali PLL driftguard settings */
1.433 +enum TPllDrift
1.434 + {
1.435 + EPllDriftGuardDisabled,
1.436 + EPllDriftGuardEnabled
1.437 + };
1.438 +
1.439 +/** Structure containing configuration for a PLL */
1.440 +struct TPllConfiguration
1.441 + {
1.442 + TUint iMultiplier; ///< Multiple value
1.443 + TUint iDivider; ///< Divider value (this is actual divider, hardware is programmed with iDivider-1)
1.444 + TPllFrequencyRange iFreqRange : 8;
1.445 + TPllRamp iRamp : 8;
1.446 + TPllDrift iDrift : 8;
1.447 + TUint8 __spare;
1.448 + };
1.449 +
1.450 +/** Enumeration of supported SysClk frequency configurations */
1.451 +enum TSysClkFrequency
1.452 + {
1.453 + ESysClk12MHz,
1.454 + ESysClk13MHz,
1.455 + ESysClk16_8MHz,
1.456 + ESysClk19_2MHz,
1.457 + ESysClk26MHz,
1.458 + ESysClk38_4MHz
1.459 + };
1.460 +
1.461 +// called during start-up
1.462 +IMPORT_C void Init3(); // PRCM (disable every peripheral leaving DSS (and UART3 in debug) running)
1.463 +
1.464 +IMPORT_C void SetPllConfig( TPll aPll, const TPllConfiguration& aConfig );
1.465 +IMPORT_C void PllConfig( TPll aPll, TPllConfiguration& aConfigResult );
1.466 +
1.467 +
1.468 +/** Configure PLL frequency */
1.469 +IMPORT_C void SetPllMode( TPll aPll, TPllMode aPllMode );
1.470 +
1.471 +/** Return PLL frequency configuration */
1.472 +IMPORT_C TPllMode PllMode( TPll aPll );
1.473 +
1.474 +/** Test whether a PLL is locked */
1.475 +IMPORT_C TBool PllIsLocked( TPll aPll );
1.476 +
1.477 +/** Wait for a PLL to lock */
1.478 +IMPORT_C void WaitForPllLock( TPll aPll );
1.479 +
1.480 +/** Calculate the correct FreqRange setting for the given pll
1.481 + * Updates the iFreqRange parameter of the given TPllConfiguration
1.482 + */
1.483 +IMPORT_C void CalcPllFrequencyRange( TPll aPll, TPllConfiguration& aConfig );
1.484 +
1.485 +/** Enable LP mode on a DLL if it is within LP frequency range */
1.486 +IMPORT_C void AutoSetPllLpMode( TPll aPll );
1.487 +
1.488 +/** Enable or disable PLL LP mode */
1.489 +IMPORT_C void SetPllLp( TPll aPll, TLpMode aLpMode );
1.490 +
1.491 +/** Get LP mode setting for a PLL */
1.492 +IMPORT_C TLpMode PllLp( TPll aPll );
1.493 +
1.494 +/** Set the bypass divider for a PLL */
1.495 +IMPORT_C void SetPllBypassDivider( TPll aPll, TBypassDivider aDivider );
1.496 +
1.497 +/** Get the current bypass divider for a PLL */
1.498 +IMPORT_C TBypassDivider PllBypassDivider( TPll aPll );
1.499 +
1.500 +/** Set the divider value for the given clock
1.501 + * aDivider is the required divide value - e.g. to divide by 4
1.502 + * aDivider=4.
1.503 + *
1.504 + * Note that not all clocks support division by any number, and
1.505 + * only some clocks have a divider. Attempting to set a divider
1.506 + * on a clock without a divider will have no effect in UREL and
1.507 + * will panic in UDEB with ESetDividerUnsupportedClock.
1.508 + * Attempting to set a divider value not supported by the clock
1.509 + * will have no effect in UREL and will panic in UDEB with
1.510 + * ESetDividerBadDivider.
1.511 + *
1.512 + * Note 1: for EClkSgx_F the value valued of aDivide are 0, 3, 4, 6.
1.513 + * 0 sets the clock to be the 96MHz clock
1.514 + * 3, 4, 6 set it to be CORE_CLK divided by 3, 4, or 6
1.515 + *
1.516 + * Note 2: you cannot use this function to set EClkUsim_F, use
1.517 + * SetUsimClockDivider().
1.518 + */
1.519 +IMPORT_C void SetDivider( TClock aClock, TUint aDivide );
1.520 +
1.521 +/** Get the current divider value of the given clock */
1.522 +IMPORT_C TUint Divider( TClock aClock );
1.523 +
1.524 +//IMPORT_C void SetUsimClockDivider( TUint TUsimDivideMode aMode );
1.525 +//IMPORT_C TUsimDivideMode UsimClockDivider();
1.526 +
1.527 +/** Controls power to a power domain */
1.528 +IMPORT_C void SetPowerDomainMode( TPowerDomain aDomain, TPowerDomainMode aMode );
1.529 +
1.530 +/** Gets the current mode of a power domain power control */
1.531 +IMPORT_C TPowerDomainMode PowerDomainMode( TPowerDomain aDomain );
1.532 +
1.533 +//IMPORT_C void SetPowerSaveMode( TClock aClock, TPowerSaveMode aMode );
1.534 +//IMPORT_C TPowerSaveMode PowerSaveMode( TClock aClock );
1.535 +
1.536 +//IMPORT_C TBool DomainClockActive( TClock aClock );
1.537 +
1.538 +// Set clock enable/disable
1.539 +/** Set the clock state of a given clock */
1.540 +IMPORT_C void SetClockState( TClock aClock, TClockState aState );
1.541 +
1.542 +/** Get the configured clock state of a given clock */
1.543 +IMPORT_C TClockState ClockState( TClock aClock );
1.544 +
1.545 +// Configure wakeup mode for clocks
1.546 +/** Configure wakeup mode for a clock
1.547 + * Note - for peripheral blocks with an interface and functional clock, it is
1.548 + * the interface clock which is configured for wakeup. Attempting to configure
1.549 + * wakeup on the functional clock has no effect
1.550 + */
1.551 +IMPORT_C void SetWakeupMode( TClock aClock, TWakeupMode aMode );
1.552 +
1.553 +/** Get configured wakeup mode for a clock */
1.554 +IMPORT_C TWakeupMode WakeupMode( TClock aClock );
1.555 +
1.556 +/** Add a peripheral interface clock to the specified wakeup group */
1.557 +IMPORT_C void AddToWakeupGroup( TClock aClock, TWakeupGroup aGroup );
1.558 +
1.559 +/** Remove a peripheral interface clock from the specified wakeup group */
1.560 +IMPORT_C void RemoveFromWakeupGroup( TClock aClock, TWakeupGroup aGroup );
1.561 +
1.562 +/** Test whether a peripheral interface clock is in the specified wakeup group */
1.563 +IMPORT_C TBool IsInWakeupGroup( TClock aClock, TWakeupGroup aGroup );
1.564 +
1.565 +/** Add a clock to the given wakeup domain */
1.566 +IMPORT_C void AddToWakeupDomain( TClock aClock, TWakeupDomain aDomain );
1.567 +
1.568 +/** Remove a clock from the given wakeup domain */
1.569 +IMPORT_C void RemoveFromWakeupDomain( TClock aClock, TWakeupDomain aDomain );
1.570 +
1.571 +/** Test whether a clock is in the specified wakeup domain */
1.572 +IMPORT_C TBool IsInWakeupDomain( TClock aClock, TWakeupDomain aDomain );
1.573 +
1.574 +
1.575 +// Functions for configuring clock sources
1.576 +
1.577 +/** Set the clock source for a GPT timer */
1.578 +IMPORT_C void SetGptClockSource( TGpt aGpt, TGptClockSource aSource );
1.579 +
1.580 +/** Get the current clock source of a GPT */
1.581 +IMPORT_C TGptClockSource GptClockSource( TGpt aGpt );
1.582 +
1.583 +/** Get the USIM divider factor */
1.584 +IMPORT_C TUint UsimDivider();
1.585 +
1.586 +/** Get the USIM source clock */
1.587 +IMPORT_C TClock UsimClockSource();
1.588 +
1.589 +/** Sets the current input clock into the clock mux for the specified clock
1.590 + * aClock must refer to a clock that has a mux for selecting input clock
1.591 + * and aSource must be a possible input clock for aClock
1.592 + */
1.593 +IMPORT_C void SetClockMux( TClock aClock, TClock aSource );
1.594 +
1.595 +
1.596 +/** Gets the current input clock into the clock mux for the specified clock
1.597 + * aClock must refer to a clock that has a mux for selecting input clock
1.598 + */
1.599 +IMPORT_C TClock ClockMux( TClock aClock );
1.600 +
1.601 +/** Get the currently configured frequency of the specified clock
1.602 + * Note that this is regardless of whether the clock is currently running.
1.603 + * That is, if a clock is configured to run at 8MHz, then this function
1.604 + * will return 8000000 whether the clock is currently enabled or disabled.
1.605 + *
1.606 + * @param aClock clock required
1.607 + * @return Frequency in Hz
1.608 + */
1.609 +IMPORT_C TUint ClockFrequency( TClock aClock );
1.610 +
1.611 +/** Set the correct SysClock frequency */
1.612 +IMPORT_C void SetSysClkFrequency( TSysClkFrequency aFrequency );
1.613 +
1.614 +/** Get the currently configured SysClk frequency */
1.615 +IMPORT_C TSysClkFrequency SysClkFrequency();
1.616 +
1.617 +/** Function to get the name to be passed to the Power Resource Manager
1.618 + * to refer to the given clock source
1.619 + */
1.620 +IMPORT_C const TDesC& PrmName( TClock aClock );
1.621 +
1.622 +}
1.623 +
1.624 +#endif // !defined PRCM_H__