1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
2 // All rights reserved.
3 // This component and the accompanying materials are made available
4 // under the terms of the License "Eclipse Public License v1.0"
5 // which accompanies this distribution, and is available
6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".
8 // Initial Contributors:
9 // Nokia Corporation - initial contribution.
14 // omap3530/assp/inc/omap3530_irqmap.h
17 #ifndef OMAP3530_IRQMAP_H
18 #define OMAP3530_IRQMAP_H
20 #include <assp/omap3530_assp/omap3530_hardware_base.h>
23 #define INTCPS_BASE Omap3530HwBase::KL4_Core + 0x200000
24 #define INTCPS_SYSCONFIG INTCPS_BASE + 0x10
25 #define INTCPS_SYSSTATUS INTCPS_BASE + 0x14
26 #define INTCPS_PROTECTION INTCPS_BASE + 0x4c
27 #define INTCPS_IRQ_PRIORITY INTCPS_BASE + 0x60
28 #define INTCPS_FIQ_PRIORITY INTCPS_BASE + 0x64
31 #define INTCPS_ITR(n) (INTCPS_BASE + 0x80 +( 0x20 *n))
32 #define INTCPS_THRESHOLD INTCPS_BASE + 0x64
33 #define INTCPS_IDLE INTCPS_BASE + 0x50
34 //#define INTC_INIT_REGISTER1 0x470C8010
35 //#define INTC_INIT_REGISTER2 0x470C8050
36 #define INTCPS_ILRM(n) (INTCPS_BASE + 0x100 +(0x04 *n))
38 //current interrupt vector & clear regs
39 #define INTCPS_SIR_IRQ INTCPS_BASE + 0x40
40 #define INTCPS_SIR_FIQ INTCPS_BASE + 0x44
41 #define INTCPS_CONTROL INTCPS_BASE + 0x48
44 #define INTCPS_PENDING_IRQ(n) (INTCPS_BASE + 0x98 + (0x20 * n))
45 #define INTCPS_PENDING_FIQ(n) (INTCPS_BASE + 0x9c + (0x20 * n))
47 #define INTCPS_MIRn(n) (INTCPS_BASE + 0x084 + (n *0x20))
48 #define INTCPS_MIR_SETn(n) (INTCPS_BASE + 0x08c + (n * 0x20))
49 #define INTCPS_MIR_CLEARn(n) (INTCPS_BASE + 0x088 + (n *0x20))
52 #define INTCPS_ISRSET(n) (INTCPS_BASE + 0x090 + (n *0x20))
53 #define INTCPS_ISR_CLEAR(n) (INTCPS_BASE + 0x094 + (n *0x20))
56 #define INTCPS_SYSCONFIG_AUTOIDLE 0x1
57 #define INTCPS_IDLE_FUNCIDLE 0x0
58 #define INTCPS_IDLE_TURBO 0x1
59 #define INTCPS_ILRM_DEF_PRI (0x1 <<2)
60 #define INTCPS_ILRM_ROUTE_FIQ 0x1
61 #define INTCPS_ILRM_ROUTE_IRQ 0x00
62 #define INTCPS_MIR_ALL_UNSET 0x00000000
63 #define INTCPS_MIR_ALL_SET 0xffffffff
65 #define INTCPS_CONTROL_IRQ_CLEAR 0x1
66 #define INTCPS_CONTROL_FIQ_CLEAR (0x1 << 1)
67 #define INTCPS_INIT_RG_LOW_PWR 0x1
68 #define INTCPS_PENDING_MASK 0x7f
72 // Base of each interrupt range supported within the ASSP layer
73 // Used to index the correct interrupt handler object
76 EIrqRangeBaseCore, // main interrupt controller
77 EIrqRangeBasePrcm, // PRCM sub-controller interrupt sources
78 EIrqRangeBaseGpio, // GPIO sub-controller interrupt sources
79 EIrqRangeBasePsu, // Place-holder for off-board PSU device, reserved here because
80 // we know there will always be one (probably a TPD65950 or similar)
85 const TInt KIrqRangeIndexShift = 16;
86 const TInt KIrqNumberMask = 0xFFFF;
88 /** Class defining an interrupt dispatcher */
89 class MInterruptDispatcher
92 IMPORT_C void Register( TIrqRangeIndex aIndex );
94 virtual TInt Bind(TInt aId, TIsr aIsr, TAny* aPtr) = 0;
95 virtual TInt Unbind(TInt aId) = 0;
96 virtual TInt Enable(TInt aId) = 0;
97 virtual TInt Disable(TInt aId) = 0;
98 virtual TInt Clear(TInt aId) = 0;
99 virtual TInt SetPriority(TInt aId, TInt aPriority) = 0;
103 (1) All the IRQ signals are active at low level.
104 (2) These interrupts are internally generated within the MPU subsystem.
106 Table 10-4. Interrupt Mapping to the MPU Subsystem (continued)
110 EOmap3530_IRQ0_EMUINT = (EIrqRangeBaseCore << KIrqRangeIndexShift), //MPU emulation(2)
111 EOmap3530_IRQ1_COMMTX, //MPU emulation(2)
112 EOmap3530_IRQ2_COMMRX, //MPU emulation(2)
113 EOmap3530_IRQ3_BENCH, //MPU emulation(2)
114 EOmap3530_IRQ4_MCBSP2_ST_IRQ, //Sidetone MCBSP2 overflow
115 EOmap3530_IRQ5_MCBSP3_ST_IRQ, //Sidetone MCBSP3 overflow
116 EOmap3530_IRQ6_SSM_ABORT_IRQ, //MPU subsystem secure state-machine abort (2)
117 EOmap3530_IRQ7_SYS_NIRQ, //External source (active low)
118 EOmap3530_IRQ8_RESERVED, //RESERVED
119 EOmap3530_IRQ9_SMX_DBG_IRQ, //SMX error for debug
120 EOmap3530_IRQ10_SMX_APP_IRQ, //SMX error for application
121 EOmap3530_IRQ11_PRCM_MPU_IRQ, //PRCM module IRQ
122 EOmap3530_IRQ12_SDMA_IRQ0, //System DMA request 0(3)
123 EOmap3530_IRQ13_SDMA_IRQ1, //System DMA request 1(3)
124 EOmap3530_IRQ14_SDMA_IRQ2, //System DMA request 2
125 EOmap3530_IRQ15_SDMA_IRQ3, //System DMA request 3
126 EOmap3530_IRQ16_MCBSP1_IRQ, //McBSP module 1 IRQ (3)
127 EOmap3530_IRQ17_MCBSP2_IRQ, //McBSP module 2 IRQ (3)
128 EOmap3530_IRQ18_SR1_IRQ, //SmartReflex™ 1
129 EOmap3530_IRQ19_SR2_IRQ, //SmartReflex™ 2
130 EOmap3530_IRQ20_GPMC_IRQ, //General-purpose memory controller module
131 EOmap3530_IRQ21_SGX_IRQ, //2D/3D graphics module
132 EOmap3530_IRQ22_MCBSP3_IRQ, //McBSP module 3(3)
133 EOmap3530_IRQ23_MCBSP4_IRQ, //McBSP module 4(3)
134 EOmap3530_IRQ24_CAEM_IRQ0, //Camera interface request 0
135 EOmap3530_IRQ25_DSS_IRQ, //Display subsystem module(3)
136 EOmap3530_IRQ26_MAIL_U0_MPU_IRQ, //Mailbox user 0 request
137 EOmap3530_IRQ27_MCBSP5_IRQ, //McBSP module 5 (3)
138 EOmap3530_IRQ28_IVA2_MMU_IRQ, //IVA2 MMU
139 EOmap3530_IRQ29_GPIO1_MPU_IRQ, //GPIO module 1(3)
140 EOmap3530_IRQ30_GPIO2_MPU_IRQ, //GPIO module 2(3)
141 EOmap3530_IRQ31_GPIO3_MPU_IRQ, //GPIO module 3(3)
142 EOmap3530_IRQ32_GPIO4_MPU_IRQ, //GPIO module 4(3)
143 EOmap3530_IRQ33_GPIO5_MPU_IRQ, //GPIO module 5(3)
144 EOmap3530_IRQ34_GPIO6_MPU_IRQ, //GPIO module 6(3)
145 EOmap3530_IRQ35_USIEM_IRQ, //USIM interrupt (HS devices only) (4)
146 EOmap3530_IRQ36_WDT3_IRQ, //Watchdog timer module 3 overflow
147 EOmap3530_IRQ37_GPT1_IRQ, //General-purpose timer module 1
148 EOmap3530_IRQ38_GPT2_IRQ, //General-purpose timer module 2
149 EOmap3530_IRQ39_GPT3_IRQ, //General-purpose timer module 3
150 EOmap3530_IRQ40_GPT4_IRQ, //General-purpose timer module 4
151 EOmap3530_IRQ41_GPT5_IRQ, //General-purpose timer module 5(3)
152 EOmap3530_IRQ42_GPT6_IRQ, //General-purpose timer module 6(3)
153 EOmap3530_IRQ43_GPT7_IRQ, //General-purpose timer module 7(3)
154 EOmap3530_IRQ44_GPT8_IRQ, //General-purpose timer module 8(3)
155 EOmap3530_IRQ45_GPT9_IRQ, //General-purpose timer module 9
156 EOmap3530_IRQ46_GPT10_IRQ, //General-purpose timer module 10
157 EOmap3530_IRQ47_GPT11_IRQ, //General-purpose timer module 11
158 EOmap3530_IRQ48_SPI4_IRQ, //McSPI module 4
159 EOmap3530_IRQ49_SHA1MD5_IRQ2, //SHA-1/MD5 crypto-accelerator 2 (HS devices only)(4)
160 EOmap3530_IRQ50_FPKA_IRQREADY_N, //PKA crypto-accelerator (HS devices only) (4)
161 EOmap3530_IRQ51_SHA2MD5_IRQ, //SHA-2/MD5 crypto-accelerator 1 (HS devices only) (4)
162 EOmap3530_IRQ52_RNG_IRQ, //RNG module (HS devices only) (4)
163 EOmap3530_IRQ53_MG_IRQ, //MG function (3)
164 EOmap3530_IRQ54_MCBSP4_IRQTX, //McBSP module 4 transmit(3)
165 EOmap3530_IRQ55_MCBSP4_IRQRX, //McBSP module 4 receive(3)
166 EOmap3530_IRQ56_I2C1_IRQ, //I2C module 1
167 EOmap3530_IRQ57_I2C2_IRQ, //I2C module 2
168 EOmap3530_IRQ58_HDQ_IRQ, //HDQ/One-wire
169 EOmap3530_IRQ59_McBSP1_IRQTX, //McBSP module 1 transmit(3)
170 EOmap3530_IRQ60_McBSP1_IRQRX, //McBSP module 1 receive(3)
171 EOmap3530_IRQ61_I2C3_IRQ, //I2C module 3
172 EOmap3530_IRQ62_McBSP2_IRQTX, //McBSP module 2 transmit(3)
173 EOmap3530_IRQ63_McBSP2_IRQRX, //McBSP module 2 receive(3)
174 EOmap3530_IRQ64_FPKA_IRQRERROR_N, //PKA crypto-accelerator (HS devices only) (4)
175 EOmap3530_IRQ65_SPI1_IRQ, //McSPI module 1
176 EOmap3530_IRQ66_SPI2_IRQ, //McSPI module 2
177 EOmap3530_IRQ67_RESERVED, //RESERVED
178 EOmap3530_IRQ68_RESERVED, //RESERVED
179 EOmap3530_IRQ69_RESERVED, //RESERVED
180 EOmap3530_IRQ70_RESERVED, //RESERVED
181 EOmap3530_IRQ71_RESERVED, //RESERVED
182 EOmap3530_IRQ72_UART1_IRQ, //UART module 1
183 EOmap3530_IRQ73_UART2_IRQ, //UART module 2
184 EOmap3530_IRQ74_UART3_IRQ, //UART module 3 (also infrared)(3)
185 EOmap3530_IRQ75_PBIAS_IRQ, //Merged interrupt for PBIASlite1 and 2
186 EOmap3530_IRQ76_OHCI_IRQ, //OHCI controller HSUSB MP Host Interrupt
187 EOmap3530_IRQ77_EHCI_IRQ, //EHCI controller HSUSB MP Host Interrupt
188 EOmap3530_IRQ78_TLL_IRQ, //HSUSB MP TLL Interrupt
189 EOmap3530_IRQ79_PARTHASH_IRQ, //SHA2/MD5 crypto-accelerator 1 (HS devices only) (4)
190 EOmap3530_IRQ80_RESERVED, //Reserved
191 EOmap3530_IRQ81_MCBSP5_IRQTX, //McBSP module 5 transmit(3)
192 EOmap3530_IRQ82_MCBSP5_IRQRX, //McBSP module 5 receive(3)
193 EOmap3530_IRQ83_MMC1_IRQ, //MMC/SD module 1
194 EOmap3530_IRQ84_MS_IRQ, //MS-PRO module
195 EOmap3530_IRQ85_RESERVED, //Reserved
196 EOmap3530_IRQ86_MMC2_IRQ, //MMC/SD module 2
197 EOmap3530_IRQ87_MPU_ICR_IRQ, //MPU ICR
198 EOmap3530_IRQ88_RESERVED, //RESERVED
199 EOmap3530_IRQ89_MCBSP3_IRQTX, //McBSP module 3 transmit(3)
200 EOmap3530_IRQ90_MCBSP3_IRQRX, //McBSP module 3 receive(3)
201 EOmap3530_IRQ91_SPI3_IRQ, //McSPI module 3
202 EOmap3530_IRQ92_HSUSB_MC_NINT, //High-Speed USB OTG controller
203 EOmap3530_IRQ93_HSUSB_DMA_NINT, //High-Speed USB OTG DMA controller
204 EOmap3530_IRQ94_MMC3_IRQ, //MMC/SD module 3
205 EOmap3530_IRQ95_GPT12_IRQ, //General-purpose timer module 12
208 EOmap3530_GPIOIRQ_FIRST,
210 EOmap3530_GPIOIRQ_PIN_0,
211 EOmap3530_GPIOIRQ_PIN_1,
212 EOmap3530_GPIOIRQ_PIN_2,
213 EOmap3530_GPIOIRQ_PIN_3,
214 EOmap3530_GPIOIRQ_PIN_4,
215 EOmap3530_GPIOIRQ_PIN_5,
216 EOmap3530_GPIOIRQ_PIN_6,
217 EOmap3530_GPIOIRQ_PIN_7,
218 EOmap3530_GPIOIRQ_PIN_8,
219 EOmap3530_GPIOIRQ_PIN_9,
220 EOmap3530_GPIOIRQ_PIN_10,
221 EOmap3530_GPIOIRQ_PIN_11,
222 EOmap3530_GPIOIRQ_PIN_12,
223 EOmap3530_GPIOIRQ_PIN_13,
224 EOmap3530_GPIOIRQ_PIN_14,
225 EOmap3530_GPIOIRQ_PIN_15,
226 EOmap3530_GPIOIRQ_PIN_16,
227 EOmap3530_GPIOIRQ_PIN_17,
228 EOmap3530_GPIOIRQ_PIN_18,
229 EOmap3530_GPIOIRQ_PIN_19,
230 EOmap3530_GPIOIRQ_PIN_20,
231 EOmap3530_GPIOIRQ_PIN_21,
232 EOmap3530_GPIOIRQ_PIN_22,
233 EOmap3530_GPIOIRQ_PIN_23,
234 EOmap3530_GPIOIRQ_PIN_24,
235 EOmap3530_GPIOIRQ_PIN_25,
236 EOmap3530_GPIOIRQ_PIN_26,
237 EOmap3530_GPIOIRQ_PIN_27,
238 EOmap3530_GPIOIRQ_PIN_28,
239 EOmap3530_GPIOIRQ_PIN_29,
240 EOmap3530_GPIOIRQ_PIN_30,
241 EOmap3530_GPIOIRQ_PIN_31,
242 EOmap3530_GPIOIRQ_PIN_32,
243 EOmap3530_GPIOIRQ_PIN_33,
244 EOmap3530_GPIOIRQ_PIN_34,
245 EOmap3530_GPIOIRQ_PIN_35,
246 EOmap3530_GPIOIRQ_PIN_36,
247 EOmap3530_GPIOIRQ_PIN_37,
248 EOmap3530_GPIOIRQ_PIN_38,
249 EOmap3530_GPIOIRQ_PIN_39,
250 EOmap3530_GPIOIRQ_PIN_40,
251 EOmap3530_GPIOIRQ_PIN_41,
252 EOmap3530_GPIOIRQ_PIN_42,
253 EOmap3530_GPIOIRQ_PIN_43,
254 EOmap3530_GPIOIRQ_PIN_44,
255 EOmap3530_GPIOIRQ_PIN_45,
256 EOmap3530_GPIOIRQ_PIN_46,
257 EOmap3530_GPIOIRQ_PIN_47,
258 EOmap3530_GPIOIRQ_PIN_48,
259 EOmap3530_GPIOIRQ_PIN_49,
260 EOmap3530_GPIOIRQ_PIN_50,
261 EOmap3530_GPIOIRQ_PIN_51,
262 EOmap3530_GPIOIRQ_PIN_52,
263 EOmap3530_GPIOIRQ_PIN_53,
264 EOmap3530_GPIOIRQ_PIN_54,
265 EOmap3530_GPIOIRQ_PIN_55,
266 EOmap3530_GPIOIRQ_PIN_56,
267 EOmap3530_GPIOIRQ_PIN_57,
268 EOmap3530_GPIOIRQ_PIN_58,
269 EOmap3530_GPIOIRQ_PIN_59,
270 EOmap3530_GPIOIRQ_PIN_60,
271 EOmap3530_GPIOIRQ_PIN_61,
272 EOmap3530_GPIOIRQ_PIN_62,
273 EOmap3530_GPIOIRQ_PIN_63,
274 EOmap3530_GPIOIRQ_PIN_64,
275 EOmap3530_GPIOIRQ_PIN_65,
276 EOmap3530_GPIOIRQ_PIN_66,
277 EOmap3530_GPIOIRQ_PIN_67,
278 EOmap3530_GPIOIRQ_PIN_68,
279 EOmap3530_GPIOIRQ_PIN_69,
280 EOmap3530_GPIOIRQ_PIN_70,
281 EOmap3530_GPIOIRQ_PIN_71,
282 EOmap3530_GPIOIRQ_PIN_72,
283 EOmap3530_GPIOIRQ_PIN_73,
284 EOmap3530_GPIOIRQ_PIN_74,
285 EOmap3530_GPIOIRQ_PIN_75,
286 EOmap3530_GPIOIRQ_PIN_76,
287 EOmap3530_GPIOIRQ_PIN_77,
288 EOmap3530_GPIOIRQ_PIN_78,
289 EOmap3530_GPIOIRQ_PIN_79,
290 EOmap3530_GPIOIRQ_PIN_80,
291 EOmap3530_GPIOIRQ_PIN_81,
292 EOmap3530_GPIOIRQ_PIN_82,
293 EOmap3530_GPIOIRQ_PIN_83,
294 EOmap3530_GPIOIRQ_PIN_84,
295 EOmap3530_GPIOIRQ_PIN_85,
296 EOmap3530_GPIOIRQ_PIN_86,
297 EOmap3530_GPIOIRQ_PIN_87,
298 EOmap3530_GPIOIRQ_PIN_88,
299 EOmap3530_GPIOIRQ_PIN_89,
300 EOmap3530_GPIOIRQ_PIN_90,
301 EOmap3530_GPIOIRQ_PIN_91,
302 EOmap3530_GPIOIRQ_PIN_92,
303 EOmap3530_GPIOIRQ_PIN_93,
304 EOmap3530_GPIOIRQ_PIN_94,
305 EOmap3530_GPIOIRQ_PIN_95,
306 EOmap3530_GPIOIRQ_PIN_96,
307 EOmap3530_GPIOIRQ_PIN_97,
308 EOmap3530_GPIOIRQ_PIN_98,
309 EOmap3530_GPIOIRQ_PIN_99,
310 EOmap3530_GPIOIRQ_PIN_100,
311 EOmap3530_GPIOIRQ_PIN_101,
312 EOmap3530_GPIOIRQ_PIN_102,
313 EOmap3530_GPIOIRQ_PIN_103,
314 EOmap3530_GPIOIRQ_PIN_104,
315 EOmap3530_GPIOIRQ_PIN_105,
316 EOmap3530_GPIOIRQ_PIN_106,
317 EOmap3530_GPIOIRQ_PIN_107,
318 EOmap3530_GPIOIRQ_PIN_108,
319 EOmap3530_GPIOIRQ_PIN_109,
320 EOmap3530_GPIOIRQ_PIN_110,
321 EOmap3530_GPIOIRQ_PIN_111,
322 EOmap3530_GPIOIRQ_PIN_112,
323 EOmap3530_GPIOIRQ_PIN_113,
324 EOmap3530_GPIOIRQ_PIN_114,
325 EOmap3530_GPIOIRQ_PIN_115,
326 EOmap3530_GPIOIRQ_PIN_116,
327 EOmap3530_GPIOIRQ_PIN_117,
328 EOmap3530_GPIOIRQ_PIN_118,
329 EOmap3530_GPIOIRQ_PIN_119,
330 EOmap3530_GPIOIRQ_PIN_120,
331 EOmap3530_GPIOIRQ_PIN_121,
332 EOmap3530_GPIOIRQ_PIN_122,
333 EOmap3530_GPIOIRQ_PIN_123,
334 EOmap3530_GPIOIRQ_PIN_124,
335 EOmap3530_GPIOIRQ_PIN_125,
336 EOmap3530_GPIOIRQ_PIN_126,
337 EOmap3530_GPIOIRQ_PIN_127,
338 EOmap3530_GPIOIRQ_PIN_128,
339 EOmap3530_GPIOIRQ_PIN_129,
340 EOmap3530_GPIOIRQ_PIN_130,
341 EOmap3530_GPIOIRQ_PIN_131,
342 EOmap3530_GPIOIRQ_PIN_132,
343 EOmap3530_GPIOIRQ_PIN_133,
344 EOmap3530_GPIOIRQ_PIN_134,
345 EOmap3530_GPIOIRQ_PIN_135,
346 EOmap3530_GPIOIRQ_PIN_136,
347 EOmap3530_GPIOIRQ_PIN_137,
348 EOmap3530_GPIOIRQ_PIN_138,
349 EOmap3530_GPIOIRQ_PIN_139,
350 EOmap3530_GPIOIRQ_PIN_140,
351 EOmap3530_GPIOIRQ_PIN_141,
352 EOmap3530_GPIOIRQ_PIN_142,
353 EOmap3530_GPIOIRQ_PIN_143,
354 EOmap3530_GPIOIRQ_PIN_144,
355 EOmap3530_GPIOIRQ_PIN_145,
356 EOmap3530_GPIOIRQ_PIN_146,
357 EOmap3530_GPIOIRQ_PIN_147,
358 EOmap3530_GPIOIRQ_PIN_148,
359 EOmap3530_GPIOIRQ_PIN_149,
360 EOmap3530_GPIOIRQ_PIN_150,
361 EOmap3530_GPIOIRQ_PIN_151,
362 EOmap3530_GPIOIRQ_PIN_152,
363 EOmap3530_GPIOIRQ_PIN_153,
364 EOmap3530_GPIOIRQ_PIN_154,
365 EOmap3530_GPIOIRQ_PIN_155,
366 EOmap3530_GPIOIRQ_PIN_156,
367 EOmap3530_GPIOIRQ_PIN_157,
368 EOmap3530_GPIOIRQ_PIN_158,
369 EOmap3530_GPIOIRQ_PIN_159,
370 EOmap3530_GPIOIRQ_PIN_160,
371 EOmap3530_GPIOIRQ_PIN_161,
372 EOmap3530_GPIOIRQ_PIN_162,
373 EOmap3530_GPIOIRQ_PIN_163,
374 EOmap3530_GPIOIRQ_PIN_164,
375 EOmap3530_GPIOIRQ_PIN_165,
376 EOmap3530_GPIOIRQ_PIN_166,
377 EOmap3530_GPIOIRQ_PIN_167,
378 EOmap3530_GPIOIRQ_PIN_168,
379 EOmap3530_GPIOIRQ_PIN_169,
380 EOmap3530_GPIOIRQ_PIN_170,
381 EOmap3530_GPIOIRQ_PIN_171,
382 EOmap3530_GPIOIRQ_PIN_172,
383 EOmap3530_GPIOIRQ_PIN_173,
384 EOmap3530_GPIOIRQ_PIN_174,
385 EOmap3530_GPIOIRQ_PIN_175,
386 EOmap3530_GPIOIRQ_PIN_176,
387 EOmap3530_GPIOIRQ_PIN_177,
388 EOmap3530_GPIOIRQ_PIN_178,
389 EOmap3530_GPIOIRQ_PIN_179,
390 EOmap3530_GPIOIRQ_PIN_180,
391 EOmap3530_GPIOIRQ_PIN_181,
392 EOmap3530_GPIOIRQ_PIN_182,
393 EOmap3530_GPIOIRQ_PIN_183,
394 EOmap3530_GPIOIRQ_PIN_184,
395 EOmap3530_GPIOIRQ_PIN_185,
396 EOmap3530_GPIOIRQ_PIN_186,
397 EOmap3530_GPIOIRQ_PIN_187,
398 EOmap3530_GPIOIRQ_PIN_188,
399 EOmap3530_GPIOIRQ_PIN_189,
400 EOmap3530_GPIOIRQ_PIN_190,
401 EOmap3530_GPIOIRQ_PIN_191,
403 EOmap3530_GPIOIRQ_TOTAL,
410 const TInt KNumOmap3530Ints = (EOmap3530_GPIOIRQ_FIRST -1);
412 const TInt KOmap3530MaxIntPriority =0;
413 const TInt KOmap3530MinIntPriority =63;
414 const TInt KOmap3530DefIntPriority =KOmap3530MinIntPriority /2;
415 IMPORT_C void ClearAndDisableTestInterrupt(TInt anId);
416 IMPORT_C void TestInterrupts(TInt id,TIsr func);
419 #endif /*Omap3530_IRQMAP_H*/