1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/epoc32/include/assp/omap3530_assp/omap3530_irqmap.h Wed Mar 31 12:33:34 2010 +0100
1.3 @@ -0,0 +1,419 @@
1.4 +// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// omap3530/assp/inc/omap3530_irqmap.h
1.18 +//
1.19 +
1.20 +#ifndef OMAP3530_IRQMAP_H
1.21 +#define OMAP3530_IRQMAP_H
1.22 +
1.23 +#include <assp/omap3530_assp/omap3530_hardware_base.h>
1.24 +
1.25 +
1.26 +#define INTCPS_BASE Omap3530HwBase::KL4_Core + 0x200000
1.27 +#define INTCPS_SYSCONFIG INTCPS_BASE + 0x10
1.28 +#define INTCPS_SYSSTATUS INTCPS_BASE + 0x14
1.29 +#define INTCPS_PROTECTION INTCPS_BASE + 0x4c
1.30 +#define INTCPS_IRQ_PRIORITY INTCPS_BASE + 0x60
1.31 +#define INTCPS_FIQ_PRIORITY INTCPS_BASE + 0x64
1.32 +
1.33 +
1.34 +#define INTCPS_ITR(n) (INTCPS_BASE + 0x80 +( 0x20 *n))
1.35 +#define INTCPS_THRESHOLD INTCPS_BASE + 0x64
1.36 +#define INTCPS_IDLE INTCPS_BASE + 0x50
1.37 +//#define INTC_INIT_REGISTER1 0x470C8010
1.38 +//#define INTC_INIT_REGISTER2 0x470C8050
1.39 +#define INTCPS_ILRM(n) (INTCPS_BASE + 0x100 +(0x04 *n))
1.40 +
1.41 +//current interrupt vector & clear regs
1.42 +#define INTCPS_SIR_IRQ INTCPS_BASE + 0x40
1.43 +#define INTCPS_SIR_FIQ INTCPS_BASE + 0x44
1.44 +#define INTCPS_CONTROL INTCPS_BASE + 0x48
1.45 +
1.46 +
1.47 +#define INTCPS_PENDING_IRQ(n) (INTCPS_BASE + 0x98 + (0x20 * n))
1.48 +#define INTCPS_PENDING_FIQ(n) (INTCPS_BASE + 0x9c + (0x20 * n))
1.49 +//masks on /off
1.50 +#define INTCPS_MIRn(n) (INTCPS_BASE + 0x084 + (n *0x20))
1.51 +#define INTCPS_MIR_SETn(n) (INTCPS_BASE + 0x08c + (n * 0x20))
1.52 +#define INTCPS_MIR_CLEARn(n) (INTCPS_BASE + 0x088 + (n *0x20))
1.53 +
1.54 +
1.55 +#define INTCPS_ISRSET(n) (INTCPS_BASE + 0x090 + (n *0x20))
1.56 +#define INTCPS_ISR_CLEAR(n) (INTCPS_BASE + 0x094 + (n *0x20))
1.57 +
1.58 +//regvals
1.59 +#define INTCPS_SYSCONFIG_AUTOIDLE 0x1
1.60 +#define INTCPS_IDLE_FUNCIDLE 0x0
1.61 +#define INTCPS_IDLE_TURBO 0x1
1.62 +#define INTCPS_ILRM_DEF_PRI (0x1 <<2)
1.63 +#define INTCPS_ILRM_ROUTE_FIQ 0x1
1.64 +#define INTCPS_ILRM_ROUTE_IRQ 0x00
1.65 +#define INTCPS_MIR_ALL_UNSET 0x00000000
1.66 +#define INTCPS_MIR_ALL_SET 0xffffffff
1.67 +
1.68 +#define INTCPS_CONTROL_IRQ_CLEAR 0x1
1.69 +#define INTCPS_CONTROL_FIQ_CLEAR (0x1 << 1)
1.70 +#define INTCPS_INIT_RG_LOW_PWR 0x1
1.71 +#define INTCPS_PENDING_MASK 0x7f
1.72 +
1.73 +
1.74 +
1.75 +// Base of each interrupt range supported within the ASSP layer
1.76 +// Used to index the correct interrupt handler object
1.77 +enum TIrqRangeIndex
1.78 + {
1.79 + EIrqRangeBaseCore, // main interrupt controller
1.80 + EIrqRangeBasePrcm, // PRCM sub-controller interrupt sources
1.81 + EIrqRangeBaseGpio, // GPIO sub-controller interrupt sources
1.82 + EIrqRangeBasePsu, // Place-holder for off-board PSU device, reserved here because
1.83 + // we know there will always be one (probably a TPD65950 or similar)
1.84 +
1.85 + KIrqRangeCount
1.86 + };
1.87 +
1.88 +const TInt KIrqRangeIndexShift = 16;
1.89 +const TInt KIrqNumberMask = 0xFFFF;
1.90 +
1.91 +/** Class defining an interrupt dispatcher */
1.92 +class MInterruptDispatcher
1.93 + {
1.94 + public:
1.95 + IMPORT_C void Register( TIrqRangeIndex aIndex );
1.96 +
1.97 + virtual TInt Bind(TInt aId, TIsr aIsr, TAny* aPtr) = 0;
1.98 + virtual TInt Unbind(TInt aId) = 0;
1.99 + virtual TInt Enable(TInt aId) = 0;
1.100 + virtual TInt Disable(TInt aId) = 0;
1.101 + virtual TInt Clear(TInt aId) = 0;
1.102 + virtual TInt SetPriority(TInt aId, TInt aPriority) = 0;
1.103 + };
1.104 +
1.105 +/*
1.106 +(1) All the IRQ signals are active at low level.
1.107 +(2) These interrupts are internally generated within the MPU subsystem.
1.108 +
1.109 +Table 10-4. Interrupt Mapping to the MPU Subsystem (continued)
1.110 +*/
1.111 +enum TOmap3530_IRQ {
1.112 +
1.113 + EOmap3530_IRQ0_EMUINT = (EIrqRangeBaseCore << KIrqRangeIndexShift), //MPU emulation(2)
1.114 + EOmap3530_IRQ1_COMMTX, //MPU emulation(2)
1.115 + EOmap3530_IRQ2_COMMRX, //MPU emulation(2)
1.116 + EOmap3530_IRQ3_BENCH, //MPU emulation(2)
1.117 + EOmap3530_IRQ4_MCBSP2_ST_IRQ, //Sidetone MCBSP2 overflow
1.118 + EOmap3530_IRQ5_MCBSP3_ST_IRQ, //Sidetone MCBSP3 overflow
1.119 + EOmap3530_IRQ6_SSM_ABORT_IRQ, //MPU subsystem secure state-machine abort (2)
1.120 + EOmap3530_IRQ7_SYS_NIRQ, //External source (active low)
1.121 + EOmap3530_IRQ8_RESERVED, //RESERVED
1.122 + EOmap3530_IRQ9_SMX_DBG_IRQ, //SMX error for debug
1.123 + EOmap3530_IRQ10_SMX_APP_IRQ, //SMX error for application
1.124 + EOmap3530_IRQ11_PRCM_MPU_IRQ, //PRCM module IRQ
1.125 + EOmap3530_IRQ12_SDMA_IRQ0, //System DMA request 0(3)
1.126 + EOmap3530_IRQ13_SDMA_IRQ1, //System DMA request 1(3)
1.127 + EOmap3530_IRQ14_SDMA_IRQ2, //System DMA request 2
1.128 + EOmap3530_IRQ15_SDMA_IRQ3, //System DMA request 3
1.129 + EOmap3530_IRQ16_MCBSP1_IRQ, //McBSP module 1 IRQ (3)
1.130 + EOmap3530_IRQ17_MCBSP2_IRQ, //McBSP module 2 IRQ (3)
1.131 + EOmap3530_IRQ18_SR1_IRQ, //SmartReflex™ 1
1.132 + EOmap3530_IRQ19_SR2_IRQ, //SmartReflex™ 2
1.133 + EOmap3530_IRQ20_GPMC_IRQ, //General-purpose memory controller module
1.134 + EOmap3530_IRQ21_SGX_IRQ, //2D/3D graphics module
1.135 + EOmap3530_IRQ22_MCBSP3_IRQ, //McBSP module 3(3)
1.136 + EOmap3530_IRQ23_MCBSP4_IRQ, //McBSP module 4(3)
1.137 + EOmap3530_IRQ24_CAEM_IRQ0, //Camera interface request 0
1.138 + EOmap3530_IRQ25_DSS_IRQ, //Display subsystem module(3)
1.139 + EOmap3530_IRQ26_MAIL_U0_MPU_IRQ, //Mailbox user 0 request
1.140 + EOmap3530_IRQ27_MCBSP5_IRQ, //McBSP module 5 (3)
1.141 + EOmap3530_IRQ28_IVA2_MMU_IRQ, //IVA2 MMU
1.142 + EOmap3530_IRQ29_GPIO1_MPU_IRQ, //GPIO module 1(3)
1.143 + EOmap3530_IRQ30_GPIO2_MPU_IRQ, //GPIO module 2(3)
1.144 + EOmap3530_IRQ31_GPIO3_MPU_IRQ, //GPIO module 3(3)
1.145 + EOmap3530_IRQ32_GPIO4_MPU_IRQ, //GPIO module 4(3)
1.146 + EOmap3530_IRQ33_GPIO5_MPU_IRQ, //GPIO module 5(3)
1.147 + EOmap3530_IRQ34_GPIO6_MPU_IRQ, //GPIO module 6(3)
1.148 + EOmap3530_IRQ35_USIEM_IRQ, //USIM interrupt (HS devices only) (4)
1.149 + EOmap3530_IRQ36_WDT3_IRQ, //Watchdog timer module 3 overflow
1.150 + EOmap3530_IRQ37_GPT1_IRQ, //General-purpose timer module 1
1.151 + EOmap3530_IRQ38_GPT2_IRQ, //General-purpose timer module 2
1.152 + EOmap3530_IRQ39_GPT3_IRQ, //General-purpose timer module 3
1.153 + EOmap3530_IRQ40_GPT4_IRQ, //General-purpose timer module 4
1.154 + EOmap3530_IRQ41_GPT5_IRQ, //General-purpose timer module 5(3)
1.155 + EOmap3530_IRQ42_GPT6_IRQ, //General-purpose timer module 6(3)
1.156 + EOmap3530_IRQ43_GPT7_IRQ, //General-purpose timer module 7(3)
1.157 + EOmap3530_IRQ44_GPT8_IRQ, //General-purpose timer module 8(3)
1.158 + EOmap3530_IRQ45_GPT9_IRQ, //General-purpose timer module 9
1.159 + EOmap3530_IRQ46_GPT10_IRQ, //General-purpose timer module 10
1.160 + EOmap3530_IRQ47_GPT11_IRQ, //General-purpose timer module 11
1.161 + EOmap3530_IRQ48_SPI4_IRQ, //McSPI module 4
1.162 + EOmap3530_IRQ49_SHA1MD5_IRQ2, //SHA-1/MD5 crypto-accelerator 2 (HS devices only)(4)
1.163 + EOmap3530_IRQ50_FPKA_IRQREADY_N, //PKA crypto-accelerator (HS devices only) (4)
1.164 + EOmap3530_IRQ51_SHA2MD5_IRQ, //SHA-2/MD5 crypto-accelerator 1 (HS devices only) (4)
1.165 + EOmap3530_IRQ52_RNG_IRQ, //RNG module (HS devices only) (4)
1.166 + EOmap3530_IRQ53_MG_IRQ, //MG function (3)
1.167 + EOmap3530_IRQ54_MCBSP4_IRQTX, //McBSP module 4 transmit(3)
1.168 + EOmap3530_IRQ55_MCBSP4_IRQRX, //McBSP module 4 receive(3)
1.169 + EOmap3530_IRQ56_I2C1_IRQ, //I2C module 1
1.170 + EOmap3530_IRQ57_I2C2_IRQ, //I2C module 2
1.171 + EOmap3530_IRQ58_HDQ_IRQ, //HDQ/One-wire
1.172 + EOmap3530_IRQ59_McBSP1_IRQTX, //McBSP module 1 transmit(3)
1.173 + EOmap3530_IRQ60_McBSP1_IRQRX, //McBSP module 1 receive(3)
1.174 + EOmap3530_IRQ61_I2C3_IRQ, //I2C module 3
1.175 + EOmap3530_IRQ62_McBSP2_IRQTX, //McBSP module 2 transmit(3)
1.176 + EOmap3530_IRQ63_McBSP2_IRQRX, //McBSP module 2 receive(3)
1.177 + EOmap3530_IRQ64_FPKA_IRQRERROR_N, //PKA crypto-accelerator (HS devices only) (4)
1.178 + EOmap3530_IRQ65_SPI1_IRQ, //McSPI module 1
1.179 + EOmap3530_IRQ66_SPI2_IRQ, //McSPI module 2
1.180 + EOmap3530_IRQ67_RESERVED, //RESERVED
1.181 + EOmap3530_IRQ68_RESERVED, //RESERVED
1.182 + EOmap3530_IRQ69_RESERVED, //RESERVED
1.183 + EOmap3530_IRQ70_RESERVED, //RESERVED
1.184 + EOmap3530_IRQ71_RESERVED, //RESERVED
1.185 + EOmap3530_IRQ72_UART1_IRQ, //UART module 1
1.186 + EOmap3530_IRQ73_UART2_IRQ, //UART module 2
1.187 + EOmap3530_IRQ74_UART3_IRQ, //UART module 3 (also infrared)(3)
1.188 + EOmap3530_IRQ75_PBIAS_IRQ, //Merged interrupt for PBIASlite1 and 2
1.189 + EOmap3530_IRQ76_OHCI_IRQ, //OHCI controller HSUSB MP Host Interrupt
1.190 + EOmap3530_IRQ77_EHCI_IRQ, //EHCI controller HSUSB MP Host Interrupt
1.191 + EOmap3530_IRQ78_TLL_IRQ, //HSUSB MP TLL Interrupt
1.192 + EOmap3530_IRQ79_PARTHASH_IRQ, //SHA2/MD5 crypto-accelerator 1 (HS devices only) (4)
1.193 + EOmap3530_IRQ80_RESERVED, //Reserved
1.194 + EOmap3530_IRQ81_MCBSP5_IRQTX, //McBSP module 5 transmit(3)
1.195 + EOmap3530_IRQ82_MCBSP5_IRQRX, //McBSP module 5 receive(3)
1.196 + EOmap3530_IRQ83_MMC1_IRQ, //MMC/SD module 1
1.197 + EOmap3530_IRQ84_MS_IRQ, //MS-PRO module
1.198 + EOmap3530_IRQ85_RESERVED, //Reserved
1.199 + EOmap3530_IRQ86_MMC2_IRQ, //MMC/SD module 2
1.200 + EOmap3530_IRQ87_MPU_ICR_IRQ, //MPU ICR
1.201 + EOmap3530_IRQ88_RESERVED, //RESERVED
1.202 + EOmap3530_IRQ89_MCBSP3_IRQTX, //McBSP module 3 transmit(3)
1.203 + EOmap3530_IRQ90_MCBSP3_IRQRX, //McBSP module 3 receive(3)
1.204 + EOmap3530_IRQ91_SPI3_IRQ, //McSPI module 3
1.205 + EOmap3530_IRQ92_HSUSB_MC_NINT, //High-Speed USB OTG controller
1.206 + EOmap3530_IRQ93_HSUSB_DMA_NINT, //High-Speed USB OTG DMA controller
1.207 + EOmap3530_IRQ94_MMC3_IRQ, //MMC/SD module 3
1.208 + EOmap3530_IRQ95_GPT12_IRQ, //General-purpose timer module 12
1.209 +
1.210 +// IRQ virtual IDs
1.211 + EOmap3530_GPIOIRQ_FIRST,
1.212 +
1.213 + EOmap3530_GPIOIRQ_PIN_0,
1.214 + EOmap3530_GPIOIRQ_PIN_1,
1.215 + EOmap3530_GPIOIRQ_PIN_2,
1.216 + EOmap3530_GPIOIRQ_PIN_3,
1.217 + EOmap3530_GPIOIRQ_PIN_4,
1.218 + EOmap3530_GPIOIRQ_PIN_5,
1.219 + EOmap3530_GPIOIRQ_PIN_6,
1.220 + EOmap3530_GPIOIRQ_PIN_7,
1.221 + EOmap3530_GPIOIRQ_PIN_8,
1.222 + EOmap3530_GPIOIRQ_PIN_9,
1.223 + EOmap3530_GPIOIRQ_PIN_10,
1.224 + EOmap3530_GPIOIRQ_PIN_11,
1.225 + EOmap3530_GPIOIRQ_PIN_12,
1.226 + EOmap3530_GPIOIRQ_PIN_13,
1.227 + EOmap3530_GPIOIRQ_PIN_14,
1.228 + EOmap3530_GPIOIRQ_PIN_15,
1.229 + EOmap3530_GPIOIRQ_PIN_16,
1.230 + EOmap3530_GPIOIRQ_PIN_17,
1.231 + EOmap3530_GPIOIRQ_PIN_18,
1.232 + EOmap3530_GPIOIRQ_PIN_19,
1.233 + EOmap3530_GPIOIRQ_PIN_20,
1.234 + EOmap3530_GPIOIRQ_PIN_21,
1.235 + EOmap3530_GPIOIRQ_PIN_22,
1.236 + EOmap3530_GPIOIRQ_PIN_23,
1.237 + EOmap3530_GPIOIRQ_PIN_24,
1.238 + EOmap3530_GPIOIRQ_PIN_25,
1.239 + EOmap3530_GPIOIRQ_PIN_26,
1.240 + EOmap3530_GPIOIRQ_PIN_27,
1.241 + EOmap3530_GPIOIRQ_PIN_28,
1.242 + EOmap3530_GPIOIRQ_PIN_29,
1.243 + EOmap3530_GPIOIRQ_PIN_30,
1.244 + EOmap3530_GPIOIRQ_PIN_31,
1.245 + EOmap3530_GPIOIRQ_PIN_32,
1.246 + EOmap3530_GPIOIRQ_PIN_33,
1.247 + EOmap3530_GPIOIRQ_PIN_34,
1.248 + EOmap3530_GPIOIRQ_PIN_35,
1.249 + EOmap3530_GPIOIRQ_PIN_36,
1.250 + EOmap3530_GPIOIRQ_PIN_37,
1.251 + EOmap3530_GPIOIRQ_PIN_38,
1.252 + EOmap3530_GPIOIRQ_PIN_39,
1.253 + EOmap3530_GPIOIRQ_PIN_40,
1.254 + EOmap3530_GPIOIRQ_PIN_41,
1.255 + EOmap3530_GPIOIRQ_PIN_42,
1.256 + EOmap3530_GPIOIRQ_PIN_43,
1.257 + EOmap3530_GPIOIRQ_PIN_44,
1.258 + EOmap3530_GPIOIRQ_PIN_45,
1.259 + EOmap3530_GPIOIRQ_PIN_46,
1.260 + EOmap3530_GPIOIRQ_PIN_47,
1.261 + EOmap3530_GPIOIRQ_PIN_48,
1.262 + EOmap3530_GPIOIRQ_PIN_49,
1.263 + EOmap3530_GPIOIRQ_PIN_50,
1.264 + EOmap3530_GPIOIRQ_PIN_51,
1.265 + EOmap3530_GPIOIRQ_PIN_52,
1.266 + EOmap3530_GPIOIRQ_PIN_53,
1.267 + EOmap3530_GPIOIRQ_PIN_54,
1.268 + EOmap3530_GPIOIRQ_PIN_55,
1.269 + EOmap3530_GPIOIRQ_PIN_56,
1.270 + EOmap3530_GPIOIRQ_PIN_57,
1.271 + EOmap3530_GPIOIRQ_PIN_58,
1.272 + EOmap3530_GPIOIRQ_PIN_59,
1.273 + EOmap3530_GPIOIRQ_PIN_60,
1.274 + EOmap3530_GPIOIRQ_PIN_61,
1.275 + EOmap3530_GPIOIRQ_PIN_62,
1.276 + EOmap3530_GPIOIRQ_PIN_63,
1.277 + EOmap3530_GPIOIRQ_PIN_64,
1.278 + EOmap3530_GPIOIRQ_PIN_65,
1.279 + EOmap3530_GPIOIRQ_PIN_66,
1.280 + EOmap3530_GPIOIRQ_PIN_67,
1.281 + EOmap3530_GPIOIRQ_PIN_68,
1.282 + EOmap3530_GPIOIRQ_PIN_69,
1.283 + EOmap3530_GPIOIRQ_PIN_70,
1.284 + EOmap3530_GPIOIRQ_PIN_71,
1.285 + EOmap3530_GPIOIRQ_PIN_72,
1.286 + EOmap3530_GPIOIRQ_PIN_73,
1.287 + EOmap3530_GPIOIRQ_PIN_74,
1.288 + EOmap3530_GPIOIRQ_PIN_75,
1.289 + EOmap3530_GPIOIRQ_PIN_76,
1.290 + EOmap3530_GPIOIRQ_PIN_77,
1.291 + EOmap3530_GPIOIRQ_PIN_78,
1.292 + EOmap3530_GPIOIRQ_PIN_79,
1.293 + EOmap3530_GPIOIRQ_PIN_80,
1.294 + EOmap3530_GPIOIRQ_PIN_81,
1.295 + EOmap3530_GPIOIRQ_PIN_82,
1.296 + EOmap3530_GPIOIRQ_PIN_83,
1.297 + EOmap3530_GPIOIRQ_PIN_84,
1.298 + EOmap3530_GPIOIRQ_PIN_85,
1.299 + EOmap3530_GPIOIRQ_PIN_86,
1.300 + EOmap3530_GPIOIRQ_PIN_87,
1.301 + EOmap3530_GPIOIRQ_PIN_88,
1.302 + EOmap3530_GPIOIRQ_PIN_89,
1.303 + EOmap3530_GPIOIRQ_PIN_90,
1.304 + EOmap3530_GPIOIRQ_PIN_91,
1.305 + EOmap3530_GPIOIRQ_PIN_92,
1.306 + EOmap3530_GPIOIRQ_PIN_93,
1.307 + EOmap3530_GPIOIRQ_PIN_94,
1.308 + EOmap3530_GPIOIRQ_PIN_95,
1.309 + EOmap3530_GPIOIRQ_PIN_96,
1.310 + EOmap3530_GPIOIRQ_PIN_97,
1.311 + EOmap3530_GPIOIRQ_PIN_98,
1.312 + EOmap3530_GPIOIRQ_PIN_99,
1.313 + EOmap3530_GPIOIRQ_PIN_100,
1.314 + EOmap3530_GPIOIRQ_PIN_101,
1.315 + EOmap3530_GPIOIRQ_PIN_102,
1.316 + EOmap3530_GPIOIRQ_PIN_103,
1.317 + EOmap3530_GPIOIRQ_PIN_104,
1.318 + EOmap3530_GPIOIRQ_PIN_105,
1.319 + EOmap3530_GPIOIRQ_PIN_106,
1.320 + EOmap3530_GPIOIRQ_PIN_107,
1.321 + EOmap3530_GPIOIRQ_PIN_108,
1.322 + EOmap3530_GPIOIRQ_PIN_109,
1.323 + EOmap3530_GPIOIRQ_PIN_110,
1.324 + EOmap3530_GPIOIRQ_PIN_111,
1.325 + EOmap3530_GPIOIRQ_PIN_112,
1.326 + EOmap3530_GPIOIRQ_PIN_113,
1.327 + EOmap3530_GPIOIRQ_PIN_114,
1.328 + EOmap3530_GPIOIRQ_PIN_115,
1.329 + EOmap3530_GPIOIRQ_PIN_116,
1.330 + EOmap3530_GPIOIRQ_PIN_117,
1.331 + EOmap3530_GPIOIRQ_PIN_118,
1.332 + EOmap3530_GPIOIRQ_PIN_119,
1.333 + EOmap3530_GPIOIRQ_PIN_120,
1.334 + EOmap3530_GPIOIRQ_PIN_121,
1.335 + EOmap3530_GPIOIRQ_PIN_122,
1.336 + EOmap3530_GPIOIRQ_PIN_123,
1.337 + EOmap3530_GPIOIRQ_PIN_124,
1.338 + EOmap3530_GPIOIRQ_PIN_125,
1.339 + EOmap3530_GPIOIRQ_PIN_126,
1.340 + EOmap3530_GPIOIRQ_PIN_127,
1.341 + EOmap3530_GPIOIRQ_PIN_128,
1.342 + EOmap3530_GPIOIRQ_PIN_129,
1.343 + EOmap3530_GPIOIRQ_PIN_130,
1.344 + EOmap3530_GPIOIRQ_PIN_131,
1.345 + EOmap3530_GPIOIRQ_PIN_132,
1.346 + EOmap3530_GPIOIRQ_PIN_133,
1.347 + EOmap3530_GPIOIRQ_PIN_134,
1.348 + EOmap3530_GPIOIRQ_PIN_135,
1.349 + EOmap3530_GPIOIRQ_PIN_136,
1.350 + EOmap3530_GPIOIRQ_PIN_137,
1.351 + EOmap3530_GPIOIRQ_PIN_138,
1.352 + EOmap3530_GPIOIRQ_PIN_139,
1.353 + EOmap3530_GPIOIRQ_PIN_140,
1.354 + EOmap3530_GPIOIRQ_PIN_141,
1.355 + EOmap3530_GPIOIRQ_PIN_142,
1.356 + EOmap3530_GPIOIRQ_PIN_143,
1.357 + EOmap3530_GPIOIRQ_PIN_144,
1.358 + EOmap3530_GPIOIRQ_PIN_145,
1.359 + EOmap3530_GPIOIRQ_PIN_146,
1.360 + EOmap3530_GPIOIRQ_PIN_147,
1.361 + EOmap3530_GPIOIRQ_PIN_148,
1.362 + EOmap3530_GPIOIRQ_PIN_149,
1.363 + EOmap3530_GPIOIRQ_PIN_150,
1.364 + EOmap3530_GPIOIRQ_PIN_151,
1.365 + EOmap3530_GPIOIRQ_PIN_152,
1.366 + EOmap3530_GPIOIRQ_PIN_153,
1.367 + EOmap3530_GPIOIRQ_PIN_154,
1.368 + EOmap3530_GPIOIRQ_PIN_155,
1.369 + EOmap3530_GPIOIRQ_PIN_156,
1.370 + EOmap3530_GPIOIRQ_PIN_157,
1.371 + EOmap3530_GPIOIRQ_PIN_158,
1.372 + EOmap3530_GPIOIRQ_PIN_159,
1.373 + EOmap3530_GPIOIRQ_PIN_160,
1.374 + EOmap3530_GPIOIRQ_PIN_161,
1.375 + EOmap3530_GPIOIRQ_PIN_162,
1.376 + EOmap3530_GPIOIRQ_PIN_163,
1.377 + EOmap3530_GPIOIRQ_PIN_164,
1.378 + EOmap3530_GPIOIRQ_PIN_165,
1.379 + EOmap3530_GPIOIRQ_PIN_166,
1.380 + EOmap3530_GPIOIRQ_PIN_167,
1.381 + EOmap3530_GPIOIRQ_PIN_168,
1.382 + EOmap3530_GPIOIRQ_PIN_169,
1.383 + EOmap3530_GPIOIRQ_PIN_170,
1.384 + EOmap3530_GPIOIRQ_PIN_171,
1.385 + EOmap3530_GPIOIRQ_PIN_172,
1.386 + EOmap3530_GPIOIRQ_PIN_173,
1.387 + EOmap3530_GPIOIRQ_PIN_174,
1.388 + EOmap3530_GPIOIRQ_PIN_175,
1.389 + EOmap3530_GPIOIRQ_PIN_176,
1.390 + EOmap3530_GPIOIRQ_PIN_177,
1.391 + EOmap3530_GPIOIRQ_PIN_178,
1.392 + EOmap3530_GPIOIRQ_PIN_179,
1.393 + EOmap3530_GPIOIRQ_PIN_180,
1.394 + EOmap3530_GPIOIRQ_PIN_181,
1.395 + EOmap3530_GPIOIRQ_PIN_182,
1.396 + EOmap3530_GPIOIRQ_PIN_183,
1.397 + EOmap3530_GPIOIRQ_PIN_184,
1.398 + EOmap3530_GPIOIRQ_PIN_185,
1.399 + EOmap3530_GPIOIRQ_PIN_186,
1.400 + EOmap3530_GPIOIRQ_PIN_187,
1.401 + EOmap3530_GPIOIRQ_PIN_188,
1.402 + EOmap3530_GPIOIRQ_PIN_189,
1.403 + EOmap3530_GPIOIRQ_PIN_190,
1.404 + EOmap3530_GPIOIRQ_PIN_191,
1.405 +
1.406 + EOmap3530_GPIOIRQ_TOTAL,
1.407 +
1.408 + EOmap3530_TOTAL_IRQS
1.409 +};
1.410 +
1.411 +
1.412 +
1.413 +const TInt KNumOmap3530Ints = (EOmap3530_GPIOIRQ_FIRST -1);
1.414 +
1.415 +const TInt KOmap3530MaxIntPriority =0;
1.416 +const TInt KOmap3530MinIntPriority =63;
1.417 +const TInt KOmap3530DefIntPriority =KOmap3530MinIntPriority /2;
1.418 +IMPORT_C void ClearAndDisableTestInterrupt(TInt anId);
1.419 +IMPORT_C void TestInterrupts(TInt id,TIsr func);
1.420 +
1.421 +
1.422 +#endif /*Omap3530_IRQMAP_H*/