1 // Copyright (c) 2006-2009 Nokia Corporation and/or its subsidiary(-ies).
2 // All rights reserved.
3 // This component and the accompanying materials are made available
4 // under the terms of the License "Eclipse Public License v1.0"
5 // which accompanies this distribution, and is available
6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".
8 // Initial Contributors:
9 // Nokia Corporation - initial contribution.
14 // e32test\mmu\d_cache.h
22 #ifndef __KERNEL_MODE__
26 _LIT(KCacheTestDriverName,"d_cache");
27 const TInt KMaxThresholdTypes = 5; // 1.Instruction/Unified, 2.Data, 3.AltD 4.Data_IMB 5.L210/L2XScale
30 const TInt KSingleCacheDescSize = 30;//Desc. of each particular cache. Must be *2 as t_cache converts TDes8 into TDes16.
31 const TInt KCacheDescSize = 200;//Desc. of the cache as a whole on the platforms. Must be *2 as t_cache converts TDes8 into TDes16.
32 const TInt KMaxCaches = 8; //Max number of caches. In theory, could be more but...
33 /**User side channel to Device Driver.*/
34 class RCacheTestDevice : public RBusLogicalChannel
42 ETestWriteBackReadAllocate,
43 ETestWriteBackWriteAllocate,
58 //Description of a single cache
61 TInt8 iLevel; // Cache level (1-8)
62 TInt8 iData; // 1 if it is data (or unified) cache, 0 otherwise
63 TInt8 iCode; // 1 if this is instruction (or unified) cache, 0 otherwise
64 TInt iSize; // In bytes. Should be = iLineLength * iWays * iSets
65 TInt iLineSize; // In bytes
66 TInt iWays; // Number of sets in cache
67 TInt iSets; // Number of ways in cache
68 TBuf8<2*KSingleCacheDescSize> iDesc; // Description, eg. L1_Instr_Inner L1_Data L2_Unified L210_Unified_Outer
73 TBuf8<2*KCacheDescSize> iDesc; // General decription of the platform. E.g. '1176 with L210'.
74 TInt iCacheCount; // How many caches are there all together.
75 TInt iMaxCacheSize; // All caches considered. In bytes
76 TInt iMemoryRemapping; // 1 if memory remapping is ON.
77 TInt iOuterCache; // 1 if there is outer cache
78 TInt iDmaBufferAlignment; // Maximum size of any data cache line
79 TCacheSingle iCache[KMaxCaches];// Info for each separate cache.
82 enum TCacheAttr//Specifies cache attributes
84 { //CacheAttr BC(armv5) TEX:BC(armv6) memory_remapping(armv6K, armv7)
86 E_FullyBlocking, //00 00 SO/Shared T0
87 E_Buffered_NC, //01 00 Device/Shared T1
88 E_Buffered_C, //02 01 Normal-Uncached T1
91 E_InnerWT, //05 10 Normal-InnerWT T2
92 E_InnerWBRA, //06 11 Normal-InnerWB-RA T3
93 E_InnerWB, //07 11 Normal-InnerWB-RAWA T3
95 E_OuterWT, //50 10 Normal/OuterWT T2
96 E_OuterWBRA, //60 11 Normal/OuterBW-RA T2
97 E_OuterWB, //70 11 Normal/OuterBW-RAWA T2
99 E_InOutWT, //55 10 Normal/FullyWT T2
100 E_InOutWBRA, //66 11 Normal/FullyWB-RA T3
101 E_InOutWB, //77 11 Normal/FullyWB-RAWA T3
103 // Memory remapped attributes
104 E_StronglyOrder, //-- T0/00 SO T0
105 E_Device, //-- T0/00 Device T1
106 E_Normal_Uncached, //-- T0/01 Normal/Uncached T2
107 E_Normal_Cached, //-- T0/11 Normal/FullyBW T3
108 E_KernelInternal4, //-- ----- --- T4
109 E_PlatformSpecific5, //-- ----- --- T5
110 E_PlatformSpecific6, //-- ----- --- T6
111 E_PlatformSpecific7, //-- ----- --- T7
114 E_InnerWT_Remapped, //-- -- -- T4/Normal/InnerWT-OuterNC
115 E_InnerWBRA_Remapped, //-- -- -- T4/Normal/InnerWBRA-OuterNC
116 E_InnerWB_Remapped, //-- -- -- T4/Normal/InnerWB-OuterNC
118 E_OuterWT_Remapped, //-- -- -- T4/Normal/InnerNC-OuterWT
119 E_OuterWBRA_Remapped, //-- -- -- T4/Normal/InnerNC-OuterWBRA
120 E_OuterWB_Remapped, //-- -- -- T4/Normal/InnerNC-OuterWBRA
122 E_InOutWT_Remapped, //-- -- -- T4/Normal/InnerWT-OuterWT
123 E_InOutWBRA_Remapped, //-- -- -- T4/Normal/InnerWBRA-OuterWBRA
124 E_InOutWB_Remapped, //-- -- -- T4/Normal/InnerWB-OuterWB
126 // Kernel heap for data test / rom-image for code test
132 TChunkTest() {iShared=EFalse; iUseCase=0; iLoops=0;}
133 TChunkTest(TInt aUseCase, TInt aSize, TInt aLoops) {iShared=EFalse;iUseCase=aUseCase;iLoops=aLoops;iSize=aSize;}
135 TInt iSize; //Defines the size of memory (either code or data) to test against.
136 TCacheAttr iCacheAttr; //Defines cache attributes of the memory to test.
137 TBool iShared; //Defines the shared bit
138 TInt iUseCase; //Specifies which test to execute.
139 TInt iLoops; //The number of loops to execute.
141 TUint32 iActualMapAttr; //The actual mapping attributes of the chunk. Will be set by the driver.
142 TInt iTime; //The number of kernel ticks. Will be set by the driver.
145 #ifndef __KERNEL_MODE__
147 {return DoCreate(KCacheTestDriverName,TVersion(1,0,0),KNullUnit,NULL,NULL);}
148 TInt GetCacheInfo (TCacheInfo& aCaches)
149 {return DoControl(EGetCacheInfo, reinterpret_cast<TAny*>(&aCaches));}
150 TInt TestDataChunk (TChunkTest& aChunkTest)
151 {return DoControl(ETestDataChunk, reinterpret_cast<TAny*>(&aChunkTest));}
152 TInt TestCodeChunk (TChunkTest& aChunkTest)
153 {return DoControl(ETestCodeChunk, reinterpret_cast<TAny*>(&aChunkTest));}
154 TInt TestWriteBackReadAllocate (TChunkTest& aChunkTest)
155 {return DoControl(ETestWriteBackReadAllocate, reinterpret_cast<TAny*>(&aChunkTest));}
156 TInt TestWriteBackWriteAllocate (TChunkTest& aChunkTest)
157 {return DoControl(ETestWriteBackWriteAllocate, reinterpret_cast<TAny*>(&aChunkTest));}
158 TInt TestL2Maintenance()
159 {return DoControl(ETesL2Maintenance);}
160 TInt GetThreshold(TThresholdInfo& aThreshold)
161 {return DoControl(EGetThreshold, reinterpret_cast<TAny*>(&aThreshold));}
162 TInt SetThreshold(TThresholdInfo& aThreshold)
163 {return DoControl(ESetThreshold, reinterpret_cast<TAny*>(&aThreshold));}
164 TInt TestUseCase (TChunkTest& aChunkTest)
165 {return DoControl(ETestUseCase, reinterpret_cast<TAny*>(&aChunkTest));}
166 #endif //__KERNEL_MODE__
168 #endif //__D_CACHE_H__