Update contrib.
1 // Copyright (c) 2003-2009 Nokia Corporation and/or its subsidiary(-ies).
2 // All rights reserved.
3 // This component and the accompanying materials are made available
4 // under the terms of the License "Eclipse Public License v1.0"
5 // which accompanies this distribution, and is available
6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".
8 // Initial Contributors:
9 // Nokia Corporation - initial contribution.
14 // e32test\math\t_vfp.cia
23 #define _DIE(x) asm(".word %a0" : : "i" ((TInt)( 0xe7f000f0|((x)&0x0f)|(((x)&0xfff0)<<4) )));
24 #define DIE _DIE(__LINE__);
26 /******************************************************************************
28 ******************************************************************************/
29 __NAKED__ TUint32 Vfp::Fpscr()
31 VFP_FMRX(,0,VFP_XREG_FPSCR);
35 __NAKED__ void Vfp::SetFpscr(TUint32 /*aVal*/)
37 VFP_FMXR(,VFP_XREG_FPSCR,0);
41 /******************************************************************************
42 * Single precision operations
43 ******************************************************************************/
44 __NAKED__ TInt32 Vfp::SRegInt(TInt /*aReg*/)
49 __NAKED__ TReal32 Vfp::SReg(TInt /*aReg*/)
52 asm("addls pc, pc, r0, lsl #3 ");
100 VFP_FMRS(CC_AL,0,23);
102 VFP_FMRS(CC_AL,0,24);
104 VFP_FMRS(CC_AL,0,25);
106 VFP_FMRS(CC_AL,0,26);
108 VFP_FMRS(CC_AL,0,27);
110 VFP_FMRS(CC_AL,0,28);
112 VFP_FMRS(CC_AL,0,29);
114 VFP_FMRS(CC_AL,0,30);
116 VFP_FMRS(CC_AL,0,31);
120 __NAKED__ void Vfp::SetSReg(TInt32 /*aVal*/, TInt /*aReg*/)
125 __NAKED__ void Vfp::SetSReg(TReal32 /*aVal*/, TInt /*aReg*/)
128 asm("addls pc, pc, r1, lsl #3 ");
150 VFP_FMSR(CC_AL,10,0);
152 VFP_FMSR(CC_AL,11,0);
154 VFP_FMSR(CC_AL,12,0);
156 VFP_FMSR(CC_AL,13,0);
158 VFP_FMSR(CC_AL,14,0);
160 VFP_FMSR(CC_AL,15,0);
162 VFP_FMSR(CC_AL,16,0);
164 VFP_FMSR(CC_AL,17,0);
166 VFP_FMSR(CC_AL,18,0);
168 VFP_FMSR(CC_AL,19,0);
170 VFP_FMSR(CC_AL,20,0);
172 VFP_FMSR(CC_AL,21,0);
174 VFP_FMSR(CC_AL,22,0);
176 VFP_FMSR(CC_AL,23,0);
178 VFP_FMSR(CC_AL,24,0);
180 VFP_FMSR(CC_AL,25,0);
182 VFP_FMSR(CC_AL,26,0);
184 VFP_FMSR(CC_AL,27,0);
186 VFP_FMSR(CC_AL,28,0);
188 VFP_FMSR(CC_AL,29,0);
190 VFP_FMSR(CC_AL,30,0);
192 VFP_FMSR(CC_AL,31,0);
196 __NAKED__ void Vfp::AbsS()
198 asm("nop "); // so that RVCT doesn't complain about branches to non-code symbols
199 VFP_FABSS(CC_AL,0,1);
203 __NAKED__ void Vfp::AddS()
205 asm("nop "); // so that RVCT doesn't complain about branches to non-code symbols
206 VFP_FADDS(CC_AL,0,1,2);
210 __NAKED__ void Vfp::CmpS()
212 VFP_FCMPS(CC_AL,0,1);
216 __NAKED__ void Vfp::CmpES()
218 VFP_FCMPES(CC_AL,0,1);
222 __NAKED__ void Vfp::CmpEZS()
224 VFP_FCMPEZS(CC_AL,0);
228 __NAKED__ void Vfp::CmpZS()
234 __NAKED__ void Vfp::Cpy0S(TInt /*aReg*/)
237 asm("addls pc, pc, r0, lsl #3 ");
239 VFP_FCPYS(CC_AL,0,0);
241 VFP_FCPYS(CC_AL,0,1);
243 VFP_FCPYS(CC_AL,0,2);
245 VFP_FCPYS(CC_AL,0,3);
247 VFP_FCPYS(CC_AL,0,4);
249 VFP_FCPYS(CC_AL,0,5);
251 VFP_FCPYS(CC_AL,0,6);
253 VFP_FCPYS(CC_AL,0,7);
255 VFP_FCPYS(CC_AL,0,8);
257 VFP_FCPYS(CC_AL,0,9);
259 VFP_FCPYS(CC_AL,0,10);
261 VFP_FCPYS(CC_AL,0,11);
263 VFP_FCPYS(CC_AL,0,12);
265 VFP_FCPYS(CC_AL,0,13);
267 VFP_FCPYS(CC_AL,0,14);
269 VFP_FCPYS(CC_AL,0,15);
271 VFP_FCPYS(CC_AL,0,16);
273 VFP_FCPYS(CC_AL,0,17);
275 VFP_FCPYS(CC_AL,0,18);
277 VFP_FCPYS(CC_AL,0,19);
279 VFP_FCPYS(CC_AL,0,20);
281 VFP_FCPYS(CC_AL,0,21);
283 VFP_FCPYS(CC_AL,0,22);
285 VFP_FCPYS(CC_AL,0,23);
287 VFP_FCPYS(CC_AL,0,24);
289 VFP_FCPYS(CC_AL,0,25);
291 VFP_FCPYS(CC_AL,0,26);
293 VFP_FCPYS(CC_AL,0,27);
295 VFP_FCPYS(CC_AL,0,28);
297 VFP_FCPYS(CC_AL,0,29);
299 VFP_FCPYS(CC_AL,0,30);
301 VFP_FCPYS(CC_AL,0,31);
305 __NAKED__ void Vfp::CpyS0(TInt /*aReg*/)
308 asm("addls pc, pc, r0, lsl #3 ");
310 VFP_FCPYS(CC_AL,0,0);
312 VFP_FCPYS(CC_AL,1,0);
314 VFP_FCPYS(CC_AL,2,0);
316 VFP_FCPYS(CC_AL,3,0);
318 VFP_FCPYS(CC_AL,4,0);
320 VFP_FCPYS(CC_AL,5,0);
322 VFP_FCPYS(CC_AL,6,0);
324 VFP_FCPYS(CC_AL,7,0);
326 VFP_FCPYS(CC_AL,8,0);
328 VFP_FCPYS(CC_AL,9,0);
330 VFP_FCPYS(CC_AL,10,0);
332 VFP_FCPYS(CC_AL,11,0);
334 VFP_FCPYS(CC_AL,12,0);
336 VFP_FCPYS(CC_AL,13,0);
338 VFP_FCPYS(CC_AL,14,0);
340 VFP_FCPYS(CC_AL,15,0);
342 VFP_FCPYS(CC_AL,16,0);
344 VFP_FCPYS(CC_AL,17,0);
346 VFP_FCPYS(CC_AL,18,0);
348 VFP_FCPYS(CC_AL,19,0);
350 VFP_FCPYS(CC_AL,20,0);
352 VFP_FCPYS(CC_AL,21,0);
354 VFP_FCPYS(CC_AL,22,0);
356 VFP_FCPYS(CC_AL,23,0);
358 VFP_FCPYS(CC_AL,24,0);
360 VFP_FCPYS(CC_AL,25,0);
362 VFP_FCPYS(CC_AL,26,0);
364 VFP_FCPYS(CC_AL,27,0);
366 VFP_FCPYS(CC_AL,28,0);
368 VFP_FCPYS(CC_AL,29,0);
370 VFP_FCPYS(CC_AL,30,0);
372 VFP_FCPYS(CC_AL,31,0);
376 __NAKED__ void Vfp::DivS()
378 asm("nop "); // so that RVCT doesn't complain about branches to non-code symbols
379 VFP_FDIVS(CC_AL,0,1,2);
383 __NAKED__ void Vfp::MacS()
385 asm("nop "); // so that RVCT doesn't complain about branches to non-code symbols
386 VFP_FMACS(CC_AL,0,1,2);
390 __NAKED__ void Vfp::MscS()
392 asm("nop "); // so that RVCT doesn't complain about branches to non-code symbols
393 VFP_FMSCS(CC_AL,0,1,2);
397 __NAKED__ void Vfp::MulS()
399 asm("nop "); // so that RVCT doesn't complain about branches to non-code symbols
400 VFP_FMULS(CC_AL,0,1,2);
404 __NAKED__ void Vfp::NegS()
406 asm("nop "); // so that RVCT doesn't complain about branches to non-code symbols
407 VFP_FNEGS(CC_AL,0,1);
411 __NAKED__ void Vfp::NMacS()
413 asm("nop "); // so that RVCT doesn't complain about branches to non-code symbols
414 VFP_FNMACS(CC_AL,0,1,2);
418 __NAKED__ void Vfp::NMscS()
420 asm("nop "); // so that RVCT doesn't complain about branches to non-code symbols
421 VFP_FNMSCS(CC_AL,0,1,2);
425 __NAKED__ void Vfp::NMulS()
427 asm("nop "); // so that RVCT doesn't complain about branches to non-code symbols
428 VFP_FNMULS(CC_AL,0,1,2);
432 __NAKED__ void Vfp::SqrtS()
434 asm("nop "); // so that RVCT doesn't complain about branches to non-code symbols
435 VFP_FSQRTS(CC_AL,0,1);
439 __NAKED__ void Vfp::SubS()
441 asm("nop "); // so that RVCT doesn't complain about branches to non-code symbols
442 VFP_FSUBS(CC_AL,0,1,2);
449 /******************************************************************************
450 * Double precision operations
451 ******************************************************************************/
452 __NAKED__ TInt64 Vfp::DRegInt(TInt /*aReg*/)
457 __NAKED__ TReal64 Vfp::DReg(TInt /*aReg*/)
464 asm("addls r0, r0, r0, lsl #1 ");
465 asm("addls pc, pc, r0, lsl #2 ");
469 // VFP_FLDD(CC_AL,4,5,0);
471 VFP_FMRDL(CC_AL,0,0);
472 VFP_FMRDH(CC_AL,1,0);
474 VFP_FMRDL(CC_AL,0,1);
475 VFP_FMRDH(CC_AL,1,1);
477 VFP_FMRDL(CC_AL,0,2);
478 VFP_FMRDH(CC_AL,1,2);
480 VFP_FMRDL(CC_AL,0,3);
481 VFP_FMRDH(CC_AL,1,3);
483 VFP_FMRDL(CC_AL,0,4);
484 VFP_FMRDH(CC_AL,1,4);
486 VFP_FMRDL(CC_AL,0,5);
487 VFP_FMRDH(CC_AL,1,5);
489 VFP_FMRDL(CC_AL,0,6);
490 VFP_FMRDH(CC_AL,1,6);
492 VFP_FMRDL(CC_AL,0,7);
493 VFP_FMRDH(CC_AL,1,7);
495 VFP_FMRDL(CC_AL,0,8);
496 VFP_FMRDH(CC_AL,1,8);
498 VFP_FMRDL(CC_AL,0,9);
499 VFP_FMRDH(CC_AL,1,9);
501 VFP_FMRDL(CC_AL,0,10);
502 VFP_FMRDH(CC_AL,1,10);
504 VFP_FMRDL(CC_AL,0,11);
505 VFP_FMRDH(CC_AL,1,11);
507 VFP_FMRDL(CC_AL,0,12);
508 VFP_FMRDH(CC_AL,1,12);
510 VFP_FMRDL(CC_AL,0,13);
511 VFP_FMRDH(CC_AL,1,13);
513 VFP_FMRDL(CC_AL,0,14);
514 VFP_FMRDH(CC_AL,1,14);
516 VFP_FMRDL(CC_AL,0,15);
517 VFP_FMRDH(CC_AL,1,15);
521 VFP_FMRDL(CC_AL,0,16);
522 VFP_FMRDH(CC_AL,1,16);
524 VFP_FMRDL(CC_AL,0,17);
525 VFP_FMRDH(CC_AL,1,17);
527 VFP_FMRDL(CC_AL,0,18);
528 VFP_FMRDH(CC_AL,1,18);
530 VFP_FMRDL(CC_AL,0,19);
531 VFP_FMRDH(CC_AL,1,19);
533 VFP_FMRDL(CC_AL,0,20);
534 VFP_FMRDH(CC_AL,1,20);
536 VFP_FMRDL(CC_AL,0,21);
537 VFP_FMRDH(CC_AL,1,21);
539 VFP_FMRDL(CC_AL,0,22);
540 VFP_FMRDH(CC_AL,1,22);
542 VFP_FMRDL(CC_AL,0,23);
543 VFP_FMRDH(CC_AL,1,23);
545 VFP_FMRDL(CC_AL,0,24);
546 VFP_FMRDH(CC_AL,1,24);
548 VFP_FMRDL(CC_AL,0,25);
549 VFP_FMRDH(CC_AL,1,25);
551 VFP_FMRDL(CC_AL,0,26);
552 VFP_FMRDH(CC_AL,1,26);
554 VFP_FMRDL(CC_AL,0,27);
555 VFP_FMRDH(CC_AL,1,27);
557 VFP_FMRDL(CC_AL,0,28);
558 VFP_FMRDH(CC_AL,1,28);
560 VFP_FMRDL(CC_AL,0,29);
561 VFP_FMRDH(CC_AL,1,29);
563 VFP_FMRDL(CC_AL,0,30);
564 VFP_FMRDH(CC_AL,1,30);
566 VFP_FMRDL(CC_AL,0,31);
567 VFP_FMRDH(CC_AL,1,31);
568 #endif // __TEST_VFPV3
571 #ifdef __DOUBLE_WORDS_SWAPPED__
579 __NAKED__ void Vfp::SetDReg(TInt64 /*aVal*/, TInt /*aReg*/)
584 __NAKED__ void Vfp::SetDReg(TReal64 /*aVal*/, TInt /*aReg*/)
586 #ifdef __DOUBLE_WORDS_SWAPPED__
596 asm("addls r2, r2, r2, lsl #1 ");
597 asm("addls pc, pc, r2, lsl #2 ");
599 VFP_FMDLR(CC_AL,0,0);
600 VFP_FMDHR(CC_AL,0,1);
602 VFP_FMDLR(CC_AL,1,0);
603 VFP_FMDHR(CC_AL,1,1);
605 VFP_FMDLR(CC_AL,2,0);
606 VFP_FMDHR(CC_AL,2,1);
608 VFP_FMDLR(CC_AL,3,0);
609 VFP_FMDHR(CC_AL,3,1);
611 VFP_FMDLR(CC_AL,4,0);
612 VFP_FMDHR(CC_AL,4,1);
614 VFP_FMDLR(CC_AL,5,0);
615 VFP_FMDHR(CC_AL,5,1);
617 VFP_FMDLR(CC_AL,6,0);
618 VFP_FMDHR(CC_AL,6,1);
620 VFP_FMDLR(CC_AL,7,0);
621 VFP_FMDHR(CC_AL,7,1);
623 VFP_FMDLR(CC_AL,8,0);
624 VFP_FMDHR(CC_AL,8,1);
626 VFP_FMDLR(CC_AL,9,0);
627 VFP_FMDHR(CC_AL,9,1);
629 VFP_FMDLR(CC_AL,10,0);
630 VFP_FMDHR(CC_AL,10,1);
632 VFP_FMDLR(CC_AL,11,0);
633 VFP_FMDHR(CC_AL,11,1);
635 VFP_FMDLR(CC_AL,12,0);
636 VFP_FMDHR(CC_AL,12,1);
638 VFP_FMDLR(CC_AL,13,0);
639 VFP_FMDHR(CC_AL,13,1);
641 VFP_FMDLR(CC_AL,14,0);
642 VFP_FMDHR(CC_AL,14,1);
644 VFP_FMDLR(CC_AL,15,0);
645 VFP_FMDHR(CC_AL,15,1);
648 VFP_FMDLR(CC_AL,16,0);
649 VFP_FMDHR(CC_AL,16,1);
651 VFP_FMDLR(CC_AL,17,0);
652 VFP_FMDHR(CC_AL,17,1);
654 VFP_FMDLR(CC_AL,18,0);
655 VFP_FMDHR(CC_AL,18,1);
657 VFP_FMDLR(CC_AL,19,0);
658 VFP_FMDHR(CC_AL,19,1);
660 VFP_FMDLR(CC_AL,20,0);
661 VFP_FMDHR(CC_AL,20,1);
663 VFP_FMDLR(CC_AL,21,0);
664 VFP_FMDHR(CC_AL,21,1);
666 VFP_FMDLR(CC_AL,22,0);
667 VFP_FMDHR(CC_AL,22,1);
669 VFP_FMDLR(CC_AL,23,0);
670 VFP_FMDHR(CC_AL,23,1);
672 VFP_FMDLR(CC_AL,24,0);
673 VFP_FMDHR(CC_AL,24,1);
675 VFP_FMDLR(CC_AL,25,0);
676 VFP_FMDHR(CC_AL,25,1);
678 VFP_FMDLR(CC_AL,26,0);
679 VFP_FMDHR(CC_AL,26,1);
681 VFP_FMDLR(CC_AL,27,0);
682 VFP_FMDHR(CC_AL,27,1);
684 VFP_FMDLR(CC_AL,28,0);
685 VFP_FMDHR(CC_AL,28,1);
687 VFP_FMDLR(CC_AL,29,0);
688 VFP_FMDHR(CC_AL,29,1);
690 VFP_FMDLR(CC_AL,30,0);
691 VFP_FMDHR(CC_AL,30,1);
693 VFP_FMDLR(CC_AL,31,0);
694 VFP_FMDHR(CC_AL,31,1);
696 #endif // __TEST_VFPV3
699 __NAKED__ void Vfp::AbsD()
705 __NAKED__ void Vfp::AddD()
711 __NAKED__ void Vfp::CmpD()
717 __NAKED__ void Vfp::CmpED()
723 __NAKED__ void Vfp::CmpEZD()
729 __NAKED__ void Vfp::CmpZD()
735 __NAKED__ void Vfp::Cpy0D(TInt /*aReg*/)
738 asm("addls pc, pc, r0, lsl #3 ");
774 __NAKED__ void Vfp::CpyD0(TInt /*aReg*/)
777 asm("addls pc, pc, r0, lsl #3 ");
813 __NAKED__ void Vfp::DivD()
819 __NAKED__ void Vfp::MacD()
825 __NAKED__ void Vfp::MscD()
831 __NAKED__ void Vfp::MulD()
837 __NAKED__ void Vfp::NegD()
843 __NAKED__ void Vfp::NMacD()
849 __NAKED__ void Vfp::NMscD()
855 __NAKED__ void Vfp::NMulD()
861 __NAKED__ void Vfp::SqrtD()
867 __NAKED__ void Vfp::SubD()
874 /******************************************************************************
875 * Conversion operations
876 ******************************************************************************/
877 __NAKED__ void Vfp::CvtDS()
879 VFP_FCVTDS(CC_AL,0,2);
883 __NAKED__ void Vfp::CvtSD()
885 VFP_FCVTSD(CC_AL,0,1);
889 __NAKED__ void Vfp::SitoD()
891 VFP_FSITOD(CC_AL,0,2);
895 __NAKED__ void Vfp::SitoS()
897 VFP_FSITOS(CC_AL,0,2);
901 __NAKED__ void Vfp::TosiD()
903 VFP_FTOSID(CC_AL,0,1);
907 __NAKED__ void Vfp::TosiZD()
909 VFP_FTOSIZD(CC_AL,0,1);
913 __NAKED__ void Vfp::TosiS()
915 VFP_FTOSIS(CC_AL,0,2);
919 __NAKED__ void Vfp::TosiZS()
921 VFP_FTOSIZS(CC_AL,0,2);
925 __NAKED__ void Vfp::UitoD()
927 VFP_FUITOD(CC_AL,0,2);
931 __NAKED__ void Vfp::UitoS()
933 VFP_FUITOS(CC_AL,0,2);
937 __NAKED__ void Vfp::TouiD()
939 VFP_FTOUID(CC_AL,0,1);
943 __NAKED__ void Vfp::TouiZD()
945 VFP_FTOUIZD(CC_AL,0,1);
949 __NAKED__ void Vfp::TouiS()
951 VFP_FTOUIS(CC_AL,0,2);
955 __NAKED__ void Vfp::TouiZS()
957 VFP_FTOUIZS(CC_AL,0,2);
962 __NAKED__ void Vfp::ToFixedS(TInt /*aBits*/)
965 asm("addls pc, pc, r0, lsl #3 ");
967 VFP_VCT_S32_F32(CC_AL,0,0);
969 VFP_VCT_S32_F32(CC_AL,0,1);
971 VFP_VCT_S32_F32(CC_AL,0,2);
973 VFP_VCT_S32_F32(CC_AL,0,3);
975 VFP_VCT_S32_F32(CC_AL,0,4);
977 VFP_VCT_S32_F32(CC_AL,0,5);
979 VFP_VCT_S32_F32(CC_AL,0,6);
981 VFP_VCT_S32_F32(CC_AL,0,7);
983 VFP_VCT_S32_F32(CC_AL,0,8);
985 VFP_VCT_S32_F32(CC_AL,0,9);
987 VFP_VCT_S32_F32(CC_AL,0,10);
989 VFP_VCT_S32_F32(CC_AL,0,11);
991 VFP_VCT_S32_F32(CC_AL,0,12);
993 VFP_VCT_S32_F32(CC_AL,0,13);
995 VFP_VCT_S32_F32(CC_AL,0,14);
997 VFP_VCT_S32_F32(CC_AL,0,15);
1001 __NAKED__ void Vfp::FromFixedS(TInt /*aBits*/)
1003 asm("cmp r0, #15 ");
1004 asm("addls pc, pc, r0, lsl #3 ");
1006 VFP_VCT_F32_S32(CC_AL,0,0);
1008 VFP_VCT_F32_S32(CC_AL,0,1);
1010 VFP_VCT_F32_S32(CC_AL,0,2);
1012 VFP_VCT_F32_S32(CC_AL,0,3);
1014 VFP_VCT_F32_S32(CC_AL,0,4);
1016 VFP_VCT_F32_S32(CC_AL,0,5);
1018 VFP_VCT_F32_S32(CC_AL,0,6);
1020 VFP_VCT_F32_S32(CC_AL,0,7);
1022 VFP_VCT_F32_S32(CC_AL,0,8);
1024 VFP_VCT_F32_S32(CC_AL,0,9);
1026 VFP_VCT_F32_S32(CC_AL,0,10);
1028 VFP_VCT_F32_S32(CC_AL,0,11);
1030 VFP_VCT_F32_S32(CC_AL,0,12);
1032 VFP_VCT_F32_S32(CC_AL,0,13);
1034 VFP_VCT_F32_S32(CC_AL,0,14);
1036 VFP_VCT_F32_S32(CC_AL,0,15);
1042 __NAKED__ void Vfp::TconstS2()
1045 VFP_VMOV_IMM(CC_AL,0,0,0);
1050 __NAKED__ void Vfp::TconstD2()
1053 VFP_VMOV_IMM(CC_AL,1,0,0);
1058 __NAKED__ void Vfp::TconstS2_8()
1061 VFP_VMOV_IMM(CC_AL,0,0,0x7);
1066 __NAKED__ void Vfp::TconstD2_8()
1069 VFP_VMOV_IMM(CC_AL,1,0,0x7);
1075 // Neon test instructions
1077 __NAKED__ TInt NeonWithF2(TAny*)
1080 // VEXT.8 D0, D1, D2, #3
1081 asm(".word 0xF2B10302 ");
1086 __NAKED__ TInt NeonWithF3(TAny*)
1090 asm(".word 0xF3B50C01 ");
1095 __NAKED__ TInt NeonWithF4x(TAny*)
1098 // VLD1.8 {D0[1]}, r2
1099 asm(".word 0xF4E2002F ");
1103 asm(".word 0x12345678" );
1106 __NAKED__ TInt ThumbMode(TAny*)
1108 #if defined(__SUPPORT_THUMB_INTERWORKING)
1109 asm("adr r2, 1f "); // Store a test value address
1111 asm("mov r1, #1 "); // r1 = 1
1112 asm("add r1, r0, lsl #3 "); // Add the arg * 8 to r1
1114 asm("mov r0, #0 "); // Store a return value of KErrNone
1116 asm("add r1, pc, r1 "); // Add pc to get jump destination
1117 asm("bx r1 "); // Switch to thumb mode
1120 // Thumb mode so halfwords reversed
1121 asm(".word 0x0A10EC41 "); // VMOV S0, S1, r0, r1
1124 asm(".word 0x0B00ED12 "); // VLDR D0, [r2]
1127 asm(".word 0x8A00EE30 "); // VADD.32 S0, S0, S0
1130 asm(".word 0x0302EFB1 "); // VEXT.8 D0, D1, D2, #3
1133 asm(".word 0x002FF9E2 "); // VLD1.8 {D0[1]}, r2
1136 asm(".word 0x0C01FFB5 "); // VDUP.8 D0, D1[2]
1140 asm("mov r0, #1 "); // Change ret to "done"
1145 asm(".word 0x12345678" );
1148 #endif // __TEST_VFPV3