3 ; Copyright (c) 1998-2001 Symbian Ltd. All rights reserved.
5 ; Template bootstrap configuration file
7 ; Include to enable tracing
8 ; GBLL CFG_DebugBootRom
10 ; Include one of these to select the CPU
11 ; GBLL CFG_CPU_GENERIC_ARM4
12 ; GBLL CFG_CPU_ARM710T
13 ; GBLL CFG_CPU_ARM720T
15 ; GBLL CFG_CPU_ARM920T
16 ; GBLL CFG_CPU_ARM925T
17 ; GBLL CFG_CPU_ARM926J
19 ; GBLL CFG_CPU_ARM1136
23 ; Include the following line if this is a bootloader bootstrap
26 ; The following line needs to be removed for target hardware
29 ; If you want to supply a custom set of initial vectors (including reset vector) include the following line
30 ; GBLL CFG_CustomVectors
32 ; and provide a custom_vectors.inc file
34 ; Variant Number, just an example:
35 INIT_NUMERIC_CONSTANT CFG_HWVD, 0x09080001
37 ; On ARM architecture 6 processors, include the following line to override the threshold
38 ; on total physical RAM size at which the multiple memory model switches into large address space mode
39 ; i.e. size>threshold -> 2Gb per process, size<=threshold -> 1Gb per process
41 ; INIT_NUMERIC_CONSTANT CFG_ARMV6_LARGE_CONFIG_THRESHOLD, <value>
43 ; For the direct memory model only, include the following line if you wish the exception vectors at the
44 ; start of the bootstrap to be used at all times. This is only relevant if an MMU is present - this option
45 ; is mandatory if not.
46 ; GBLL CFG_UseBootstrapVectors
48 ; If the above option is in use (including if no MMU is present) the following symbol should be defined
49 ; to specify the offset from the bootstrap to the kernel image.
50 INIT_NUMERIC_CONSTANT KernelCodeOffset, 0x4000
52 ; Include the following line if you wish to include the ROM autodetection code based on data bus
53 ; capacitance and image repeats.
54 ; GBLL CFG_AutoDetectROM
56 ; Include the following line to minimise the initial kernel heap size
57 ; On the direct memory model the size of the kernel data area (super page to end of kernel heap)
58 ; is rounded up to the next 1Mb if this is not included, 4K if it is.
59 ; On the moving and multiple models, the size of the initial kernel heap area is rounded up to
60 ; the next 64K if this is not included, 4K if it is.
61 ; GBLL CFG_MinimiseKernelHeap
63 ; Include the following line if default memory mapping should use shared memory.
64 ; Should be defined on multicore (SMP) devices.
65 ; GBLL CFG_USE_SHARED_MEMORY
67 ; On the moving or multiple memory models, include either or both of the following lines to
68 ; specify the size of the initial kernel heap
69 ; INIT_NUMERIC_CONSTANT CFG_KernelHeapMultiplier, <multiplier>
70 ; INIT_NUMERIC_CONSTANT CFG_KernelHeapBaseSize, <base>
72 ; The initial kernel heap size is MAX( <base> + <multiplier> * N / 16, value specified in ROMBUILD )
73 ; where N is the total physical RAM size in pages.
74 ; <base> defaults to 24K and <multiplier> defaults to 9*16 (ie 9 bytes per page).
76 ; Uncomment if using ARM1136 processor and ARM1136 Erratum 353494
77 ; "Rare conditions can cause corruption of the Instruction Cache"
78 ; is fixed on this hardware.
80 ; NOTE: The boot table should use this macro to determine whether RONO or RORO permissions
81 ; are used for the exception vectors. If the erratum is not fixed, RORO must be used.
83 ; GBLL CFG_CPU_ARM1136_ERRATUM_353494_FIXED
85 ; Uncomment if using ARM1136 processor and ARM1136 Erratum 364296
86 ; "Possible Cache Data Corruption with Hit-Under-Miss"
87 ; is fixed on this hardware.
89 ; GBLL CFG_CPU_ARM1136_ERRATUM_364296_FIXED
91 ; Uncomment if using ARM1136 processor and ARM1136 Erratum 399234
92 ; "Write back data cache entry evicted by write through entry causes data corruption"
93 ; is fixed on this hardware.
95 ; The erratum may be avoided by marking all cacheable memory as one of write through or write back.
96 ; This requires the memory attributes described in the translation tables to be modified by software
97 ; appropriately, or the use of the remapping capability to remap write through regions to non cacheable.
99 ; If this macro is enabled, it should be accompanied by:
100 ; "macro __CPU_ARM1136_ERRATUM_399234_FIXED" in variant.mmh
101 ; GBLL CFG_CPU_ARM1136_ERRATUM_399234_FIXED
105 ; 1) using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache
106 ; operation might fail to invalidate some lines if coincident with linefill"
107 ; is fixed on this hardware, or
108 ; 2) using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache
109 ; operation might fail to invalidate some lines if coincident with linefill
110 ; is fixed on this hardware.
112 ; 1) Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg.
113 ; 2) Replaces Invalidate ICache operation with the sequence defined in the errata document.
114 ; If this macro is enabled, it should be accompanied by:
115 ; "macro __CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh
117 ; GBLL CFG_CPU_ARM1136_ERRATUM_411920_FIXED
120 ; Uncomment if using ARM1136 processor and ARM1136 Erratum 415662: "Invalidate Instruction Cache by
121 ; Index might corrupt cache when used with background prefetch range" is fixed on this hardware.
123 ; Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg.
125 ; GBLL CFG_CPU_ARM1136_ERRATUM_415662_FIXED
129 ; These are deduced from the supplied configuration
133 ; CFG_WriteBufferPresent
136 ; CFG_AltDCachePresent
138 ; CFG_CacheWriteAllocate
139 ; CFG_CachePhysicalTag
140 ; CFG_CacheFlushByDataRead
141 ; CFG_CacheFlushByWaySetIndex
142 ; CFG_CacheFlushByLineAlloc
143 ; CFG_CachePolicyInPTE
145 ; CFG_SingleEntryDCacheFlush
146 ; CFG_SingleEntryICacheFlush
147 ; CFG_SingleEntryITLBFlush
148 ; CFG_SingleEntryTLBFlush
155 ; CFG_IncludeRAMAllocator