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os/kernelhwsrv/kerneltest/e32test/mmu/d_cache.cia
author sl@SLION-WIN7.fritz.box
Fri, 15 Jun 2012 03:10:57 +0200
changeset 0 bde4ae8d615e
permissions -rw-r--r--
First public contribution. 
     1 // Copyright (c) 2006-2009 Nokia Corporation and/or its subsidiary(-ies).

     2 // All rights reserved.

     3 // This component and the accompanying materials are made available

     4 // under the terms of the License "Eclipse Public License v1.0"

     5 // which accompanies this distribution, and is available

     6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".

     7 //

     8 // Initial Contributors:

     9 // Nokia Corporation - initial contribution.

    10 //

    11 // Contributors:

    12 //

    13 // Description:

    14 // e32test\mmu\d_cache.cia

    15 // See e32test\mmu\t_cache.cpp for details

    16 // 

    17 //

    18 

    19 

    20 #ifndef __KERNEL_MODE__

    21 #include <u32std.h>

    22 #else

    23 #include <u32std.h>

    24 #include "nk_cpu.h"

    25 

    26 

    27 #if defined(__CPU_ARMV7)

    28 /**Returns Cache Type Register content*/

    29 __NAKED__ TUint32 CacheTypeRegister()

    30 	{

    31 	asm("mrc p15, 0, r0, c0, c0, 1 ");

    32 	__JUMP(,lr);

    33 	}

    34 

    35 /**Returns Cache Level ID Register content*/

    36 __NAKED__ TUint32 CacheLevelIDRegister()

    37 	{

    38 	asm("mrc p15, 1, r0, c0, c0, 1 ");

    39 	__JUMP(,lr);

    40 	}

    41 

    42 /**

    43 Returns Cache Size Id Register content for the given cache level/type

    44 @param aType 	Cache type: 	0=data/unified, 1=code

    45 @param aLevel 	Cache level: 	0=Level1 ... 7=Level8

    46 */

    47 __NAKED__ TUint32 CacheSizeIdRegister(TUint32 /*aType*/, TUint32 /*aLevel*/)

    48 	{

    49 	asm("orr r0, r1, lsl #1");  		// r0 = entry for Cache Size Selection Reg.

    50 	asm("mcr p15, 2, r0, c0, c0, 0 ");  // set Cache Size Selection Register

    51 	ARM_ISBSY;

    52     asm("mrc p15, 1, r0, c0, c0, 0 ");  // read Cache Size Id Register

    53     __JUMP(,lr);

    54 	}

    55 #endif

    56 

    57 

    58 #if defined(__CPU_MEMORY_TYPE_REMAPPING)

    59 /** Returns Coprocessor Control Register*/

    60 __NAKED__ TUint32 CtrlRegister()

    61 	{

    62     asm("mrc p15, 0, r0, c1, c0, 0 ");//read CR reg.

    63     __JUMP(,lr);

    64 	}

    65 

    66 /** Returns PRRR Register*/

    67 __NAKED__ TUint32 PRRRRegister()

    68 	{

    69     asm("mrc p15, 0, r0, c10, c2, 0 ");

    70     __JUMP(,lr);

    71 	}

    72 

    73 /** Returns NRRR Register*/

    74 __NAKED__ TUint32 NRRRRegister()

    75 	{

    76     asm("mrc p15, 0, r0, c10, c2, 1 ");

    77     __JUMP(,lr);

    78 	}

    79 

    80 /** Sets PRRR Register*/

    81 __NAKED__ void SetPRRR(TUint32)

    82 	{

    83     asm("mcr p15, 0, r0, c10, c2, 0 ");

    84 #if defined(__CPU_ARMV7)

    85 	UTLBIALL;

    86 	ARM_ISBSY;

    87 #else

    88 	FLUSH_DTLB(,r0);

    89 #endif

    90     __JUMP(,lr);

    91 	}

    92 

    93 /** Sets NRRR Register*/

    94 __NAKED__ void SetNRRR(TUint32)

    95 	{

    96     asm("mcr p15, 0, r0, c10, c2, 1 ");

    97     __JUMP(,lr);

    98 	}

    99 #endif

   100 

   101 

   102 

   103 #ifdef __CPU_HAS_CACHE_TYPE_REGISTER

   104 __NAKED__ TUint32 GetCacheType()

   105 	{

   106 	asm("mrc p15, 0, r0, c0, c0, 1 ");

   107 	__JUMP(,lr);

   108 	}

   109 #endif

   110 

   111 

   112 #ifdef __XSCALE_L2_CACHE__

   113 /**	Returns L2 Cache Type Register Content	*/

   114 __NAKED__ TUint32 L2CacheTypeReg()

   115 	{

   116 	asm("mrc p15, 1, r0, c0, c0, 1 ");

   117 	__JUMP(,lr);

   118 	}

   119 #endif	// __XSCALE_L2_CACHE__

   120 

   121 #define NOP_8()	\

   122 	asm("nop"); \

   123 	asm("nop"); \

   124 	asm("nop"); \

   125 	asm("nop"); \

   126 	asm("nop"); \

   127 	asm("nop"); \

   128 	asm("nop"); \

   129 	asm("nop"); \

   130 

   131 #define NOP_64()	\

   132 	NOP_8()	\

   133 	NOP_8()	\

   134 	NOP_8()	\

   135 	NOP_8()	\

   136 	NOP_8()	\

   137 	NOP_8()	\

   138 	NOP_8()	\

   139 	NOP_8()	\

   140 

   141 #define NOP_512()	\

   142 	NOP_64()	\

   143 	NOP_64()	\

   144 	NOP_64()	\

   145 	NOP_64()	\

   146 	NOP_64()	\

   147 	NOP_64()	\

   148 	NOP_64()	\

   149 	NOP_64()	\

   150 

   151 __NAKED__ void TestCodeFunc()

   152 	{

   153 	asm("testcodestart: ");

   154 	NOP_512(); 		//512 nops * 4 bytes/nop = 2K (800h) of code

   155 	__JUMP(,lr); 	//+ 4 bytes

   156 	asm("testcodeend: ");

   157 	}

   158 

   159 __NAKED__ TInt TestCodeFuncSize()

   160 	{

   161 	asm("ldr r0, = testcodeend - testcodestart"); //This should return 804h

   162 	__JUMP(,lr);

   163 	}

   164 

   165 #endif //#ifdef __KERNEL_MODE__

   166 

   167 // It assumes that aSize and aBase are aligned to 4 bytes. Also, aSize must be > 0.

   168 __NAKED__ void DataSegmetTestFunct(void* /*aBase*/, TInt /*aSize*/)

   169 	{

   170 	asm("add r1,r1,r0");	// r1 = end address (excluding)

   171 	asm("mov r2, #50");		// Will take 50 cycles

   172 	asm("mvn r12, #1");		// r12 = -2

   173 

   174 	asm("next_cycle:");

   175 

   176 	asm("mov r3, r0");		// r3 = aBase

   177 	asm("write_loop:");

   178 	asm("str r12, [r3],#4");

   179 

   180 	asm("cmp r3, r1");

   181 	asm("blo write_loop");

   182 

   183 	asm("mov r3, r0");		// r3 = aBase

   184 	asm("read_loop:");

   185 	asm("ldr r12, [r3],#4");

   186 	asm("cmp r3, r1");

   187 	asm("blo read_loop");

   188 

   189 	asm("subs r2,r2,#1");

   190 	asm("bne next_cycle");

   191 

   192 	__JUMP(,lr);

   193 	}
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