1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/kerneltest/e32test/mmu/d_cache.cia Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,193 @@
1.4 +// Copyright (c) 2006-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// e32test\mmu\d_cache.cia
1.18 +// See e32test\mmu\t_cache.cpp for details
1.19 +//
1.20 +//
1.21 +
1.22 +
1.23 +#ifndef __KERNEL_MODE__
1.24 +#include <u32std.h>
1.25 +#else
1.26 +#include <u32std.h>
1.27 +#include "nk_cpu.h"
1.28 +
1.29 +
1.30 +#if defined(__CPU_ARMV7)
1.31 +/**Returns Cache Type Register content*/
1.32 +__NAKED__ TUint32 CacheTypeRegister()
1.33 + {
1.34 + asm("mrc p15, 0, r0, c0, c0, 1 ");
1.35 + __JUMP(,lr);
1.36 + }
1.37 +
1.38 +/**Returns Cache Level ID Register content*/
1.39 +__NAKED__ TUint32 CacheLevelIDRegister()
1.40 + {
1.41 + asm("mrc p15, 1, r0, c0, c0, 1 ");
1.42 + __JUMP(,lr);
1.43 + }
1.44 +
1.45 +/**
1.46 +Returns Cache Size Id Register content for the given cache level/type
1.47 +@param aType Cache type: 0=data/unified, 1=code
1.48 +@param aLevel Cache level: 0=Level1 ... 7=Level8
1.49 +*/
1.50 +__NAKED__ TUint32 CacheSizeIdRegister(TUint32 /*aType*/, TUint32 /*aLevel*/)
1.51 + {
1.52 + asm("orr r0, r1, lsl #1"); // r0 = entry for Cache Size Selection Reg.
1.53 + asm("mcr p15, 2, r0, c0, c0, 0 "); // set Cache Size Selection Register
1.54 + ARM_ISBSY;
1.55 + asm("mrc p15, 1, r0, c0, c0, 0 "); // read Cache Size Id Register
1.56 + __JUMP(,lr);
1.57 + }
1.58 +#endif
1.59 +
1.60 +
1.61 +#if defined(__CPU_MEMORY_TYPE_REMAPPING)
1.62 +/** Returns Coprocessor Control Register*/
1.63 +__NAKED__ TUint32 CtrlRegister()
1.64 + {
1.65 + asm("mrc p15, 0, r0, c1, c0, 0 ");//read CR reg.
1.66 + __JUMP(,lr);
1.67 + }
1.68 +
1.69 +/** Returns PRRR Register*/
1.70 +__NAKED__ TUint32 PRRRRegister()
1.71 + {
1.72 + asm("mrc p15, 0, r0, c10, c2, 0 ");
1.73 + __JUMP(,lr);
1.74 + }
1.75 +
1.76 +/** Returns NRRR Register*/
1.77 +__NAKED__ TUint32 NRRRRegister()
1.78 + {
1.79 + asm("mrc p15, 0, r0, c10, c2, 1 ");
1.80 + __JUMP(,lr);
1.81 + }
1.82 +
1.83 +/** Sets PRRR Register*/
1.84 +__NAKED__ void SetPRRR(TUint32)
1.85 + {
1.86 + asm("mcr p15, 0, r0, c10, c2, 0 ");
1.87 +#if defined(__CPU_ARMV7)
1.88 + UTLBIALL;
1.89 + ARM_ISBSY;
1.90 +#else
1.91 + FLUSH_DTLB(,r0);
1.92 +#endif
1.93 + __JUMP(,lr);
1.94 + }
1.95 +
1.96 +/** Sets NRRR Register*/
1.97 +__NAKED__ void SetNRRR(TUint32)
1.98 + {
1.99 + asm("mcr p15, 0, r0, c10, c2, 1 ");
1.100 + __JUMP(,lr);
1.101 + }
1.102 +#endif
1.103 +
1.104 +
1.105 +
1.106 +#ifdef __CPU_HAS_CACHE_TYPE_REGISTER
1.107 +__NAKED__ TUint32 GetCacheType()
1.108 + {
1.109 + asm("mrc p15, 0, r0, c0, c0, 1 ");
1.110 + __JUMP(,lr);
1.111 + }
1.112 +#endif
1.113 +
1.114 +
1.115 +#ifdef __XSCALE_L2_CACHE__
1.116 +/** Returns L2 Cache Type Register Content */
1.117 +__NAKED__ TUint32 L2CacheTypeReg()
1.118 + {
1.119 + asm("mrc p15, 1, r0, c0, c0, 1 ");
1.120 + __JUMP(,lr);
1.121 + }
1.122 +#endif // __XSCALE_L2_CACHE__
1.123 +
1.124 +#define NOP_8() \
1.125 + asm("nop"); \
1.126 + asm("nop"); \
1.127 + asm("nop"); \
1.128 + asm("nop"); \
1.129 + asm("nop"); \
1.130 + asm("nop"); \
1.131 + asm("nop"); \
1.132 + asm("nop"); \
1.133 +
1.134 +#define NOP_64() \
1.135 + NOP_8() \
1.136 + NOP_8() \
1.137 + NOP_8() \
1.138 + NOP_8() \
1.139 + NOP_8() \
1.140 + NOP_8() \
1.141 + NOP_8() \
1.142 + NOP_8() \
1.143 +
1.144 +#define NOP_512() \
1.145 + NOP_64() \
1.146 + NOP_64() \
1.147 + NOP_64() \
1.148 + NOP_64() \
1.149 + NOP_64() \
1.150 + NOP_64() \
1.151 + NOP_64() \
1.152 + NOP_64() \
1.153 +
1.154 +__NAKED__ void TestCodeFunc()
1.155 + {
1.156 + asm("testcodestart: ");
1.157 + NOP_512(); //512 nops * 4 bytes/nop = 2K (800h) of code
1.158 + __JUMP(,lr); //+ 4 bytes
1.159 + asm("testcodeend: ");
1.160 + }
1.161 +
1.162 +__NAKED__ TInt TestCodeFuncSize()
1.163 + {
1.164 + asm("ldr r0, = testcodeend - testcodestart"); //This should return 804h
1.165 + __JUMP(,lr);
1.166 + }
1.167 +
1.168 +#endif //#ifdef __KERNEL_MODE__
1.169 +
1.170 +// It assumes that aSize and aBase are aligned to 4 bytes. Also, aSize must be > 0.
1.171 +__NAKED__ void DataSegmetTestFunct(void* /*aBase*/, TInt /*aSize*/)
1.172 + {
1.173 + asm("add r1,r1,r0"); // r1 = end address (excluding)
1.174 + asm("mov r2, #50"); // Will take 50 cycles
1.175 + asm("mvn r12, #1"); // r12 = -2
1.176 +
1.177 + asm("next_cycle:");
1.178 +
1.179 + asm("mov r3, r0"); // r3 = aBase
1.180 + asm("write_loop:");
1.181 + asm("str r12, [r3],#4");
1.182 +
1.183 + asm("cmp r3, r1");
1.184 + asm("blo write_loop");
1.185 +
1.186 + asm("mov r3, r0"); // r3 = aBase
1.187 + asm("read_loop:");
1.188 + asm("ldr r12, [r3],#4");
1.189 + asm("cmp r3, r1");
1.190 + asm("blo read_loop");
1.191 +
1.192 + asm("subs r2,r2,#1");
1.193 + asm("bne next_cycle");
1.194 +
1.195 + __JUMP(,lr);
1.196 + }