1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
2 // All rights reserved.
3 // This component and the accompanying materials are made available
4 // under the terms of the License "Eclipse Public License v1.0"
5 // which accompanies this distribution, and is available
6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".
8 // Initial Contributors:
9 // Nokia Corporation - initial contribution.
14 // e32\include\nkernsmp\arm\ncern.h
16 // WARNING: This file contains some APIs which are internal and are subject
17 // to change without notice. Such APIs should therefore not be used
18 // outside the Kernel and Hardware Services package.
30 #ifdef __FIQ_IS_UNCONTROLLED__
31 #define __ASM_CLI() CPSIDI /* Disable all interrupts */
32 #define __ASM_STI() CPSIEI /* Enable all interrupts */
33 #define __ASM_CLI1() CPSIDI /* Disable IRQ only */
34 #define __ASM_STI1() CPSIEI /* Enable IRQ only */
35 #define __ASM_CLI2() /* Disable FIQ only */
36 #define __ASM_STI2() /* Enable FIQ only */
38 #define __ASM_CLI_MODE(mode) CPSIDIM(mode) /* Disable all interrupts and change mode */
39 #define __ASM_STI_MODE(mode) CPSIEIM(mode) /* Enable all interrupts and change mode */
40 #define __ASM_CLI1_MODE(mode) CPSIDIM(mode) /* Disable IRQ only and change mode */
41 #define __ASM_STI1_MODE(mode) CPSIEIM(mode) /* Enable IRQ only and change mode */
42 #define __ASM_CLI2_MODE(mode) CPSCHM(mode) /* Disable FIQ only and change mode */
43 #define __ASM_STI2_MODE(mode) CPSCHM(mode) /* Enable FIQ only and change mode */
46 #define __ASM_CLI() CPSIDIF /* Disable all interrupts */
47 #define __ASM_STI() CPSIEIF /* Enable all interrupts */
48 #define __ASM_CLI1() CPSIDI /* Disable IRQ only */
49 #define __ASM_STI1() CPSIEI /* Enable IRQ only */
50 #define __ASM_CLI2() CPSIDF /* Disable FIQ only */
51 #define __ASM_STI2() CPSIEF /* Enable FIQ only */
53 #define __ASM_CLI_MODE(mode) CPSIDIFM(mode) /* Disable all interrupts and change mode */
54 #define __ASM_STI_MODE(mode) CPSIEIFM(mode) /* Enable all interrupts and change mode */
55 #define __ASM_CLI1_MODE(mode) CPSIDIM(mode) /* Disable IRQ only and change mode */
56 #define __ASM_STI1_MODE(mode) CPSIEIM(mode) /* Enable IRQ only and change mode */
57 #define __ASM_CLI2_MODE(mode) CPSIDFM(mode) /* Disable FIQ only and change mode */
58 #define __ASM_STI2_MODE(mode) CPSIEFM(mode) /* Enable FIQ only and change mode */
61 /** Information needed to boot an AP (ARM specific)
65 struct SArmAPBootInfo : public SAPBootInfo
67 TLinAddr iAPBootLin; // linear address of AP boot page (uncached)
68 T_UintPtr iAPBootPhys; // physical address of AP boot page (uncached)
69 TLinAddr iAPBootCodeLin; // linear address of AP boot code (part of bootstrap)
70 T_UintPtr iAPBootCodePhys; // physical address of AP boot code (part of bootstrap)
71 T_UintPtr iAPBootPageDirPhys; // physical address of AP boot page directory
72 TLinAddr iInitR13Fiq; // initial value for R13_fiq
73 TLinAddr iInitR13Irq; // initial value for R13_irq
74 TLinAddr iInitR13Abt; // initial value for R13_abt
75 TLinAddr iInitR13Und; // initial value for R13_und
79 /** Timer frequency specification
81 Stores a frequency as a fraction of a (separately stored) maximum.
82 The frequency must be at least 1/256 of the maximum.
89 TUint32 iFreq; // frequency as a fraction of maximum possible, multiplied by 2^32
90 TUint32 iInverse; // 2^24/(iFreq/2^32) = 2^56/iFreq
93 /** Variant interface block
97 struct SVariantInterfaceBlock : public SInterfaceBlockBase
99 TUint64 iMaxCpuClock; // maximum possible CPU clock frequency on this system
102 TUint32 iMaxTimerClock; // maximum possible local timer clock frequency
103 TLinAddr iScuAddr; // address of SCU
104 TLinAddr iGicDistAddr; // address of GIC Distributor
105 TLinAddr iGicCpuIfcAddr; // address of GIC CPU interface (must be same for all CPUs)
106 TLinAddr iLocalTimerAddr; // address of per-CPU timer (must be same for all CPUs)
107 volatile STimerMult* iTimerMult[KMaxCpus]; // timer[i] frequency / iMaxTimerClock * 2^32
108 volatile TUint32* iCpuMult[KMaxCpus]; // CPU[i] frequency / iMaxCpuClock * 2^32