1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/kerneltest/e32test/iic/t_iic.h Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,435 @@
1.4 +// Copyright (c) 1995-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// e32test\iic\t_iic.h
1.18 +//
1.19 +
1.20 +#ifndef __T_IIC_H__
1.21 +#define __T_IIC_H__
1.22 +
1.23 +#include <e32ver.h>
1.24 +
1.25 +const TInt KIicClientMajorVersionNumber = 1;
1.26 +const TInt KIicClientMinorVersionNumber = 0;
1.27 +const TInt KIicClientBuildVersionNumber = KE32BuildVersionNumber;
1.28 +
1.29 +const TInt KPriorityTestNum = 6; // 1 blocking transaction + 5 test transactions
1.30 +
1.31 +// For IIC,
1.32 +// If bit 31 is set and bit 30 cleared it is used to extend the Master-Slave channel;
1.33 +// if bit 31 is cleared and bit 30 is set, it extends the Master channel;
1.34 +// if both bits 31 and 30 are cleared it extends the Slave channel interface.
1.35 +// However,
1.36 +// since the kernel-side proxy clients interpret the msb being set as indicative of an
1.37 +// asynchronous request, the values here will have the static extension pattern represented
1.38 +// in bits 30 and 29, instead. In addition, to support communication with the slave-side proxy,
1.39 +// the Slave extension value will be represented as bits 30 and 29 set, so that it can be distinguished
1.40 +// from 'normal' synchronous operations.
1.41 +//
1.42 +const TUint KTestControlIoMask = 0x60000000;
1.43 +const TUint KTestMasterControlIo = 0x20000000;
1.44 +const TUint KTestSlaveControlIo = 0x60000000;
1.45 +const TUint KTestMasterSlaveControlIo = 0x40000000;
1.46 +const TUint KTestControlIoPilOffset = 0x00000002; // Corresponds to 1 higher than the number used by PIL
1.47 +const TUint KTestControlUnitTestOffset = 0x10000000;
1.48 +
1.49 +//
1.50 +// Enumerations TReqType and TBusType defined in kernel-side class TIicBusTransfer
1.51 +// The user-side test, and the kernel-side proxy client require access to this
1.52 +enum TReqType
1.53 + {
1.54 + EMasterRead,
1.55 + EMasterWrite
1.56 + };
1.57 +enum TBusType
1.58 + {
1.59 + EI2c = 0,
1.60 + ESpi = 0x01,
1.61 + EMicrowire = 0x02,
1.62 + ECci = 0x03,
1.63 + ESccb = 0x04,
1.64 + EInvalidBus
1.65 + };
1.66 +
1.67 +#define MAX_TRANS_LENGTH 20
1.68 +
1.69 +
1.70 +#ifndef __KERNEL_MODE__
1.71 +//
1.72 +// For convenience, selected kernel-side information is replicated here
1.73 +// to allow the user-side test to populate buffers accordingly
1.74 +//
1.75 +// Bus-specific configuration
1.76 +//
1.77 +enum TEndianness
1.78 + {
1.79 + EBigEndian,
1.80 + ELittleEndian
1.81 + };
1.82 +
1.83 +enum TBitOrder
1.84 + {
1.85 + ELsbFirst,
1.86 + EMsbFirst
1.87 + };
1.88 +
1.89 +//
1.90 +// Bus-specific configuration for SPI bus
1.91 +//
1.92 +
1.93 +enum TSpiWordWidth
1.94 + {
1.95 + ESpiWordWidth_8,
1.96 + ESpiWordWidth_10,
1.97 + ESpiWordWidth_12,
1.98 + ESpiWordWidth_16
1.99 + };
1.100 +
1.101 +enum TSpiClkMode
1.102 + {
1.103 + ESpiPolarityLowRisingEdge, // Active high, odd edges
1.104 + ESpiPolarityLowFallingEdge, // Active high, even edges
1.105 + ESpiPolarityHighFallingEdge, // Active low, odd edges
1.106 + ESpiPolarityHighRisingEdge // Active low, even edges
1.107 + };
1.108 +
1.109 +enum TSpiSsPinMode
1.110 + {
1.111 + ESpiCSPinActiveLow, // Active low
1.112 + ESpiCSPinActiveHigh // Active high
1.113 + };
1.114 +
1.115 +class TConfigSpiV01
1.116 + {
1.117 +public:
1.118 + TSpiWordWidth iWordWidth;
1.119 + TInt32 iClkSpeedHz;
1.120 + TSpiClkMode iClkMode;
1.121 + TInt32 iTimeoutPeriod;
1.122 + TEndianness iEndianness;
1.123 + TBitOrder iBitOrder;
1.124 + TUint iTransactionWaitCycles;
1.125 + TSpiSsPinMode iSSPinActiveMode;
1.126 + };
1.127 +
1.128 +typedef TPckgBuf <TConfigSpiV01> TConfigSpiBufV01;
1.129 +
1.130 +
1.131 +//
1.132 +// Bus-specific configuration for I2C bus
1.133 +//
1.134 +
1.135 +enum TI2cAddrType
1.136 + {
1.137 + EI2cAddr7Bit,
1.138 + EI2cAddr10Bit
1.139 + };
1.140 +
1.141 +class TConfigI2cV01
1.142 + {
1.143 + public:
1.144 + TI2cAddrType iAddrType; // 7 or 10-bit addressing
1.145 + TInt32 iClkSpeedHz;
1.146 + TEndianness iEndianness;
1.147 + TInt32 iTimeoutPeriod;
1.148 + };
1.149 +
1.150 +typedef TPckgBuf <TConfigI2cV01> TConfigI2cBufV01;
1.151 +
1.152 +
1.153 +inline static TInt CreateSpiBuf(TConfigSpiBufV01*& aBuf,
1.154 + TSpiWordWidth aWordWidth,
1.155 + TInt32 aClkSpeedHz,
1.156 + TSpiClkMode aClkMode,
1.157 + TInt32 aTimeoutPeriod,
1.158 + TEndianness aEndianness,
1.159 + TBitOrder aBitOrder,
1.160 + TUint aTransactionWaitCycles,
1.161 + TSpiSsPinMode aSSPinActiveMode)
1.162 +// Utility function to create a buffer for the SPI bus
1.163 + {
1.164 + aBuf = new TConfigSpiBufV01();
1.165 + if(aBuf==NULL)
1.166 + return KErrNoMemory;
1.167 + TConfigSpiV01 *buf = &((*aBuf)());
1.168 + buf->iWordWidth = aWordWidth;
1.169 + buf->iClkSpeedHz = aClkSpeedHz;
1.170 + buf->iClkMode = aClkMode;
1.171 + buf->iTimeoutPeriod = aTimeoutPeriod;
1.172 + buf->iEndianness = aEndianness;
1.173 + buf->iBitOrder = aBitOrder;
1.174 + buf->iTransactionWaitCycles = aTransactionWaitCycles;
1.175 + buf->iSSPinActiveMode = aSSPinActiveMode;
1.176 + return KErrNone;
1.177 + }
1.178 +
1.179 +inline static TInt CreateI2cBuf(TConfigI2cBufV01*& aBuf,
1.180 + TI2cAddrType aAddrType,
1.181 + TInt32 aClkSpeedHz,
1.182 + TEndianness aEndianness,
1.183 + TInt32 aTimeoutPeriod)
1.184 +// Utility function to create a buffer for the I2C bus
1.185 + {
1.186 + aBuf = new TConfigI2cBufV01();
1.187 + if(aBuf==NULL)
1.188 + return KErrNoMemory;
1.189 + TConfigI2cV01 *buf = &((*aBuf)());
1.190 + buf->iAddrType = aAddrType;
1.191 + buf->iClkSpeedHz = aClkSpeedHz;
1.192 + buf->iEndianness = aEndianness;
1.193 + buf->iTimeoutPeriod = aTimeoutPeriod;
1.194 + return KErrNone;
1.195 + }
1.196 +
1.197 +//
1.198 +// Enumerations for channel type and channel duplex defined in kernel-side class DIicBusChannel
1.199 +// duplicated for temporary test
1.200 +enum TChannelType
1.201 + {
1.202 + EMaster = 0,
1.203 + ESlave = 0x01,
1.204 + EMasterSlave = 0x02,
1.205 + EInvalidType
1.206 + };
1.207 +enum TChannelDuplex
1.208 + {
1.209 + EHalfDuplex = 0, // supports only half duplex transactions (even if bus spec supports full duplex)
1.210 + EFullDuplex = 0x1, // supports full duplex transactions (queud transactions may still be half duplex)
1.211 + EInvalidDuplex
1.212 + };
1.213 +//
1.214 +// Bus realisation configuration
1.215 +//
1.216 +// 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0
1.217 +//
1.218 +// 31:29 - HS Master address (I2C only)
1.219 +// 28 - HS address valid bit
1.220 +// 27:23 - Reserved
1.221 +// 22:20 - Bus type
1.222 +// 19:15 - Channel number
1.223 +// 14:10 - Transaction speed
1.224 +// 9:0 - Slave address
1.225 +#define HS_MASTER_ADDR_SHIFT 29
1.226 +#define HS_MASTER_ADDR_MASK 0x7
1.227 +#define HS_ADDR_VALID_SHIFT 28
1.228 +#define HS_ADDR_VALID_MASK 0x1
1.229 +#define BUS_TYPE_SHIFT 20
1.230 +#define BUS_TYPE_MASK 0x7
1.231 +#define CHANNEL_NO_SHIFT 15
1.232 +#define CHANNEL_NO_MASK 0x1F
1.233 +#define TRANS_SPEED_SHIFT 10
1.234 +#define TRANS_SPEED_MASK 0x1F
1.235 +#define SLAVE_ADDR_SHIFT 0
1.236 +#define SLAVE_ADDR_MASK 0x3FF
1.237 +//
1.238 +// Macros to access fields within Bus Realisation Configuration data, used on a per-transaction basis with IIC
1.239 +#define SET_CONFIG_FIELD(aBusId,aField,aMask,aShift) aBusId=(aBusId&~(aMask<<aShift))|((aField&aMask)<<aShift);
1.240 +#define GET_CONFIG_FIELD(aBusId,aMask,aShift) (((aBusId)>>(aShift))&(aMask))
1.241 +
1.242 +#define GET_HS_MASTER_ADDR(aBusId) GET_CONFIG_FIELD(aBusId,HS_MASTER_ADDR_MASK,HS_MASTER_ADDR_SHIFT)
1.243 +#define SET_HS_MASTER_ADDR(aBusId,aHsMasterAddr) SET_CONFIG_FIELD(aBusId,aHsMasterAddr,HS_MASTER_ADDR_MASK,HS_MASTER_ADDR_SHIFT)
1.244 +#define GET_HS_VALID(aBusId) GET_CONFIG_FIELD(aBusId,HS_ADDR_VALID_MASK,HS_ADDR_VALID_SHIFT)
1.245 +#define SET_HS_VALID(aBusId,aHsValid) SET_CONFIG_FIELD(aBusId,aHsValid,HS_ADDR_VALID_MASK,HS_ADDR_VALID_SHIFT)
1.246 +#define GET_BUS_TYPE(aBusId) GET_CONFIG_FIELD(aBusId,BUS_TYPE_MASK,BUS_TYPE_SHIFT)
1.247 +#define SET_BUS_TYPE(aBusId,aBusType) SET_CONFIG_FIELD(aBusId,aBusType,BUS_TYPE_MASK,BUS_TYPE_SHIFT)
1.248 +#define GET_CHAN_NUM(aBusId) GET_CONFIG_FIELD(aBusId,CHANNEL_NO_MASK,CHANNEL_NO_SHIFT)
1.249 +#define SET_CHAN_NUM(aBusId,aChanNum) SET_CONFIG_FIELD(aBusId,aChanNum,CHANNEL_NO_MASK,CHANNEL_NO_SHIFT)
1.250 +#define SET_TRANS_SPEED(aBusId,aTransSpeed) SET_CONFIG_FIELD(aBusId,aTransSpeed,TRANS_SPEED_MASK,TRANS_SPEED_SHIFT)
1.251 +#define GET_TRANS_SPEED(aBusId) GET_CONFIG_FIELD(aBusId,TRANS_SPEED_MASK,TRANS_SPEED_SHIFT)
1.252 +#define SET_SLAVE_ADDR(aBusId,aSlaveAddr) SET_CONFIG_FIELD(aBusId,aSlaveAddr,SLAVE_ADDR_MASK,SLAVE_ADDR_SHIFT)
1.253 +#define GET_SLAVE_ADDR(aBusId) GET_CONFIG_FIELD(aBusId,SLAVE_ADDR_MASK,SLAVE_ADDR_SHIFT)
1.254 +
1.255 +static const TUint8 KTransactionWithPreamble = 0x80;
1.256 +static const TUint8 KTransactionWithMultiTransc = 0x40;
1.257 +
1.258 +enum TIicBusSlaveTrigger
1.259 + {
1.260 + ERxAllBytes = 0x01,
1.261 + ERxUnderrun = 0x02,
1.262 + ERxOverrun = 0x04,
1.263 + ETxAllBytes = 0x08,
1.264 + ETxUnderrun = 0x10,
1.265 + ETxOverrun = 0x20,
1.266 + EGeneralBusError = 0x40,
1.267 + EAsyncCaptChan = 0x80
1.268 + };
1.269 +
1.270 +#endif // #ifndef __KERNEL_MODE__
1.271 +
1.272 +//
1.273 +// User-Side abbreviation of kernel side classes TIicBusTransfer and TIicBusTransaction
1.274 +//
1.275 +struct TUsideTferDesc
1.276 + {
1.277 + TInt8 iType; // as one of TReqType
1.278 + TInt8 iBufGranularity; // width of a transfer word in bits
1.279 + TDes8* iBuffer; // the data for this transfer (packed into 8-bit words with padding)
1.280 + TUsideTferDesc* iNext;
1.281 + };
1.282 +
1.283 +struct TUsideTracnDesc
1.284 + {
1.285 + TBusType iType;
1.286 + TDes8* iHeader;
1.287 + TUsideTferDesc* iHalfDuplexTrans;
1.288 + TUsideTferDesc* iFullDuplexTrans;
1.289 + TUint8 iFlags; // used to indicate if it supports a preamble
1.290 + TAny* iPreambleArg; // used for preamble argument
1.291 + TAny* iMultiTranscArg; // used for multi transc argument
1.292 + };
1.293 +
1.294 +class RBusDevIicClient : public RBusLogicalChannel
1.295 + {
1.296 + public:
1.297 + enum TControl
1.298 + {
1.299 +// Master mode operations
1.300 + EQTransSync=1, /**< Queue Transaction (Synchronous version) */
1.301 +// Slave mode operations
1.302 + EInitSlaveClient, /**< Instigate Slave initialisation required to support testing */
1.303 + ECaptureChanSync, /**< Capture Channel (Synchronous version) */
1.304 + EReleaseChan, /**< ReleaseChannel */
1.305 + ERegisterRxBuffer, /**< Register a buffer for receiving data */
1.306 + ERegisterTxBuffer, /**< Register a buffer for transmitting data */
1.307 + ESetNotifTrigger /**< Set the notification triggers */
1.308 + };
1.309 +
1.310 + enum TStaticExt
1.311 + {
1.312 + ECtlIoNone = 0,
1.313 + ECtlIoDumpChan = 1, // KCtrlIoDumpChan - defined only for UDEB
1.314 +// ControlIO codes for Master follow
1.315 + ECtlIoBlockReqCompletion=(KTestMasterControlIo+KTestControlIoPilOffset),
1.316 + ECtlIoUnblockReqCompletion,
1.317 + ECtlIoDeRegChan,
1.318 + ECtlIoTracnOne,
1.319 + ECtlIoPriorityTest,
1.320 + EGetTestResult,
1.321 + ECtlIoSetTimeOutFlag,
1.322 + ECtlIoTestFullDuplexTrans,
1.323 +// ControlIO codes for Slave follow
1.324 + ECtrlIoRxWords=(KTestSlaveControlIo+KTestControlIoPilOffset),
1.325 + ECtrlIoTxWords,
1.326 + ECtrlIoRxTxWords,
1.327 + ECtrlIoTxChkBuf,
1.328 + ECtlIoBusError,
1.329 + ECtrlIoBlockNotification,
1.330 + ECtrlIoUnblockNotification,
1.331 + ECtrlIoUpdTimeout,
1.332 + ECtrlIoNotifNoTrigger
1.333 + };
1.334 +
1.335 + enum TTestFullDuplexTrans
1.336 + {
1.337 + ETestValidFullDuplexTrans=1,
1.338 + ETestInvalidFullDuplexTrans1,
1.339 + ETestInvalidFullDuplexTrans2,
1.340 + ETestLastNodeFullDuplexTrans,
1.341 + ETestDiffNodeNoFullDuplexTrans,
1.342 + ETestNone
1.343 + };
1.344 +
1.345 + enum TRequest
1.346 + {
1.347 +// Master mode operations
1.348 + EQTransAsync=1, /**< Queue Transaction (Asynchronous version) */
1.349 + ECtrlIoTestBufReUse,
1.350 +// Slave mode operations
1.351 + ECaptureChanAsync, /**< Capture Channel (Asynchronous version) */
1.352 + ECtrlIoOvUndRunRxTx
1.353 + };
1.354 +
1.355 + enum TTestMessages
1.356 + {
1.357 + ETestIicChannelInlineFunc=KTestControlUnitTestOffset
1.358 + };
1.359 +
1.360 +#ifndef __KERNEL_MODE__
1.361 + public:
1.362 + inline TInt TestIiicChannelInlineFunc(){return DoControl (ETestIicChannelInlineFunc, NULL, NULL);}
1.363 + // Master mode functions
1.364 + inline TInt Open(TDesC& aProxyName) {return (DoCreate(aProxyName,TVersion(KIicClientMajorVersionNumber,KIicClientMinorVersionNumber,KIicClientBuildVersionNumber),-1,NULL,NULL,EOwnerThread));}
1.365 +
1.366 + inline TInt QueueTransaction(TInt aBusId, TUsideTracnDesc* aTransaction) {return(DoControl(EQTransSync,(TAny*)aBusId,(TAny*)aTransaction));}
1.367 +
1.368 + inline void QueueTransaction(TRequestStatus& aStatus, TInt aBusId, TUsideTracnDesc* aTransaction) {DoRequest(EQTransAsync,aStatus,(TAny*)aBusId,(TAny*)aTransaction);}
1.369 +
1.370 + inline void CancelAsyncOperation(TRequestStatus* aStatus, TInt aBusId) {TInt* parms[2]; parms[0]=(TInt*)aStatus; parms[1]=(TInt*)aBusId;DoCancel((TInt)&parms[0]);}
1.371 +
1.372 + // Slave mode functions
1.373 + inline TInt InitSlaveClient() {return(DoControl(EInitSlaveClient,NULL,NULL));}
1.374 + inline TInt CaptureChannel(TInt aBusId, TDes8* aConfigHdr, TInt& aChannelId) {TInt* parms[2]; parms[0]=(TInt*)aBusId; parms[1]=&aChannelId;return(DoControl(ECaptureChanSync,(TAny*)aConfigHdr,(TAny*)(&parms[0])));}
1.375 +
1.376 + inline TInt CaptureChannel(TInt aBusId, TDes8* aConfigHdr, TInt& aChannelId, TRequestStatus& aStatus) {TInt* parms[2]; parms[0]=(TInt*)aBusId; parms[1]=&aChannelId;DoRequest(ECaptureChanAsync,aStatus,(TAny*)aConfigHdr,(TAny*)(&parms[0]));return KErrNone;}
1.377 +
1.378 + inline TInt ReleaseChannel(TInt aChannelId){return(DoControl(EReleaseChan,(TAny*)aChannelId,NULL));};
1.379 + inline TInt RegisterRxBuffer(TInt aChannelId, TInt8 aBufGranularity, TInt8 aNumWords, TInt8 aOffset){TInt8 parms[3]; parms[0]=aBufGranularity; parms[1]=aNumWords; parms[2]=aOffset;return(DoControl(ERegisterRxBuffer,(TAny*)aChannelId,(TAny*)(&parms[0])));};
1.380 + inline TInt RegisterTxBuffer(TInt aChannelId, TInt8 aBufGranularity, TInt8 aNumWords, TInt8 aOffset){TInt8 parms[3]; parms[0]=aBufGranularity; parms[1]=aNumWords; parms[2]=aOffset;return(DoControl(ERegisterTxBuffer,(TAny*)aChannelId,(TAny*)(&parms[0])));};
1.381 + inline TInt SetNotificationTrigger(TInt aChannelId, TInt aTrigger, TRequestStatus* aStatus){TInt parms[2]; parms[0]=aChannelId; parms[1]=aTrigger;return(DoControl(ESetNotifTrigger,(TAny*)aStatus,(TAny*)(&parms[0])));};
1.382 +
1.383 + // ControlIO functions follow
1.384 + inline TInt BlockReqCompletion(TInt aBusId) {return(DoControl(ECtlIoBlockReqCompletion,(TAny*)aBusId));}
1.385 + inline TInt UnblockReqCompletion(TInt aBusId) {return(DoControl(ECtlIoUnblockReqCompletion,(TAny*)aBusId));}
1.386 + inline TInt DeRegisterChan(TInt aBusId) {return(DoControl(ECtlIoDeRegChan,(TAny*)aBusId));}
1.387 + inline TInt TestTracnOne(TInt aBusId) {return(DoControl(ECtlIoTracnOne, (TAny*)aBusId));}
1.388 + inline TInt SetTimeOutFlag(TInt aBusId){return(DoControl(ECtlIoSetTimeOutFlag,(TAny*)aBusId));}
1.389 + inline TInt CancelTimeOutFlag(TInt aBusId){return(DoControl(ECtlIoNone,(TAny*)aBusId));}
1.390 + inline TInt TestPriority(TInt aBusId) {return(DoControl(ECtlIoPriorityTest, (TAny*)aBusId));}
1.391 +
1.392 + inline TInt TestValidFullDuplexTrans(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestValidFullDuplexTrans));}
1.393 + inline TInt TestInvalidFullDuplexTrans1(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestInvalidFullDuplexTrans1));}
1.394 + inline TInt TestInvalidFullDuplexTrans2(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestInvalidFullDuplexTrans2));}
1.395 +
1.396 + inline TInt TestLastNodeFullDuplexTrans(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestLastNodeFullDuplexTrans));}
1.397 + inline TInt TestDiffNodeNumFullDuplexTrans(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestDiffNodeNoFullDuplexTrans));}
1.398 +
1.399 + inline void TestBufferReUse(TInt aBusId, TRequestStatus& aStatus) {DoRequest(ECtrlIoTestBufReUse,aStatus,(TAny*)aBusId,NULL);}
1.400 +
1.401 + inline TInt SimulateRxNWords(TInt aBusId, TInt aChannelId, TInt aNumWords){TInt parms[2]; parms[0]=aChannelId; parms[1]=aNumWords;return(DoControl(ECtrlIoRxWords,(TAny*)aBusId,(TAny*)(&parms[0])));};
1.402 + inline TInt SimulateTxNWords(TInt aBusId, TInt aChannelId, TInt aNumWords){TInt parms[2]; parms[0]=aChannelId; parms[1]=aNumWords;return(DoControl(ECtrlIoTxWords,(TAny*)aBusId,(TAny*)(&parms[0])));};
1.403 + inline TInt SimulateRxTxNWords(TInt aBusId, TInt aChannelId, TInt aNumRxWords, TInt aNumTxWords){TInt parms[3]; parms[0]=aChannelId; parms[1]=aNumRxWords; parms[2]=aNumTxWords;return(DoControl(ECtrlIoRxTxWords,(TAny*)aBusId,(TAny*)(&parms[0])));};
1.404 + inline TInt SimulateBusErr(TInt aBusId, TInt aChannelId) {return(DoControl(ECtlIoBusError,(TAny*)aBusId,(TAny*)aChannelId));}
1.405 + inline TInt BlockNotification(TInt aBusId, TInt aChannelId) {return(DoControl(ECtrlIoBlockNotification,(TAny*)aBusId,(TAny*)aChannelId));}
1.406 + inline TInt UnblockNotification(TInt aBusId, TInt aChannelId) {return(DoControl(ECtrlIoUnblockNotification,(TAny*)aBusId,(TAny*)aChannelId));}
1.407 + inline TInt UpdateTimeoutValues(TInt aBusId, TInt aChannelId) {return(DoControl(ECtrlIoUpdTimeout,(TAny*)aBusId,(TAny*)aChannelId));}
1.408 + inline TInt SetNotifNoTrigger(TInt aChannelId, TInt aTrigger){return(DoControl(ECtrlIoNotifNoTrigger,(TAny*)aChannelId,(TAny*)aTrigger));};
1.409 +
1.410 + inline void TestOverrunUnderrun(TInt aBusId, TInt aChannelId, TRequestStatus& aStatus) {DoRequest(ECtrlIoOvUndRunRxTx,aStatus,(TAny*)aBusId,(TAny*)aChannelId);}
1.411 +
1.412 +#endif
1.413 + };
1.414 +
1.415 +
1.416 +#ifdef __KERNEL_MODE__
1.417 +
1.418 +// Definition of function prototype for a callback function provided by the PSL
1.419 +// to be invoked when the part played by the hardware in processing a transfer
1.420 +// has completed.
1.421 +typedef void (*THwDoneCbFn)(TAny* );
1.422 +
1.423 +#endif
1.424 +
1.425 +// Data used to support tests
1.426 +
1.427 +// Transaction One
1.428 +//
1.429 +const TUint8 KTransOneTferOne[21] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20};
1.430 +const TUint8 KTransOneTferTwo[8] = {17,18,19,20,21,22,23,24};
1.431 +const TUint8 KTransOneTferThree[6] = {87,85,83,81,79,77};
1.432 +const TUint8 KPriorityTestHeader[6] = {0,1,2,3,4,10};
1.433 +const TInt KPriorityTestPrio[6] = {1,2,3,4,5,0};
1.434 +
1.435 +const TInt KRxBufSizeInBytes = 64;
1.436 +const TInt KTxBufSizeInBytes = 64;
1.437 +
1.438 +#endif