os/kernelhwsrv/kernel/eka/memmodel/epoc/direct/arm/xsched.cia
changeset 0 bde4ae8d615e
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/os/kernelhwsrv/kernel/eka/memmodel/epoc/direct/arm/xsched.cia	Fri Jun 15 03:10:57 2012 +0200
     1.3 @@ -0,0 +1,72 @@
     1.4 +// Copyright (c) 1997-2009 Nokia Corporation and/or its subsidiary(-ies).
     1.5 +// All rights reserved.
     1.6 +// This component and the accompanying materials are made available
     1.7 +// under the terms of the License "Eclipse Public License v1.0"
     1.8 +// which accompanies this distribution, and is available
     1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
    1.10 +//
    1.11 +// Initial Contributors:
    1.12 +// Nokia Corporation - initial contribution.
    1.13 +//
    1.14 +// Contributors:
    1.15 +//
    1.16 +// Description:
    1.17 +// e32\memmodel\epoc\direct\arm\xsched.cia
    1.18 +// 
    1.19 +//
    1.20 +
    1.21 +#include <e32cia.h>
    1.22 +#include <arm_mem.h>
    1.23 +
    1.24 +#define iMState		iWaitLink.iSpare1
    1.25 +
    1.26 +#ifdef __SCHEDULER_MACHINE_CODED__
    1.27 +
    1.28 +#if defined(_DEBUG)
    1.29 +extern "C" void __DebugMsgRequestComplete(TInt a0, TInt a1, TInt a2);
    1.30 +extern "C" void __DebugMsgReqCompleteWrite(TInt a0, TInt a1, TInt a2);
    1.31 +#endif
    1.32 +
    1.33 +__NAKED__ void DThread::RequestComplete(TRequestStatus*& /*aStatus*/, TInt /*aReason*/)
    1.34 +//
    1.35 +// Signal this threads request semaphore.
    1.36 +//
    1.37 +	{
    1.38 +	ASM_DEBUG2(DThreadRequestComplete,r0,lr);
    1.39 +
    1.40 +	asm("ldr r3, [r1] ");					// r3 points to TRequestStatus
    1.41 +	asm("mov r12, #0 ");
    1.42 +	asm("str r12, [r1] ");					// aStatus=NULL
    1.43 +
    1.44 +	asm(".global _asm_RequestComplete ");
    1.45 +	asm("_asm_RequestComplete: ");
    1.46 +
    1.47 +#ifdef BTRACE_REQUESTS
    1.48 +	asm("stmdb sp!,{r0-r3,lr}");
    1.49 +	asm("mov r1,r3");
    1.50 +	asm("mov r3,r2");											// arg3 = aReason
    1.51 +	asm("mov r2,r1");											// arg2 = aStatus
    1.52 +	asm("add r1,r0,#%a0" : : "i" _FOFF(DThread,iNThread));		// arg1 = &this->iNThread
    1.53 +	asm("ldr r0,_threadReqequestCompleteTraceHeader");			// arg0 = header
    1.54 +	asm("bl " CSM_ZN6BTrace4OutXEmmmm);
    1.55 +	asm("ldmia sp!,{r0-r3,lr}");
    1.56 +#endif
    1.57 +
    1.58 +	ASM_DEBUG3(RequestComplete,r0,r3,r2);
    1.59 +	asm("ldrb r12, [r0, #%a0]" : : "i" _FOFF(DThread,iMState));
    1.60 +	asm("add r0, r0, #%a0" : : "i" _FOFF(DThread,iNThread));
    1.61 +	asm("cmp r12, #%a0" : : "i" (DThread::EDead));	// test if iMState=EDead
    1.62 +	asm("beq " CSM_ZN5NKern12UnlockSystemEv );		// if it is, finish
    1.63 +	asm("tst r3, #3 ");						// check address aligned
    1.64 +	asm("streq r2, [r3] ");					// if so, write completion code
    1.65 +	asm("moveq r1, #0 ");					// and signal thread
    1.66 +	asm("beq " CSM_ZN5NKern19ThreadRequestSignalEP7NThreadP10NFastMutex );
    1.67 +	asm("b " CSM_ZN5NKern12UnlockSystemEv ); // bad address, just finish.
    1.68 +#ifdef BTRACE_REQUESTS
    1.69 +	asm("_threadReqequestCompleteTraceHeader:");
    1.70 +	asm(".word %a0" : : "i" (BTRACE_HEADER_C(16,BTrace::ERequests,BTrace::ERequestComplete)));
    1.71 +#endif
    1.72 +	}
    1.73 +
    1.74 +#endif
    1.75 +