1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/bsptemplate/asspandvariant/template_variant/config.inc Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,157 @@
1.4 +; template\config.inc
1.5 +;
1.6 +; Copyright (c) 1998-2001 Symbian Ltd. All rights reserved.
1.7 +;
1.8 +; Template bootstrap configuration file
1.9 +
1.10 +; Include to enable tracing
1.11 +; GBLL CFG_DebugBootRom
1.12 +
1.13 +; Include one of these to select the CPU
1.14 +; GBLL CFG_CPU_GENERIC_ARM4
1.15 +; GBLL CFG_CPU_ARM710T
1.16 +; GBLL CFG_CPU_ARM720T
1.17 +; GBLL CFG_CPU_SA1
1.18 +; GBLL CFG_CPU_ARM920T
1.19 +; GBLL CFG_CPU_ARM925T
1.20 +; GBLL CFG_CPU_ARM926J
1.21 +; GBLL CFG_CPU_XSCALE
1.22 +; GBLL CFG_CPU_ARM1136
1.23 + GBLL CFG_CPU_ARM1176
1.24 +; GBLL CFG_CORTEX_A8
1.25 +
1.26 +; Include the following line if this is a bootloader bootstrap
1.27 +; GBLL CFG_BootLoader
1.28 +; TO DO:
1.29 +; The following line needs to be removed for target hardware
1.30 + GBLL CFG_Template
1.31 +
1.32 +; If you want to supply a custom set of initial vectors (including reset vector) include the following line
1.33 +; GBLL CFG_CustomVectors
1.34 +;
1.35 +; and provide a custom_vectors.inc file
1.36 +
1.37 +; Variant Number, just an example:
1.38 + INIT_NUMERIC_CONSTANT CFG_HWVD, 0x09080001
1.39 +
1.40 +; On ARM architecture 6 processors, include the following line to override the threshold
1.41 +; on total physical RAM size at which the multiple memory model switches into large address space mode
1.42 +; i.e. size>threshold -> 2Gb per process, size<=threshold -> 1Gb per process
1.43 +; Defaults to 32Mb.
1.44 +; INIT_NUMERIC_CONSTANT CFG_ARMV6_LARGE_CONFIG_THRESHOLD, <value>
1.45 +
1.46 +; For the direct memory model only, include the following line if you wish the exception vectors at the
1.47 +; start of the bootstrap to be used at all times. This is only relevant if an MMU is present - this option
1.48 +; is mandatory if not.
1.49 +; GBLL CFG_UseBootstrapVectors
1.50 +;
1.51 +; If the above option is in use (including if no MMU is present) the following symbol should be defined
1.52 +; to specify the offset from the bootstrap to the kernel image.
1.53 + INIT_NUMERIC_CONSTANT KernelCodeOffset, 0x4000
1.54 +
1.55 +; Include the following line if you wish to include the ROM autodetection code based on data bus
1.56 +; capacitance and image repeats.
1.57 +; GBLL CFG_AutoDetectROM
1.58 +
1.59 +; Include the following line to minimise the initial kernel heap size
1.60 +; On the direct memory model the size of the kernel data area (super page to end of kernel heap)
1.61 +; is rounded up to the next 1Mb if this is not included, 4K if it is.
1.62 +; On the moving and multiple models, the size of the initial kernel heap area is rounded up to
1.63 +; the next 64K if this is not included, 4K if it is.
1.64 +; GBLL CFG_MinimiseKernelHeap
1.65 +
1.66 +; Include the following line if default memory mapping should use shared memory.
1.67 +; Should be defined on multicore (SMP) devices.
1.68 +; GBLL CFG_USE_SHARED_MEMORY
1.69 +
1.70 +; On the moving or multiple memory models, include either or both of the following lines to
1.71 +; specify the size of the initial kernel heap
1.72 +; INIT_NUMERIC_CONSTANT CFG_KernelHeapMultiplier, <multiplier>
1.73 +; INIT_NUMERIC_CONSTANT CFG_KernelHeapBaseSize, <base>
1.74 +;
1.75 +; The initial kernel heap size is MAX( <base> + <multiplier> * N / 16, value specified in ROMBUILD )
1.76 +; where N is the total physical RAM size in pages.
1.77 +; <base> defaults to 24K and <multiplier> defaults to 9*16 (ie 9 bytes per page).
1.78 +
1.79 +; Uncomment if using ARM1136 processor and ARM1136 Erratum 353494
1.80 +; "Rare conditions can cause corruption of the Instruction Cache"
1.81 +; is fixed on this hardware.
1.82 +;
1.83 +; NOTE: The boot table should use this macro to determine whether RONO or RORO permissions
1.84 +; are used for the exception vectors. If the erratum is not fixed, RORO must be used.
1.85 +;
1.86 +; GBLL CFG_CPU_ARM1136_ERRATUM_353494_FIXED
1.87 +
1.88 +; Uncomment if using ARM1136 processor and ARM1136 Erratum 364296
1.89 +; "Possible Cache Data Corruption with Hit-Under-Miss"
1.90 +; is fixed on this hardware.
1.91 +;
1.92 +; GBLL CFG_CPU_ARM1136_ERRATUM_364296_FIXED
1.93 +
1.94 +; Uncomment if using ARM1136 processor and ARM1136 Erratum 399234
1.95 +; "Write back data cache entry evicted by write through entry causes data corruption"
1.96 +; is fixed on this hardware.
1.97 +; Workaround
1.98 +; The erratum may be avoided by marking all cacheable memory as one of write through or write back.
1.99 +; This requires the memory attributes described in the translation tables to be modified by software
1.100 +; appropriately, or the use of the remapping capability to remap write through regions to non cacheable.
1.101 +;
1.102 +; If this macro is enabled, it should be accompanied by:
1.103 +; "macro __CPU_ARM1136_ERRATUM_399234_FIXED" in variant.mmh
1.104 +; GBLL CFG_CPU_ARM1136_ERRATUM_399234_FIXED
1.105 +
1.106 +
1.107 +; Uncomment if:
1.108 +; 1) using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache
1.109 +; operation might fail to invalidate some lines if coincident with linefill"
1.110 +; is fixed on this hardware, or
1.111 +; 2) using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache
1.112 +; operation might fail to invalidate some lines if coincident with linefill
1.113 +; is fixed on this hardware.
1.114 +; Workaround:
1.115 +; 1) Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg.
1.116 +; 2) Replaces Invalidate ICache operation with the sequence defined in the errata document.
1.117 +; If this macro is enabled, it should be accompanied by:
1.118 +; "macro __CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh
1.119 +;
1.120 +; GBLL CFG_CPU_ARM1136_ERRATUM_411920_FIXED
1.121 +
1.122 +
1.123 +; Uncomment if using ARM1136 processor and ARM1136 Erratum 415662: "Invalidate Instruction Cache by
1.124 +; Index might corrupt cache when used with background prefetch range" is fixed on this hardware.
1.125 +; Workaround:
1.126 +; Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg.
1.127 +;
1.128 +; GBLL CFG_CPU_ARM1136_ERRATUM_415662_FIXED
1.129 +
1.130 +
1.131 +
1.132 +; These are deduced from the supplied configuration
1.133 +; CFG_ARMV6
1.134 +; CFG_MMUPresent
1.135 +; CFG_CachePresent
1.136 +; CFG_WriteBufferPresent
1.137 +; CFG_SplitCache
1.138 +; CFG_SplitTLB
1.139 +; CFG_AltDCachePresent
1.140 +; CFG_WriteBackCache
1.141 +; CFG_CacheWriteAllocate
1.142 +; CFG_CachePhysicalTag
1.143 +; CFG_CacheFlushByDataRead
1.144 +; CFG_CacheFlushByWaySetIndex
1.145 +; CFG_CacheFlushByLineAlloc
1.146 +; CFG_CachePolicyInPTE
1.147 +; CFG_TEX
1.148 +; CFG_SingleEntryDCacheFlush
1.149 +; CFG_SingleEntryICacheFlush
1.150 +; CFG_SingleEntryITLBFlush
1.151 +; CFG_SingleEntryTLBFlush
1.152 +; CFG_CacheTypeReg
1.153 +; CFG_BTBPresent
1.154 +; CFG_CARPresent
1.155 +; CFG_PrefetchBuffer
1.156 +; CFG_FCSE_Present
1.157 +; CFG_ASID_Present
1.158 +; CFG_IncludeRAMAllocator
1.159 +
1.160 + END