// Copyright (c) 2002-2009 Nokia Corporation and/or its subsidiary(-ies).

// All rights reserved.

// This component and the accompanying materials are made available

// under the terms of "Eclipse Public License v1.0"

// which accompanies this distribution, and is available

// at the URL "http://www.eclipse.org/legal/epl-v10.html".

//

// Initial Contributors:

// Nokia Corporation - initial contribution.

//

// Contributors:

//

// Description:

// e32/drivers/dma2_pil.cpp

// DMA Platform Independent Layer (PIL)

//

//

#include <drivers/dma.h>

#include <drivers/dma_hai.h>

#include <kernel/kern_priv.h>

// Symbian Min() & Max() are broken, so we have to define them ourselves

inline TUint Min(TUint aLeft, TUint aRight)

	{return(aLeft < aRight ? aLeft : aRight);}

inline TUint Max(TUint aLeft, TUint aRight)

	{return(aLeft > aRight ? aLeft : aRight);}

// Uncomment the following #define only when freezing the DMA2 export library.

//#define __FREEZE_DMA2_LIB

#ifdef __FREEZE_DMA2_LIB

TInt DmaChannelMgr::StaticExtension(TInt, TAny*) {return 0;}

TDmaChannel* DmaChannelMgr::Open(TUint32, TBool, TUint) {return 0;}

void DmaChannelMgr::Close(TDmaChannel*) {}

EXPORT_C const TDmaTestInfo& DmaTestInfo() {static TDmaTestInfo a; return a;}

EXPORT_C const TDmaV2TestInfo& DmaTestInfoV2() {static TDmaV2TestInfo a; return a;}

#endif	// #ifdef __FREEZE_DMA2_LIB

static const char KDmaPanicCat[] = "DMA " __FILE__;

//////////////////////////////////////////////////////////////////////

// DmaChannelMgr

//

// Wait, Signal, and Initialise are defined here in the PIL.

// Open, Close and Extension must be defined in the PSL.

NFastMutex DmaChannelMgr::Lock;

void DmaChannelMgr::Wait()

	{

	NKern::FMWait(&Lock);

	}

void DmaChannelMgr::Signal()

	{

	NKern::FMSignal(&Lock);

	}

TInt DmaChannelMgr::Initialise()

	{

	return KErrNone;

	}

class TDmaCancelInfo : public SDblQueLink

	{

public:

	TDmaCancelInfo();

	void Signal();

public:

	NFastSemaphore iSem;

	};

TDmaCancelInfo::TDmaCancelInfo()

	: iSem(0)

	{

	iNext = this;

	iPrev = this;

	}

void TDmaCancelInfo::Signal()

	{

	TDmaCancelInfo* p = this;

	FOREVER

		{

		TDmaCancelInfo* next = (TDmaCancelInfo*)p->iNext;

		if (p!=next)

			p->Deque();

		NKern::FSSignal(&p->iSem);	// Don't dereference p after this

		if (p==next)

			break;

		p = next;

		}

	}

//////////////////////////////////////////////////////////////////////////////

#ifdef __DMASIM__

#ifdef __WINS__

typedef TLinAddr TPhysAddr;

#endif

static inline TPhysAddr LinToPhys(TLinAddr aLin) {return aLin;}

#else

static inline TPhysAddr LinToPhys(TLinAddr aLin) {return Epoc::LinearToPhysical(aLin);}

#endif

//

// Return minimum of aMaxSize and size of largest physically contiguous block

// starting at aLinAddr.

//

static TInt MaxPhysSize(TLinAddr aLinAddr, const TInt aMaxSize)

	{

	const TPhysAddr physBase = LinToPhys(aLinAddr);

	TLinAddr lin = aLinAddr;

	TInt size = 0;

	for (;;)

		{

		// Round up the linear address to the next MMU page boundary

		const TLinAddr linBoundary = Kern::RoundToPageSize(lin + 1);

		size += linBoundary - lin;

		if (size >= aMaxSize)

			return aMaxSize;

		if ((physBase + size) != LinToPhys(linBoundary))

			return size;

		lin = linBoundary;

		}

	}

//////////////////////////////////////////////////////////////////////////////

// TDmac

TDmac::TDmac(const SCreateInfo& aInfo)

	: iMaxDesCount(aInfo.iDesCount),

	  iAvailDesCount(aInfo.iDesCount),

	  iHdrPool(NULL),

#ifndef __WINS__

	  iHwDesChunk(NULL),

#endif

	  iDesPool(NULL),

	  iDesSize(aInfo.iDesSize),

	  iCapsHwDes(aInfo.iCapsHwDes),

	  iFreeHdr(NULL)

	{

	__DMA_ASSERTD(iMaxDesCount > 0);

	__DMA_ASSERTD(iDesSize > 0);

	}

//

// Second-phase c'tor

//

TInt TDmac::Create(const SCreateInfo& aInfo)

	{

	iHdrPool = new SDmaDesHdr[iMaxDesCount];

	if (iHdrPool == NULL)

		{

		return KErrNoMemory;

		}

	TInt r = AllocDesPool(aInfo.iDesChunkAttribs);

	if (r != KErrNone)

		{

		return KErrNoMemory;

		}

	// Link all descriptor headers together on the free list

	iFreeHdr = iHdrPool;

	for (TInt i = 0; i < iMaxDesCount - 1; i++)

		iHdrPool[i].iNext = iHdrPool + i + 1;

	iHdrPool[iMaxDesCount-1].iNext = NULL;

	__DMA_INVARIANT();

	return KErrNone;

	}

TDmac::~TDmac()

	{

	__DMA_INVARIANT();

	FreeDesPool();

	delete[] iHdrPool;

	}

void TDmac::Transfer(const TDmaChannel& /*aChannel*/, const SDmaDesHdr& /*aHdr*/)

	{

	// TDmac needs to override this function if it has reported the channel

	// type for which the PIL calls it.

	__DMA_CANT_HAPPEN();

	}

void TDmac::Transfer(const TDmaChannel& /*aChannel*/, const SDmaDesHdr& /*aSrcHdr*/,

					 const SDmaDesHdr& /*aDstHdr*/)

	{

	// TDmac needs to override this function if it has reported the channel

	// type for which the PIL calls it.

	__DMA_CANT_HAPPEN();

	}

TInt TDmac::PauseTransfer(const TDmaChannel& /*aChannel*/)

	{

	// TDmac needs to override this function if it has reported support for

	// channel pausing/resuming.

	return KErrNotSupported;

	}

TInt TDmac::ResumeTransfer(const TDmaChannel& /*aChannel*/)

	{

	// TDmac needs to override this function if it has reported support for

	// channel pausing/resuming.

	return KErrNotSupported;

	}

TInt TDmac::AllocDesPool(TUint aAttribs)

	{

	// Calling thread must be in CS

	__ASSERT_CRITICAL;

	TInt r;

	if (iCapsHwDes)

		{

		const TInt size = iMaxDesCount * iDesSize;

#ifdef __WINS__

		(void)aAttribs;

		iDesPool = new TUint8[size];

		r = iDesPool ? KErrNone : KErrNoMemory;

#else

		// Chunk not mapped as supervisor r/w user none? incorrect mask passed by PSL

		__DMA_ASSERTD((aAttribs & EMapAttrAccessMask) == EMapAttrSupRw);

		TPhysAddr phys;

		r = Epoc::AllocPhysicalRam(size, phys);

		if (r == KErrNone)

			{

			r = DPlatChunkHw::New(iHwDesChunk, phys, size, aAttribs);

			if (r == KErrNone)

				{

				iDesPool = (TAny*)iHwDesChunk->LinearAddress();

				__KTRACE_OPT(KDMA, Kern::Printf("descriptor hw chunk created lin=0x%08X phys=0x%08X, size=0x%X",

												iHwDesChunk->iLinAddr, iHwDesChunk->iPhysAddr, size));

				}

			else

				Epoc::FreePhysicalRam(phys, size);

			}

#endif

		}

	else

		{

		iDesPool = new TDmaTransferArgs[iMaxDesCount];

		r = iDesPool ? KErrNone : KErrNoMemory;

		}

	return r;

	}

void TDmac::FreeDesPool()

	{

	// Calling thread must be in CS

	__ASSERT_CRITICAL;

	if (iCapsHwDes)

		{

#ifdef __WINS__

		delete[] iDesPool;

#else

		if (iHwDesChunk)

			{

			const TPhysAddr phys = iHwDesChunk->PhysicalAddress();

			const TInt size = iHwDesChunk->iSize;

			iHwDesChunk->Close(NULL);

			Epoc::FreePhysicalRam(phys, size);

			}

#endif

		}

	else

		{

		Kern::Free(iDesPool);

		}

	}

//

// Prealloc the given number of descriptors.

//

TInt TDmac::ReserveSetOfDes(TInt aCount)

	{

	__KTRACE_OPT(KDMA, Kern::Printf("TDmac::ReserveSetOfDes count=%d", aCount));

	__DMA_ASSERTD(aCount > 0);

	TInt r = KErrTooBig;

	Wait();

	if (iAvailDesCount - aCount >= 0)

		{

		iAvailDesCount -= aCount;

		r = KErrNone;

		}

	Signal();

	__DMA_INVARIANT();

	return r;

	}

//

// Return the given number of preallocated descriptors to the free pool.

//

void TDmac::ReleaseSetOfDes(TInt aCount)

	{

	__DMA_ASSERTD(aCount >= 0);

	Wait();

	iAvailDesCount += aCount;

	Signal();

	__DMA_INVARIANT();

	}

//

// Queue DFC and update word used to communicate with channel DFC.

//

// Called in interrupt context by PSL.

//

void TDmac::HandleIsr(TDmaChannel& aChannel, TUint aEventMask, TBool aIsComplete)

	{

	__KTRACE_OPT(KDMA, Kern::Printf("TDmac::HandleIsr"));

	// Function needs to be called by PSL in ISR context

	__DMA_ASSERTD(NKern::CurrentContext() == NKern::EInterrupt);

	// First the ISR callback stuff

	// Is this a transfer completion notification?

	if (aEventMask & EDmaCallbackRequestCompletion)

		{

		// If so, has the client requested an ISR callback?

		if (__e32_atomic_load_acq32(&aChannel.iIsrCbRequest))

			{

			__KTRACE_OPT(KDMA, Kern::Printf("ISR callback"));

			// Since iIsrCbRequest was set no threads will be

			// modifying the request queue.

			const DDmaRequest* const req = _LOFF(aChannel.iReqQ.First(), DDmaRequest, iLink);

			// We expect the request to have requested

			// ISR callback

			__NK_ASSERT_DEBUG(req->iIsrCb);

			TDmaCallback const cb = req->iDmaCb;

			TAny* const arg = req->iDmaCbArg;

			// Execute the client callback

			(*cb)(EDmaCallbackRequestCompletion,

				  (aIsComplete ? EDmaResultOK : EDmaResultError),

				  arg,

				  NULL);

			// Now let's see if the callback rescheduled the transfer request

			// (see TDmaChannel::IsrRedoRequest()).

			const TBool redo = aChannel.iRedoRequest;

			aChannel.iRedoRequest = EFalse;

			const TBool stop = __e32_atomic_load_acq32(&aChannel.iIsrDfc) &

				(TUint32)TDmaChannel::KCancelFlagMask;

			// There won't be another ISR callback if this callback didn't

			// reschedule the request, or the client cancelled all requests, or

			// this callback rescheduled the request with a DFC callback.

			if (!redo || stop || !req->iIsrCb)

				{

				__e32_atomic_store_rel32(&aChannel.iIsrCbRequest, EFalse);

				}

			if (redo && !stop)

				{

				// We won't queue the channel DFC in this case and just return.

				__KTRACE_OPT(KDMA, Kern::Printf("CB rescheduled xfer -> no DFC"));

				return;

				}

			// Not redoing or being cancelled means we've been calling the

			// request's ISR callback for the last time. We're going to

			// complete the request via the DFC in the usual way.

			}

		}

	// Now queue a DFC if necessary. The possible scenarios are:

	// a) DFC not queued (orig == 0)              -> update iIsrDfc + queue DFC

	// b) DFC queued, not running yet (orig != 0) -> just update iIsrDfc

	// c) DFC running / iIsrDfc not reset yet (orig != 0) -> just update iIsrDfc

	// d) DFC running / iIsrDfc already reset (orig == 0) -> update iIsrDfc + requeue DFC

	// Set error flag if necessary.

	const TUint32 inc = aIsComplete ? 1u : TUint32(TDmaChannel::KErrorFlagMask) | 1u;

	// Add 'inc' (interrupt count increment + poss. error flag) to 'iIsrDfc' if

	// cancel flag is not set, do nothing otherwise. Assign original value of

	// 'iIsrDfc' to 'orig' in any case.

	const TUint32 orig = __e32_atomic_tau_ord32(&aChannel.iIsrDfc,

												TUint32(TDmaChannel::KCancelFlagMask),

												0,

												inc);

	// As transfer should be suspended when an error occurs, we

	// should never get there with the error flag already set.

	__DMA_ASSERTD((orig & inc & (TUint32)TDmaChannel::KErrorFlagMask) == 0);

	if (orig == 0)

		{

		aChannel.iDfc.Add();

		}

	}

TInt TDmac::InitDes(const SDmaDesHdr& aHdr, const TDmaTransferArgs& aTransferArgs)

	{

	__KTRACE_OPT(KDMA, Kern::Printf("TDmac::InitDes"));

	TInt r;

	if (iCapsHwDes)

		{

		__KTRACE_OPT(KDMA, Kern::Printf("iCaps.iHwDescriptors"));

		r = InitHwDes(aHdr, aTransferArgs);

		}

	else

		{

		TDmaTransferArgs& args = HdrToDes(aHdr);

		args = aTransferArgs;

		r = KErrNone;

		}

	return r;

	}

TInt TDmac::InitHwDes(const SDmaDesHdr& /*aHdr*/, const TDmaTransferArgs& /*aTransferArgs*/)

	{

	// concrete controller must override if SDmacCaps::iHwDescriptors set

	__DMA_CANT_HAPPEN();

	return KErrGeneral;

	}

TInt TDmac::InitSrcHwDes(const SDmaDesHdr& /*aHdr*/, const TDmaTransferArgs& /*aTransferArgs*/)

	{

	// concrete controller must override if SDmacCaps::iAsymHwDescriptors set

	__DMA_CANT_HAPPEN();

	return KErrGeneral;

	}

TInt TDmac::InitDstHwDes(const SDmaDesHdr& /*aHdr*/, const TDmaTransferArgs& /*aTransferArgs*/)

	{

	// concrete controller must override if SDmacCaps::iAsymHwDescriptors set

	__DMA_CANT_HAPPEN();

	return KErrGeneral;

	}

TInt TDmac::UpdateDes(const SDmaDesHdr& aHdr, TUint32 aSrcAddr, TUint32 aDstAddr,

					  TUint aTransferCount, TUint32 aPslRequestInfo)

	{

	__KTRACE_OPT(KDMA, Kern::Printf("TDmac::UpdateDes"));

	TInt r;

	if (iCapsHwDes)

		{

		__KTRACE_OPT(KDMA, Kern::Printf("iCaps.iHwDescriptors"));

		r = UpdateHwDes(aHdr, aSrcAddr, aDstAddr, aTransferCount, aPslRequestInfo);

		}

	else

		{

		TDmaTransferArgs& args = HdrToDes(aHdr);

		if (aSrcAddr != KPhysAddrInvalid)

			args.iSrcConfig.iAddr = aSrcAddr;

		if (aDstAddr != KPhysAddrInvalid)

			args.iDstConfig.iAddr = aDstAddr;

		if (aTransferCount)

			args.iTransferCount = aTransferCount;

		if (aPslRequestInfo)

			args.iPslRequestInfo = aPslRequestInfo;

		r = KErrNone;

		}

	return r;

	}

TInt TDmac::UpdateHwDes(const SDmaDesHdr& /*aHdr*/, TUint32 /*aSrcAddr*/, TUint32 /*aDstAddr*/,

						TUint /*aTransferCount*/, TUint32 /*aPslRequestInfo*/)

	{

	// concrete controller must override if SDmacCaps::iHwDescriptors set

	__DMA_CANT_HAPPEN();

	return KErrGeneral;

	}

TInt TDmac::UpdateSrcHwDes(const SDmaDesHdr& /*aHdr*/, TUint32 /*aSrcAddr*/,

						   TUint /*aTransferCount*/, TUint32 /*aPslRequestInfo*/)

	{

	// concrete controller must override if SDmacCaps::iAsymHwDescriptors set

	__DMA_CANT_HAPPEN();

	return KErrGeneral;

	}

TInt TDmac::UpdateDstHwDes(const SDmaDesHdr& /*aHdr*/, TUint32 /*aDstAddr*/,

						   TUint /*aTransferCount*/, TUint32 /*aPslRequestInfo*/)

	{

	// concrete controller must override if SDmacCaps::iAsymHwDescriptors set

	__DMA_CANT_HAPPEN();

	return KErrGeneral;

	}

void TDmac::ChainHwDes(const SDmaDesHdr& /*aHdr*/, const SDmaDesHdr& /*aNextHdr*/)

	{

	// concrete controller must override if SDmacCaps::iHwDescriptors set

	__DMA_CANT_HAPPEN();

	}

void TDmac::AppendHwDes(const TDmaChannel& /*aChannel*/, const SDmaDesHdr& /*aLastHdr*/,

						const SDmaDesHdr& /*aNewHdr*/)

	{

 	// concrete controller must override if SDmacCaps::iHwDescriptors set

	__DMA_CANT_HAPPEN();

	}

void TDmac::AppendHwDes(const TDmaChannel& /*aChannel*/,

						const SDmaDesHdr& /*aSrcLastHdr*/, const SDmaDesHdr& /*aSrcNewHdr*/,

						const SDmaDesHdr& /*aDstLastHdr*/, const SDmaDesHdr& /*aDstNewHdr*/)

	{

	// concrete controller must override if SDmacCaps::iAsymHwDescriptors set

	__DMA_CANT_HAPPEN();

	}

void TDmac::UnlinkHwDes(const TDmaChannel& /*aChannel*/, SDmaDesHdr& /*aHdr*/)

	{

 	// concrete controller must override if SDmacCaps::iHwDescriptors set

	__DMA_CANT_HAPPEN();

	}

void TDmac::ClearHwDes(const SDmaDesHdr& /*aHdr*/)

	{

	// default implementation - NOP; concrete controller may override

	return;

	}

TInt TDmac::LinkChannels(TDmaChannel& /*a1stChannel*/, TDmaChannel& /*a2ndChannel*/)

	{

	// default implementation - NOP; concrete controller may override

	return KErrNotSupported;

	}

TInt TDmac::UnlinkChannel(TDmaChannel& /*aChannel*/)

	{

	// default implementation - NOP; concrete controller may override

	return KErrNotSupported;

	}

TInt TDmac::FailNext(const TDmaChannel& /*aChannel*/)

	{

	// default implementation - NOP; concrete controller may override

	return KErrNotSupported;

	}

TInt TDmac::MissNextInterrupts(const TDmaChannel& /*aChannel*/, TInt /*aInterruptCount*/)

	{

	// default implementation - NOP; concrete controller may override

	return KErrNotSupported;

	}

TInt TDmac::Extension(TDmaChannel& /*aChannel*/, TInt /*aCmd*/, TAny* /*aArg*/)

	{

	// default implementation - NOP; concrete controller may override

	return KErrNotSupported;

	}

TUint32 TDmac::HwDesNumDstElementsTransferred(const SDmaDesHdr& /*aHdr*/)

	{

 	// Concrete controller must override if SDmacCaps::iHwDescriptors set.

	__DMA_CANT_HAPPEN();

	return 0;

	}

TUint32 TDmac::HwDesNumSrcElementsTransferred(const SDmaDesHdr& /*aHdr*/)

	{

 	// Concrete controller must override if SDmacCaps::iHwDescriptors set.

	__DMA_CANT_HAPPEN();

	return 0;

	}

#ifdef _DEBUG

void TDmac::Invariant()

	{

	Wait();

	__DMA_ASSERTD(0 <= iAvailDesCount && iAvailDesCount <= iMaxDesCount);

	__DMA_ASSERTD(! iFreeHdr || IsValidHdr(iFreeHdr));

	for (TInt i = 0; i < iMaxDesCount; i++)

		__DMA_ASSERTD(iHdrPool[i].iNext == NULL || IsValidHdr(iHdrPool[i].iNext));

	Signal();

	}

TBool TDmac::IsValidHdr(const SDmaDesHdr* aHdr)

	{

	return (iHdrPool <= aHdr) && (aHdr < iHdrPool + iMaxDesCount);

	}

#endif

//

// Internal compat version, used by legacy Fragment()

//

TDmaTransferConfig::TDmaTransferConfig(TUint32 aAddr, TUint aFlags, TBool aAddrInc)

	: iAddr(aAddr),

	  iAddrMode(aAddrInc ? KDmaAddrModePostIncrement : KDmaAddrModeConstant),

	  iElementSize(0),

	  iElementsPerFrame(0),

	  iElementsPerPacket(0),

	  iFramesPerTransfer(0),

	  iElementSkip(0),

	  iFrameSkip(0),

	  iBurstSize(KDmaBurstSizeAny),

	  iFlags(aFlags),

	  iSyncFlags(KDmaSyncAuto),

	  iPslTargetInfo(0),

	  iRepeatCount(0),

	  iDelta(~0u),

	  iReserved(0)

	{

	}

//

// Internal compat version, used by legacy Fragment()

//

TDmaTransferArgs::TDmaTransferArgs(TUint32 aSrc, TUint32 aDest, TInt aCount,

								   TUint aFlags, TUint32 aPslInfo)

	: iSrcConfig(aSrc, RequestFlags2SrcConfigFlags(aFlags), (aFlags & KDmaIncSrc)),

	  iDstConfig(aDest, RequestFlags2DstConfigFlags(aFlags), (aFlags & KDmaIncDest)),

	  iTransferCount(aCount),

	  iGraphicsOps(KDmaGraphicsOpNone),

	  iColour(0),

	  iFlags(0),

	  iChannelPriority(KDmaPriorityNone),

	  iPslRequestInfo(aPslInfo),

	  iDelta(~0u),

	  iReserved1(0),

	  iChannelCookie(0),

	  iReserved2(0)

	{

	}

//

// As DDmaRequest is derived from DBase, the initializations with zero aren't

// strictly necessary here, but this way it's nicer.

//

EXPORT_C DDmaRequest::DDmaRequest(TDmaChannel& aChannel, TCallback aCb,

								  TAny* aCbArg, TInt aMaxTransferSize)

	: iChannel(aChannel),

	  iCb(aCb),

	  iCbArg(aCbArg),

	  iDmaCb(NULL),

	  iDmaCbArg(NULL),

	  iIsrCb(EFalse),

	  iDesCount(0),

	  iFirstHdr(NULL),

	  iLastHdr(NULL),

	  iSrcDesCount(0),

	  iSrcFirstHdr(NULL),

	  iSrcLastHdr(NULL),

	  iDstDesCount(0),

	  iDstFirstHdr(NULL),

	  iDstLastHdr(NULL),

	  iQueued(EFalse),

	  iMaxTransferSize(aMaxTransferSize),

	  iTotalNumSrcElementsTransferred(0),

	  iTotalNumDstElementsTransferred(0)

	{

	iChannel.iReqCount++;

	__DMA_ASSERTD(0 <= aMaxTransferSize);

	__DMA_INVARIANT();

	}

//

// As DDmaRequest is derived from DBase, the initializations with zero aren't

// strictly necessary here, but this way it's nicer.

//

EXPORT_C DDmaRequest::DDmaRequest(TDmaChannel& aChannel, TDmaCallback aDmaCb,

								  TAny* aCbArg, TUint aMaxTransferSize)

	: iChannel(aChannel),

	  iCb(NULL),

	  iCbArg(NULL),

	  iDmaCb(aDmaCb),

	  iDmaCbArg(aCbArg),

	  iIsrCb(EFalse),

	  iDesCount(0),

	  iFirstHdr(NULL),

	  iLastHdr(NULL),

	  iSrcDesCount(0),

	  iSrcFirstHdr(NULL),

	  iSrcLastHdr(NULL),

	  iDstDesCount(0),

	  iDstFirstHdr(NULL),

	  iDstLastHdr(NULL),

	  iQueued(EFalse),

	  iMaxTransferSize(aMaxTransferSize),

	  iTotalNumSrcElementsTransferred(0),

	  iTotalNumDstElementsTransferred(0)

	{

	__e32_atomic_add_ord32(&iChannel.iReqCount, 1);

	__DMA_INVARIANT();

	}

EXPORT_C DDmaRequest::~DDmaRequest()

	{

	__DMA_ASSERTD(!iQueued);

	__DMA_INVARIANT();

	FreeDesList();

	__e32_atomic_add_ord32(&iChannel.iReqCount, TUint32(-1));

	}

EXPORT_C TInt DDmaRequest::Fragment(TUint32 aSrc, TUint32 aDest, TInt aCount,

									TUint aFlags, TUint32 aPslInfo)

	{

	__KTRACE_OPT(KDMA, Kern::Printf("DDmaRequest::Fragment thread %O "

									"src=0x%08X dest=0x%08X count=%d flags=0x%X psl=0x%08X",

									&Kern::CurrentThread(), aSrc, aDest, aCount, aFlags, aPslInfo));

	__DMA_ASSERTD(aCount > 0);

	TDmaTransferArgs args(aSrc, aDest, aCount, aFlags, aPslInfo);

	return Frag(args);

	}

EXPORT_C TInt DDmaRequest::Fragment(const TDmaTransferArgs& aTransferArgs)

	{

	__KTRACE_OPT(KDMA, Kern::Printf("DDmaRequest::Fragment thread %O", &Kern::CurrentThread()));

	// Writable temporary working copy of the transfer arguments.

	// We need this because we may have to modify some fields before passing it

	// to the PSL (for example iChannelCookie, iTransferCount,

	// iDstConfig::iAddr, and iSrcConfig::iAddr).

	TDmaTransferArgs args(aTransferArgs);

	return Frag(args);

	}

TUint DDmaRequest::GetTransferCount(const TDmaTransferArgs& aTransferArgs)

	{

	const TDmaTransferConfig& src = aTransferArgs.iSrcConfig;

	const TDmaTransferConfig& dst = aTransferArgs.iDstConfig;

	TUint count = aTransferArgs.iTransferCount;

	if (count == 0)

		{

		__KTRACE_OPT(KDMA, Kern::Printf("iTransferCount == 0"));

		count = src.iElementSize * src.iElementsPerFrame *

			src.iFramesPerTransfer;

		const TUint dst_cnt = dst.iElementSize * dst.iElementsPerFrame *

			dst.iFramesPerTransfer;

		if (count != dst_cnt)

			{

			__KTRACE_OPT(KPANIC, Kern::Printf("Error: (count != dst_cnt)"));

			return 0;

			}

		}

	else

		{

		__KTRACE_OPT(KDMA, Kern::Printf("iTransferCount == %d", count));

		// Client shouldn't specify contradictory or incomplete things

		if (src.iElementSize != 0)

			{

			if ((count % src.iElementSize) != 0)

				{

				__KTRACE_OPT(KPANIC,

							 Kern::Printf("Error: ((count %% src.iElementSize) != 0)"));

				return 0;

				}

			if (src.iElementsPerFrame != 0)

				{

				if ((src.iElementSize * src.iElementsPerFrame * src.iFramesPerTransfer) != count)

					{

					__KTRACE_OPT(KPANIC,

								 Kern::Printf("Error: ((src.iElementSize * "

											  "src.iElementsPerFrame * "

											  "src.iFramesPerTransfer) != count)"));

					return 0;

					}

				}

			}

		else

			{

			if (src.iElementsPerFrame != 0)

				{

				__KTRACE_OPT(KPANIC,

							 Kern::Printf("Error: (src.iElementsPerFrame != 0)"));

				return 0;

				}

			if (src.iFramesPerTransfer != 0)

				{

				__KTRACE_OPT(KPANIC,

							 Kern::Printf("Error: (src.iFramesPerTransfer != 0)"));

				return 0;

				}

			if (src.iElementsPerPacket != 0)

				{

				__KTRACE_OPT(KPANIC,

							 Kern::Printf("Error: (src.iElementsPerPacket != 0)"));

				return 0;

				}

			}

		if (dst.iElementSize != 0)

			{

			if ((count % dst.iElementSize) != 0)

				{

				__KTRACE_OPT(KPANIC,

							 Kern::Printf("Error: ((count %% dst.iElementSize) != 0)"));

				return 0;

				}

			if (dst.iElementsPerFrame != 0)

				{

				if ((dst.iElementSize * dst.iElementsPerFrame * dst.iFramesPerTransfer) != count)

					{

					__KTRACE_OPT(KPANIC,

								 Kern::Printf("Error: ((dst.iElementSize * "

											  "dst.iElementsPerFrame * "

											  "dst.iFramesPerTransfer) != count)"));

					return 0;

					}

				}

			}

		else

			{

			if (dst.iElementsPerFrame != 0)

				{

				__KTRACE_OPT(KPANIC,

							 Kern::Printf("Error: (dst.iElementsPerFrame != 0)"));

				return 0;

				}

			if (dst.iFramesPerTransfer != 0)

				{

				__KTRACE_OPT(KPANIC,

							 Kern::Printf("Error: (dst.iFramesPerTransfer != 0)"));

				return 0;

				}

			if (dst.iElementsPerPacket != 0)

				{

				__KTRACE_OPT(KPANIC,

							 Kern::Printf("Error: (dst.iElementsPerPacket != 0)"));

				return 0;

				}

			}

		}

	return count;

	}

TInt DDmaRequest::Frag(TDmaTransferArgs& aTransferArgs)

	{

	__DMA_ASSERTD(!iQueued);

	// Transfer count checks

	const TUint count = GetTransferCount(aTransferArgs);

	if (count == 0)

		{

		return KErrArgument;

		}

	const TDmaTransferConfig& src = aTransferArgs.iSrcConfig;

	const TDmaTransferConfig& dst = aTransferArgs.iDstConfig;

	// Ask the PSL what the maximum length possible for this transfer is

	TUint max_xfer_len = iChannel.MaxTransferLength(src.iFlags, dst.iFlags,

													aTransferArgs.iPslRequestInfo);

	if (iMaxTransferSize)

		{

		// User has set a size cap

		__KTRACE_OPT(KDMA, Kern::Printf("iMaxTransferSize != 0"));

		__DMA_ASSERTA((iMaxTransferSize <= max_xfer_len) || (max_xfer_len == 0));

		max_xfer_len = iMaxTransferSize;

		}

	else

		{

		// User doesn't care about max size

		if (max_xfer_len == 0)

			{

			// No maximum imposed by controller

			max_xfer_len = count;

			}

		}

	// ISR callback requested?

	const TBool isr_cb = (aTransferArgs.iFlags & KDmaRequestCallbackFromIsr);

	if (isr_cb)

		{

		// Requesting an ISR callback w/o supplying one?

		if (!iDmaCb)

			{

			return KErrArgument;

			}

		}

	// Set the channel cookie for the PSL

	aTransferArgs.iChannelCookie = iChannel.PslId();

	// Now the actual fragmentation

	TInt r;

	if (iChannel.iDmacCaps->iAsymHwDescriptors)

		{

		r = FragAsym(aTransferArgs, count, max_xfer_len);

		}

	else

		{

		r = FragSym(aTransferArgs, count, max_xfer_len);

		}

	if (r == KErrNone)

		{

		iIsrCb = isr_cb;

		}

	__DMA_INVARIANT();

	return r;

	};

TInt DDmaRequest::FragSym(TDmaTransferArgs& aTransferArgs, TUint aCount,

						  TUint aMaxTransferLen)

	{

	TDmaTransferConfig& src = aTransferArgs.iSrcConfig;

	TDmaTransferConfig& dst = aTransferArgs.iDstConfig;

	const TBool mem_src = (src.iFlags & KDmaMemAddr);

	const TBool mem_dst = (dst.iFlags & KDmaMemAddr);

	const TUint align_mask_src = iChannel.AddressAlignMask(src.iFlags,

														   src.iElementSize,

														   aTransferArgs.iPslRequestInfo);

	const TUint align_mask_dst = iChannel.AddressAlignMask(dst.iFlags,

														   dst.iElementSize,

														   aTransferArgs.iPslRequestInfo);

	// Memory buffers must satisfy alignment constraint

	__DMA_ASSERTD(!mem_src || ((src.iAddr & align_mask_src) == 0));

	__DMA_ASSERTD(!mem_dst || ((dst.iAddr & align_mask_dst) == 0));

	const TUint max_aligned_len = (aMaxTransferLen &

								   ~(Max(align_mask_src, align_mask_dst)));

	// Client and PSL sane?

	__DMA_ASSERTD(max_aligned_len > 0);

	FreeDesList();			   // revert any previous fragmentation attempt

	TInt r;

	do

		{

		// Allocate fragment

		r = ExpandDesList(/*1*/);

		if (r != KErrNone)

			{

			FreeDesList();

			break;

			}

		// Compute fragment size

		TUint c = Min(aMaxTransferLen, aCount);

		if (mem_src && !(src.iFlags & KDmaPhysAddr))

			{

			__KTRACE_OPT(KDMA, Kern::Printf("mem_src && !(src.iFlags & KDmaPhysAddr)"));

			// @@@ Should also take into account (src.iFlags & KDmaMemIsContiguous)!

			c = MaxPhysSize(src.iAddr, c);

			}

		if (mem_dst && !(dst.iFlags & KDmaPhysAddr))