sl@0
|
1 |
// Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
|
sl@0
|
2 |
// All rights reserved.
|
sl@0
|
3 |
// This component and the accompanying materials are made available
|
sl@0
|
4 |
// under the terms of the License "Eclipse Public License v1.0"
|
sl@0
|
5 |
// which accompanies this distribution, and is available
|
sl@0
|
6 |
// at the URL "http://www.eclipse.org/legal/epl-v10.html".
|
sl@0
|
7 |
//
|
sl@0
|
8 |
// Initial Contributors:
|
sl@0
|
9 |
// Nokia Corporation - initial contribution.
|
sl@0
|
10 |
//
|
sl@0
|
11 |
// Contributors:
|
sl@0
|
12 |
//
|
sl@0
|
13 |
// Description:
|
sl@0
|
14 |
//
|
sl@0
|
15 |
|
sl@0
|
16 |
#ifndef __FLASH_NOR_H__
|
sl@0
|
17 |
#define __FLASH_NOR_H__
|
sl@0
|
18 |
|
sl@0
|
19 |
// If Flash parameters are not already defined, set them to Tyax values.
|
sl@0
|
20 |
#ifndef FLASHERASEBLOCKSIZE
|
sl@0
|
21 |
#define FLASHERASEBLOCKSIZE 0x20000 //128KB
|
sl@0
|
22 |
#endif
|
sl@0
|
23 |
#ifndef FLASHWRITEBUFSIZE
|
sl@0
|
24 |
#define FLASHWRITEBUFSIZE 0x40 //64 bytes
|
sl@0
|
25 |
#endif
|
sl@0
|
26 |
|
sl@0
|
27 |
///////////////////////////////////////////////////////////////////////////////
|
sl@0
|
28 |
//
|
sl@0
|
29 |
// CFI - flash identification
|
sl@0
|
30 |
//
|
sl@0
|
31 |
///////////////////////////////////////////////////////////////////////////////
|
sl@0
|
32 |
enum CfiManifacturerId
|
sl@0
|
33 |
{
|
sl@0
|
34 |
CFI_MANUF_SPANSION = 0x01,
|
sl@0
|
35 |
CFI_MANUF_INTEL = 0x89,
|
sl@0
|
36 |
CFI_MANUF_ANY = (TUint16) -1, // some manufacturers' flash chips comform to one standard CFI command set
|
sl@0
|
37 |
};
|
sl@0
|
38 |
|
sl@0
|
39 |
enum CfiDeviceId
|
sl@0
|
40 |
{
|
sl@0
|
41 |
CFI_DEV_S29GL512N = 0x227e,
|
sl@0
|
42 |
CFI_DEV_SIBLEY = 0x88b1, // Intel Sibley as found on 3430 SDP (H6)
|
sl@0
|
43 |
CFI_DEV_28F256L18T = 0x880d, // Intel Tyax as found on my H4
|
sl@0
|
44 |
CFI_DEV_ANY = (TUint16) -1, // some manufacturers' flash chips comform to one standard CFI command set
|
sl@0
|
45 |
};
|
sl@0
|
46 |
|
sl@0
|
47 |
typedef struct
|
sl@0
|
48 |
{
|
sl@0
|
49 |
TPtrC name;
|
sl@0
|
50 |
TUint16 manufacturerId;
|
sl@0
|
51 |
TUint16 deviceId;
|
sl@0
|
52 |
|
sl@0
|
53 |
TInt (*reset)(TUint32 flashId, TUint32 address);
|
sl@0
|
54 |
TInt (*erase)(TUint32 flashId, TUint32 aBase, TUint32 anAddr, TUint32 aSize);
|
sl@0
|
55 |
TInt (*write)(TUint32 flashId, TUint32 anAddr, TUint32 aSize, const TUint32* aPS);
|
sl@0
|
56 |
|
sl@0
|
57 |
TUint blockSize; // the physical block size of the flash
|
sl@0
|
58 |
}
|
sl@0
|
59 |
TFlashInfo;
|
sl@0
|
60 |
|
sl@0
|
61 |
const TUint FLASH_TYPE_UNKNOWN = 0;
|
sl@0
|
62 |
|
sl@0
|
63 |
///////////////////////////////////////////////////////////////////////////////
|
sl@0
|
64 |
//
|
sl@0
|
65 |
// CFI - generic command processing
|
sl@0
|
66 |
//
|
sl@0
|
67 |
///////////////////////////////////////////////////////////////////////////////
|
sl@0
|
68 |
typedef struct
|
sl@0
|
69 |
{
|
sl@0
|
70 |
TUint32 location; // where to write this command to
|
sl@0
|
71 |
TUint32 offset; // the offset for this command
|
sl@0
|
72 |
TUint32 command; // the command itself
|
sl@0
|
73 |
}
|
sl@0
|
74 |
TCfiCommands;
|
sl@0
|
75 |
|
sl@0
|
76 |
enum
|
sl@0
|
77 |
{
|
sl@0
|
78 |
CFI_BASE8, // use the base address for this 8 bit command
|
sl@0
|
79 |
CFI_SECTOR8, // use the sector address for this 8 bit command
|
sl@0
|
80 |
|
sl@0
|
81 |
CFI_END = (TUint32) -1 // used to mark the end of the command sequence
|
sl@0
|
82 |
};
|
sl@0
|
83 |
|
sl@0
|
84 |
|
sl@0
|
85 |
|
sl@0
|
86 |
const TUint32 KFlashEraseBlockSize = FLASHERASEBLOCKSIZE;
|
sl@0
|
87 |
const TUint32 KFlashWriteBufSize = FLASHWRITEBUFSIZE;
|
sl@0
|
88 |
const TUint32 KRebootDelaySecs = 5; // Delay(S) between flashing bootldr to reboot
|
sl@0
|
89 |
|
sl@0
|
90 |
// Flash commands
|
sl@0
|
91 |
//const TUint8 KCmdWordProgram = 0x40 ;
|
sl@0
|
92 |
const TUint8 KCmdBlockErase1 = 0x20 ;
|
sl@0
|
93 |
const TUint8 KCmdBlockErase2 = 0xd0 ;
|
sl@0
|
94 |
//const TUint8 KCmdEraseSuspend = 0xb0 ;
|
sl@0
|
95 |
//const TUint8 KCmdEraseResume = 0xd0 ;
|
sl@0
|
96 |
const TUint8 KCmdReadStatus = 0x70 ;
|
sl@0
|
97 |
const TUint8 KCmdClearStatus = 0x50 ;
|
sl@0
|
98 |
const TUint8 KCmdReadArrayMode = 0xFF ;
|
sl@0
|
99 |
const TUint8 KCmdClearBlockLockBit1 = 0x60 ;
|
sl@0
|
100 |
const TUint8 KCmdClearBlockLockBit2 = 0xD0 ;
|
sl@0
|
101 |
//const TUint8 KCmdSetBlockLockBit1 = 0x60 ;
|
sl@0
|
102 |
//const TUint8 KCmdSetBlockLockBit2 = 0x01 ;
|
sl@0
|
103 |
|
sl@0
|
104 |
// Flash status
|
sl@0
|
105 |
const TUint8 KStatusBusy = 0x80 ;
|
sl@0
|
106 |
//const TUint8 KStatusProgramError = 0x38 ;
|
sl@0
|
107 |
//const TUint8 KStatusVoltageError = 0x08 ;
|
sl@0
|
108 |
const TUint8 KStatusCmdSeqError = 0x30 ;
|
sl@0
|
109 |
const TUint8 KStatusLockBitError = 0x20 ;
|
sl@0
|
110 |
|
sl@0
|
111 |
const TUint8 KCmdWriteStatusSibley = 0xE9; // Sibley write
|
sl@0
|
112 |
const TUint8 KCmdWriteStatus = 0xE8; // send Tyax write
|
sl@0
|
113 |
|
sl@0
|
114 |
GLREF_C TUint32 * GetFlashChunk(void);
|
sl@0
|
115 |
GLREF_C TBool BlankCheck (TUint32 anAddr, TUint32 aSize);
|
sl@0
|
116 |
GLREF_C TInt Erase (TUint32 anAddr, TUint32 aSize);
|
sl@0
|
117 |
GLREF_C TInt Write (TUint32 anAddr, TUint32 aSize, const TUint32* aPS);
|
sl@0
|
118 |
|
sl@0
|
119 |
#endif
|