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// Copyright (c) 2004-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// This file contains stepping code refactored from rm_debug_kerneldriver.cpp/rm_debug_kerneldriver.h
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//
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#include <e32def.h>
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#include <e32def_private.h>
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#include <e32cmn.h>
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#include <e32cmn_private.h>
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#include <kernel/kernel.h>
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#include <kernel/kern_priv.h>
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#include <nk_trace.h>
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#include <arm.h>
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#include <rm_debug_api.h>
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#include "d_rmd_stepping.h"
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#include "d_rmd_breakpoints.h"
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#include "rm_debug_kerneldriver.h" // needed to access DRM_DebugChannel
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#include "rm_debug_driver.h"
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#include "debug_logging.h"
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using namespace Debug;
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//
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// DRMDStepping::DRMDStepping
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//
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DRMDStepping::DRMDStepping(DRM_DebugChannel* aChannel)
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:
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iChannel(aChannel)
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{
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// to do
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}
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//
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// DRMDStepping::~DRM_DebugChannel
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//
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DRMDStepping::~DRMDStepping()
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{
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// to do
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}
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//
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// DRMDStepping::IsExecuted
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//
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TBool DRMDStepping::IsExecuted(TUint8 aCondition ,TUint32 aStatusRegister)
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{
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LOG_MSG("DRMDStepping::IsExecuted()");
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TBool N = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000008;
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TBool Z = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000004;
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TBool C = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000002;
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TBool V = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000001;
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switch(aCondition)
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{
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case 0:
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return Z;
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case 1:
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return !Z;
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case 2:
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return C;
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case 3:
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return !C;
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case 4:
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return N;
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case 5:
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return !N;
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case 6:
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return V;
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case 7:
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return !V;
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case 8:
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return (C && !Z);
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case 9:
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return (!C || Z);
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case 10:
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return (N == V);
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case 11:
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return (N != V);
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case 12:
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return ((N == V) && !Z);
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case 13:
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return (Z || (N != V));
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case 14:
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case 15:
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return ETrue;
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}
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return EFalse;
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}
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//
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// DRMDStepping::IsPreviousInstructionMovePCToLR
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//
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TBool DRMDStepping::IsPreviousInstructionMovePCToLR(DThread *aThread)
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{
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LOG_MSG("DRMDStepping::IsPreviousInstructionMovePCToLR()");
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TInt err = KErrNone;
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// there are several types of instructions that modify the PC that aren't
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// designated as linked or non linked branches. the way gcc generates the
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// code can tell us whether or not these instructions are to be treated as
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// linked branches. the main cases are bx and any type of mov or load or
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// arithmatic operation that changes the PC. if these are really just
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// function calls that will return, gcc will generate a mov lr, pc
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// instruction as the previous instruction. note that this is just for arm
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// and armi
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// get the address of the previous instruction
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TUint32 address = 0;
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err = iChannel->ReadKernelRegisterValue(aThread, PC_REGISTER, address);
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if(err != KErrNone)
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{
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LOG_MSG2("Non-zero error code discarded: %d", err);
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}
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address -= 4;
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TBuf8<4> previousInstruction;
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err = iChannel->DoReadMemory(aThread, address, 4, previousInstruction);
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if (KErrNone != err)
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{
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LOG_MSG2("Error %d reading memory at address %x", address);
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return EFalse;
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}
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const TUint32 movePCToLRIgnoringCondition = 0x01A0E00F;
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TUint32 inst = *(TUint32 *)previousInstruction.Ptr();
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if ((inst & 0x0FFFFFFF) == movePCToLRIgnoringCondition)
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{
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return ETrue;
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}
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return EFalse;
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}
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//
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// DRMDStepping::DecodeDataProcessingInstruction
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//
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void DRMDStepping::DecodeDataProcessingInstruction(TUint8 aOpcode, TUint32 aOp1, TUint32 aOp2, TUint32 aStatusRegister, TUint32 &aBreakAddress)
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{
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LOG_MSG("DRMDStepping::DecodeDataProcessingInstruction()");
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switch(aOpcode)
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{
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case 0:
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{
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// AND
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aBreakAddress = aOp1 & aOp2;
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break;
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}
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case 1:
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{
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// EOR
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aBreakAddress = aOp1 ^ aOp2;
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break;
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}
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case 2:
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{
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// SUB
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aBreakAddress = aOp1 - aOp2;
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break;
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}
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case 3:
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{
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// RSB
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aBreakAddress = aOp2 - aOp1;
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break;
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}
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case 4:
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{
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// ADD
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aBreakAddress = aOp1 + aOp2;
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break;
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}
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case 5:
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{
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// ADC
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aBreakAddress = aOp1 + aOp2 + (aStatusRegister & arm_carry_bit()) ? 1 : 0;
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break;
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}
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case 6:
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{
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// SBC
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aBreakAddress = aOp1 - aOp2 - (aStatusRegister & arm_carry_bit()) ? 0 : 1;
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break;
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}
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case 7:
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{
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// RSC
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aBreakAddress = aOp2 - aOp1 - (aStatusRegister & arm_carry_bit()) ? 0 : 1;
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break;
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}
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case 12:
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{
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// ORR
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aBreakAddress = aOp1 | aOp2;
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break;
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}
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case 13:
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{
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// MOV
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aBreakAddress = aOp2;
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break;
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}
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case 14:
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{
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// BIC
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aBreakAddress = aOp1 & ~aOp2;
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break;
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}
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case 15:
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{
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// MVN
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aBreakAddress = ~aOp2;
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break;
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}
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}
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}
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//
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// DRMDStepping::CurrentInstruction
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//
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// Returns the current instruction bitpattern (either 32-bits or 16-bits) if possible
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TInt DRMDStepping::CurrentInstruction(DThread* aThread, TUint32& aInstruction)
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{
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LOG_MSG("DRMDStepping::CurrentInstruction");
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// What is the current PC?
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TUint32 pc;
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ReturnIfError(CurrentPC(aThread,pc));
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// Read it one byte at a time to ensure alignment doesn't matter
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TUint32 inst = 0;
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for(TInt i=3;i>=0;i--)
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{
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TBuf8<1> instruction;
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TInt err = iChannel->DoReadMemory(aThread, (pc+i), 1, instruction);
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if (KErrNone != err)
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{
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LOG_MSG2("DRMDStepping::CurrentInstruction : Failed to read memory at current PC: return 0x%08x",pc);
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return err;
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}
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inst = (inst << 8) | (*(TUint8 *)instruction.Ptr());
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}
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aInstruction = inst;
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LOG_MSG2("DRMDStepping::CurrentInstruction 0x%08x", aInstruction);
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return KErrNone;
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}
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//
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// DRMDStepping::CurrentArchMode
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//
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// Determines architecture mode from the supplied cpsr
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TInt DRMDStepping::CurrentArchMode(const TUint32 aCpsr, Debug::TArchitectureMode& aMode)
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{
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// Thumb2 work will depend on having a suitable cpu architecture to compile for...
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#ifdef ECpuJf
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// State table as per ARM ARM DDI0406A, section A.2.5.1
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if(aCpsr & ECpuJf)
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{
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if (aCpsr & ECpuThumb)
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{
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// ThumbEE (Thumb2)
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aMode = Debug::EThumb2EEMode;
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}
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else
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{
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// Jazelle mode - not supported
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return KErrNotSupported;
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}
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}
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else
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#endif
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{
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if (aCpsr & ECpuThumb)
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{
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// Thumb mode
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aMode = Debug::EThumbMode;
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}
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else
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{
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// ARM mode
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aMode = Debug::EArmMode;
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}
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}
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return KErrNone;
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}
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//
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// DRMDStepping::PCAfterInstructionExecutes
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//
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// Note, this function pretty much ignores all the arguments except for aThread.
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// The arguments continue to exist so that the function has the same prototype as
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// the original from Nokia. In the long term this function will be re-factored
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sl@0
|
315 |
// to remove obsolete parameters.
|
|
sl@0
|
316 |
//
|
|
sl@0
|
317 |
TUint32 DRMDStepping::PCAfterInstructionExecutes(DThread *aThread, TUint32 aCurrentPC, TUint32 aStatusRegister, TInt aInstSize, /*TBool aStepInto,*/ TUint32 &aNewRangeEnd, TBool &aChangingModes)
|
|
sl@0
|
318 |
{
|
|
sl@0
|
319 |
LOG_MSG("DRMDStepping::PCAfterInstructionExecutes()");
|
|
sl@0
|
320 |
|
|
sl@0
|
321 |
// by default we will set the breakpoint at the next instruction
|
|
sl@0
|
322 |
TUint32 breakAddress = aCurrentPC + aInstSize;
|
|
sl@0
|
323 |
|
|
sl@0
|
324 |
TInt err = KErrNone;
|
|
sl@0
|
325 |
|
|
sl@0
|
326 |
// determine the architecture
|
|
sl@0
|
327 |
TUint32 cpuid;
|
|
sl@0
|
328 |
asm("mrc p15, 0, cpuid, c0, c0, 0 ");
|
|
sl@0
|
329 |
LOG_MSG2("DRMDStepping::PCAfterInstructionExecutes() - cpuid = 0x%08x\n",cpuid);
|
|
sl@0
|
330 |
|
|
sl@0
|
331 |
cpuid >>= 8;
|
|
sl@0
|
332 |
cpuid &= 0xFF;
|
|
sl@0
|
333 |
|
|
sl@0
|
334 |
// determine the architecture mode for the current instruction
|
|
sl@0
|
335 |
TArchitectureMode mode = EArmMode; // Default assumption is ARM
|
|
sl@0
|
336 |
|
|
sl@0
|
337 |
// Now we must examine the CPSR to read the T and J bits. See ARM ARM DDI0406A, section B1.3.3
|
|
sl@0
|
338 |
TUint32 cpsr;
|
|
sl@0
|
339 |
|
|
sl@0
|
340 |
ReturnIfError(CurrentCPSR(aThread,cpsr));
|
|
sl@0
|
341 |
LOG_MSG2("DRMDStepping::PCAfterInstructionExecutes() - cpsr = 0x%08x\n",cpsr);
|
|
sl@0
|
342 |
|
|
sl@0
|
343 |
// Determine the mode
|
|
sl@0
|
344 |
ReturnIfError(CurrentArchMode(cpsr,mode));
|
|
sl@0
|
345 |
|
|
sl@0
|
346 |
// Decode instruction based on current CPU mode
|
|
sl@0
|
347 |
switch(mode)
|
|
sl@0
|
348 |
{
|
|
sl@0
|
349 |
case Debug::EArmMode:
|
|
sl@0
|
350 |
{
|
|
sl@0
|
351 |
// Obtain the current instruction bit pattern
|
|
sl@0
|
352 |
TUint32 inst;
|
|
sl@0
|
353 |
ReturnIfError(CurrentInstruction(aThread,inst));
|
|
sl@0
|
354 |
|
|
sl@0
|
355 |
LOG_MSG2("Current instruction: %x", inst);
|
|
sl@0
|
356 |
|
|
sl@0
|
357 |
// check the conditions to see if this will actually get executed
|
|
sl@0
|
358 |
if (IsExecuted(((inst>>28) & 0x0000000F), aStatusRegister))
|
|
sl@0
|
359 |
{
|
|
sl@0
|
360 |
switch(arm_opcode(inst)) // bits 27-25
|
|
sl@0
|
361 |
{
|
|
sl@0
|
362 |
case 0:
|
|
sl@0
|
363 |
{
|
|
sl@0
|
364 |
switch((inst & 0x00000010) >> 4) // bit 4
|
|
sl@0
|
365 |
{
|
|
sl@0
|
366 |
case 0:
|
|
sl@0
|
367 |
{
|
|
sl@0
|
368 |
switch((inst & 0x01800000) >> 23) // bits 24-23
|
|
sl@0
|
369 |
{
|
|
sl@0
|
370 |
case 2:
|
|
sl@0
|
371 |
{
|
|
sl@0
|
372 |
// move to/from status register. pc updates not allowed
|
|
sl@0
|
373 |
// or TST, TEQ, CMP, CMN which don't modify the PC
|
|
sl@0
|
374 |
break;
|
|
sl@0
|
375 |
}
|
|
sl@0
|
376 |
default:
|
|
sl@0
|
377 |
{
|
|
sl@0
|
378 |
// Data processing immediate shift
|
|
sl@0
|
379 |
if (arm_rd(inst) == PC_REGISTER)
|
|
sl@0
|
380 |
{
|
|
sl@0
|
381 |
TUint32 rn = aCurrentPC + 8;
|
|
sl@0
|
382 |
if (arm_rn(inst) != PC_REGISTER) // bits 19-16
|
|
sl@0
|
383 |
{
|
|
sl@0
|
384 |
err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn);
|
|
sl@0
|
385 |
if(err != KErrNone)
|
|
sl@0
|
386 |
{
|
|
sl@0
|
387 |
LOG_MSG2("Non-zero error code discarded: %d", err);
|
|
sl@0
|
388 |
}
|
|
sl@0
|
389 |
}
|
|
sl@0
|
390 |
|
|
sl@0
|
391 |
TUint32 shifter = ShiftedRegValue(aThread, inst, aCurrentPC, aStatusRegister);
|
|
sl@0
|
392 |
|
|
sl@0
|
393 |
DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress);
|
|
sl@0
|
394 |
}
|
|
sl@0
|
395 |
break;
|
|
sl@0
|
396 |
}
|
|
sl@0
|
397 |
}
|
|
sl@0
|
398 |
break;
|
|
sl@0
|
399 |
}
|
|
sl@0
|
400 |
case 1:
|
|
sl@0
|
401 |
{
|
|
sl@0
|
402 |
switch((inst & 0x00000080) >> 7) // bit 7
|
|
sl@0
|
403 |
{
|
|
sl@0
|
404 |
case 0:
|
|
sl@0
|
405 |
{
|
|
sl@0
|
406 |
switch((inst & 0x01900000) >> 20) // bits 24-23 and bit 20
|
|
sl@0
|
407 |
{
|
|
sl@0
|
408 |
case 0x10:
|
|
sl@0
|
409 |
{
|
|
sl@0
|
410 |
// from figure 3-3
|
|
sl@0
|
411 |
switch((inst & 0x000000F0) >> 4) // bits 7-4
|
|
sl@0
|
412 |
{
|
|
sl@0
|
413 |
case 1:
|
|
sl@0
|
414 |
{
|
|
sl@0
|
415 |
if (((inst & 0x00400000) >> 22) == 0) // bit 22
|
|
sl@0
|
416 |
{
|
|
sl@0
|
417 |
// BX
|
|
sl@0
|
418 |
// this is a strange case. normally this is used in the epilogue to branch the the link
|
|
sl@0
|
419 |
// register. sometimes it is used to call a function, and the LR is stored in the previous
|
|
sl@0
|
420 |
// instruction. since what we want to do is different for the two cases when stepping over,
|
|
sl@0
|
421 |
// we need to read the previous instruction to see what we should do
|
|
sl@0
|
422 |
err = iChannel->ReadKernelRegisterValue(aThread, (inst & 0x0000000F), breakAddress);
|
|
sl@0
|
423 |
if(err != KErrNone)
|
|
sl@0
|
424 |
{
|
|
sl@0
|
425 |
LOG_MSG2("Non-zero error code discarded: %d", err);
|
|
sl@0
|
426 |
}
|
|
sl@0
|
427 |
|
|
sl@0
|
428 |
if ((breakAddress & 0x00000001) == 1)
|
|
sl@0
|
429 |
{
|
|
sl@0
|
430 |
aChangingModes = ETrue;
|
|
sl@0
|
431 |
}
|
|
sl@0
|
432 |
|
|
sl@0
|
433 |
breakAddress &= 0xFFFFFFFE;
|
|
sl@0
|
434 |
}
|
|
sl@0
|
435 |
break;
|
|
sl@0
|
436 |
}
|
|
sl@0
|
437 |
case 3:
|
|
sl@0
|
438 |
{
|
|
sl@0
|
439 |
// BLX
|
|
sl@0
|
440 |
{
|
|
sl@0
|
441 |
err = iChannel->ReadKernelRegisterValue(aThread, (inst & 0x0000000F), breakAddress);
|
|
sl@0
|
442 |
if(err != KErrNone)
|
|
sl@0
|
443 |
{
|
|
sl@0
|
444 |
LOG_MSG2("Non-zero error code discarded: %d", err);
|
|
sl@0
|
445 |
}
|
|
sl@0
|
446 |
|
|
sl@0
|
447 |
if ((breakAddress & 0x00000001) == 1)
|
|
sl@0
|
448 |
{
|
|
sl@0
|
449 |
aChangingModes = ETrue;
|
|
sl@0
|
450 |
}
|
|
sl@0
|
451 |
|
|
sl@0
|
452 |
breakAddress &= 0xFFFFFFFE;
|
|
sl@0
|
453 |
}
|
|
sl@0
|
454 |
break;
|
|
sl@0
|
455 |
}
|
|
sl@0
|
456 |
default:
|
|
sl@0
|
457 |
{
|
|
sl@0
|
458 |
// either doesn't modify the PC or it is illegal to
|
|
sl@0
|
459 |
break;
|
|
sl@0
|
460 |
}
|
|
sl@0
|
461 |
}
|
|
sl@0
|
462 |
break;
|
|
sl@0
|
463 |
}
|
|
sl@0
|
464 |
default:
|
|
sl@0
|
465 |
{
|
|
sl@0
|
466 |
// Data processing register shift
|
|
sl@0
|
467 |
if (((inst & 0x01800000) >> 23) == 2) // bits 24-23
|
|
sl@0
|
468 |
{
|
|
sl@0
|
469 |
// TST, TEQ, CMP, CMN don't modify the PC
|
|
sl@0
|
470 |
}
|
|
sl@0
|
471 |
else if (arm_rd(inst) == PC_REGISTER)
|
|
sl@0
|
472 |
{
|
|
sl@0
|
473 |
// destination register is the PC
|
|
sl@0
|
474 |
TUint32 rn = aCurrentPC + 8;
|
|
sl@0
|
475 |
if (arm_rn(inst) != PC_REGISTER) // bits 19-16
|
|
sl@0
|
476 |
{
|
|
sl@0
|
477 |
err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn);
|
|
sl@0
|
478 |
if(err != KErrNone)
|
|
sl@0
|
479 |
{
|
|
sl@0
|
480 |
LOG_MSG2("Non-zero error code discarded: %d", err);
|
|
sl@0
|
481 |
}
|
|
sl@0
|
482 |
}
|
|
sl@0
|
483 |
|
|
sl@0
|
484 |
TUint32 shifter = ShiftedRegValue(aThread, inst, aCurrentPC, aStatusRegister);
|
|
sl@0
|
485 |
|
|
sl@0
|
486 |
DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress);
|
|
sl@0
|
487 |
}
|
|
sl@0
|
488 |
break;
|
|
sl@0
|
489 |
}
|
|
sl@0
|
490 |
}
|
|
sl@0
|
491 |
break;
|
|
sl@0
|
492 |
}
|
|
sl@0
|
493 |
default:
|
|
sl@0
|
494 |
{
|
|
sl@0
|
495 |
// from figure 3-2, updates to the PC illegal
|
|
sl@0
|
496 |
break;
|
|
sl@0
|
497 |
}
|
|
sl@0
|
498 |
}
|
|
sl@0
|
499 |
break;
|
|
sl@0
|
500 |
}
|
|
sl@0
|
501 |
}
|
|
sl@0
|
502 |
break;
|
|
sl@0
|
503 |
}
|
|
sl@0
|
504 |
case 1:
|
|
sl@0
|
505 |
{
|
|
sl@0
|
506 |
if (((inst & 0x01800000) >> 23) == 2) // bits 24-23
|
|
sl@0
|
507 |
{
|
|
sl@0
|
508 |
// cannot modify the PC
|
|
sl@0
|
509 |
break;
|
|
sl@0
|
510 |
}
|
|
sl@0
|
511 |
else if (arm_rd(inst) == PC_REGISTER)
|
|
sl@0
|
512 |
{
|
|
sl@0
|
513 |
// destination register is the PC
|
|
sl@0
|
514 |
TUint32 rn;
|
|
sl@0
|
515 |
err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn); // bits 19-16
|
|
sl@0
|
516 |
if(err != KErrNone)
|
|
sl@0
|
517 |
{
|
|
sl@0
|
518 |
LOG_MSG2("Non-zero error code discarded: %d", err);
|
|
sl@0
|
519 |
}
|
|
sl@0
|
520 |
TUint32 shifter = ((arm_data_imm(inst) >> arm_data_rot(inst)) | (arm_data_imm(inst) << (32 - arm_data_rot(inst)))) & 0xffffffff;
|
|
sl@0
|
521 |
|
|
sl@0
|
522 |
DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress);
|
|
sl@0
|
523 |
}
|
|
sl@0
|
524 |
break;
|
|
sl@0
|
525 |
}
|
|
sl@0
|
526 |
case 2:
|
|
sl@0
|
527 |
{
|
|
sl@0
|
528 |
// load/store immediate offset
|
|
sl@0
|
529 |
if (arm_load(inst)) // bit 20
|
|
sl@0
|
530 |
{
|
|
sl@0
|
531 |
// loading a register from memory
|
|
sl@0
|
532 |
if (arm_rd(inst) == PC_REGISTER)
|
|
sl@0
|
533 |
{
|
|
sl@0
|
534 |
// loading the PC register
|
|
sl@0
|
535 |
TUint32 base;
|
|
sl@0
|
536 |
err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), base);
|
|
sl@0
|
537 |
if(err != KErrNone)
|
|
sl@0
|
538 |
{
|
|
sl@0
|
539 |
LOG_MSG2("Non-zero error code discarded: %d", err);
|
|
sl@0
|
540 |
}
|
|
sl@0
|
541 |
|
|
sl@0
|
542 |
/* Note: At runtime the PC would be 8 further on
|
|
sl@0
|
543 |
*/
|
|
sl@0
|
544 |
if (arm_rn(inst) == PC_REGISTER)
|
|
sl@0
|
545 |
{
|
|
sl@0
|
546 |
base = aCurrentPC + 8;
|
|
sl@0
|
547 |
}
|
|
sl@0
|
548 |
|
|
sl@0
|
549 |
TUint32 offset = 0;
|
|
sl@0
|
550 |
|
|
sl@0
|
551 |
if (arm_single_pre(inst))
|
|
sl@0
|
552 |
{
|
|
sl@0
|
553 |
// Pre-indexing
|
|
sl@0
|
554 |
offset = arm_single_imm(inst);
|
|
sl@0
|
555 |
|
|
sl@0
|
556 |
if (arm_single_u(inst))
|
|
sl@0
|
557 |
{
|
|
sl@0
|
558 |
base += offset;
|
|
sl@0
|
559 |
}
|
|
sl@0
|
560 |
else
|
|
sl@0
|
561 |
{
|
|
sl@0
|
562 |
base -= offset;
|
|
sl@0
|
563 |
}
|
|
sl@0
|
564 |
}
|
|
sl@0
|
565 |
|
|
sl@0
|
566 |
TBuf8<4> destination;
|
|
sl@0
|
567 |
err = iChannel->DoReadMemory(aThread, base, 4, destination);
|
|
sl@0
|
568 |
|
|
sl@0
|
569 |
if (KErrNone == err)
|
|
sl@0
|
570 |
{
|
|
sl@0
|
571 |
breakAddress = *(TUint32 *)destination.Ptr();
|
|
sl@0
|
572 |
|
|
sl@0
|
573 |
if ((breakAddress & 0x00000001) == 1)
|
|
sl@0
|
574 |
{
|
|
sl@0
|
575 |
aChangingModes = ETrue;
|
|
sl@0
|
576 |
}
|
|
sl@0
|
577 |
breakAddress &= 0xFFFFFFFE;
|
|
sl@0
|
578 |
}
|
|
sl@0
|
579 |
else
|
|
sl@0
|
580 |
{
|
|
sl@0
|
581 |
LOG_MSG("Error reading memory in decoding step instruction");
|
|
sl@0
|
582 |
}
|
|
sl@0
|
583 |
}
|
|
sl@0
|
584 |
}
|
|
sl@0
|
585 |
break;
|
|
sl@0
|
586 |
}
|
|
sl@0
|
587 |
case 3:
|
|
sl@0
|
588 |
{
|
|
sl@0
|
589 |
if (((inst & 0xF0000000) != 0xF0000000) && ((inst & 0x00000010) == 0))
|
|
sl@0
|
590 |
{
|
|
sl@0
|
591 |
// load/store register offset
|
|
sl@0
|
592 |
if (arm_load(inst)) // bit 20
|
|
sl@0
|
593 |
{
|
|
sl@0
|
594 |
// loading a register from memory
|
|
sl@0
|
595 |
if (arm_rd(inst) == PC_REGISTER)
|
|
sl@0
|
596 |
{
|
|
sl@0
|
597 |
// loading the PC register
|
|
sl@0
|
598 |
TUint32 base = 0;
|
|
sl@0
|
599 |
if(arm_rn(inst) == PC_REGISTER)
|
|
sl@0
|
600 |
{
|
|
sl@0
|
601 |
base = aCurrentPC + 8;
|
|
sl@0
|
602 |
}
|
|
sl@0
|
603 |
else
|
|
sl@0
|
604 |
{
|
|
sl@0
|
605 |
err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), base);
|
|
sl@0
|
606 |
if(err != KErrNone)
|
|
sl@0
|
607 |
{
|
|
sl@0
|
608 |
LOG_MSG2("Non-zero error code discarded: %d", err);
|
|
sl@0
|
609 |
}
|
|
sl@0
|
610 |
}
|
|
sl@0
|
611 |
|
|
sl@0
|
612 |
TUint32 offset = 0;
|
|
sl@0
|
613 |
|
|
sl@0
|
614 |
if (arm_single_pre(inst))
|
|
sl@0
|
615 |
{
|
|
sl@0
|
616 |
offset = ShiftedRegValue(aThread, inst, aCurrentPC, aStatusRegister);
|
|
sl@0
|
617 |
|
|
sl@0
|
618 |
if (arm_single_u(inst))
|
|
sl@0
|
619 |
{
|
|
sl@0
|
620 |
base += offset;
|
|
sl@0
|
621 |
}
|
|
sl@0
|
622 |
else
|
|
sl@0
|
623 |
{
|
|
sl@0
|
624 |
base -= offset;
|
|
sl@0
|
625 |
}
|
|
sl@0
|
626 |
}
|
|
sl@0
|
627 |
|
|
sl@0
|
628 |
TBuf8<4> destination;
|
|
sl@0
|
629 |
err = iChannel->DoReadMemory(aThread, base, 4, destination);
|
|
sl@0
|
630 |
|
|
sl@0
|
631 |
if (KErrNone == err)
|
|
sl@0
|
632 |
{
|
|
sl@0
|
633 |
breakAddress = *(TUint32 *)destination.Ptr();
|
|
sl@0
|
634 |
|
|
sl@0
|
635 |
if ((breakAddress & 0x00000001) == 1)
|
|
sl@0
|
636 |
{
|
|
sl@0
|
637 |
aChangingModes = ETrue;
|
|
sl@0
|
638 |
}
|
|
sl@0
|
639 |
breakAddress &= 0xFFFFFFFE;
|
|
sl@0
|
640 |
}
|
|
sl@0
|
641 |
else
|
|
sl@0
|
642 |
{
|
|
sl@0
|
643 |
LOG_MSG("Error reading memory in decoding step instruction");
|
|
sl@0
|
644 |
}
|
|
sl@0
|
645 |
}
|
|
sl@0
|
646 |
}
|
|
sl@0
|
647 |
}
|
|
sl@0
|
648 |
break;
|
|
sl@0
|
649 |
}
|
|
sl@0
|
650 |
case 4:
|
|
sl@0
|
651 |
{
|
|
sl@0
|
652 |
if ((inst & 0xF0000000) != 0xF0000000)
|
|
sl@0
|
653 |
{
|
|
sl@0
|
654 |
// load/store multiple
|
|
sl@0
|
655 |
if (arm_load(inst)) // bit 20
|
|
sl@0
|
656 |
{
|
|
sl@0
|
657 |
// loading a register from memory
|
|
sl@0
|
658 |
if (((inst & 0x00008000) >> 15))
|
|
sl@0
|
659 |
{
|
|
sl@0
|
660 |
// loading the PC register
|
|
sl@0
|
661 |
TInt offset = 0;
|
|
sl@0
|
662 |
if (arm_block_u(inst))
|
|
sl@0
|
663 |
{
|
|
sl@0
|
664 |
TUint32 reglist = arm_block_reglist(inst);
|
|
sl@0
|
665 |
offset = iChannel->Bitcount(reglist) * 4 - 4;
|
|
sl@0
|
666 |
if (arm_block_pre(inst))
|
|
sl@0
|
667 |
offset += 4;
|
|
sl@0
|
668 |
}
|
|
sl@0
|
669 |
else if (arm_block_pre(inst))
|
|
sl@0
|
670 |
{
|
|
sl@0
|
671 |
offset = -4;
|
|
sl@0
|
672 |
}
|
|
sl@0
|
673 |
|
|
sl@0
|
674 |
TUint32 temp = 0;
|
|
sl@0
|
675 |
err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), temp);
|
|
sl@0
|
676 |
if(err != KErrNone)
|
|
sl@0
|
677 |
{
|
|
sl@0
|
678 |
LOG_MSG2("Non-zero error code discarded: %d", err);
|
|
sl@0
|
679 |
}
|
|
sl@0
|
680 |
|
|
sl@0
|
681 |
temp += offset;
|
|
sl@0
|
682 |
|
|
sl@0
|
683 |
TBuf8<4> destination;
|
|
sl@0
|
684 |
err = iChannel->DoReadMemory(aThread, temp, 4, destination);
|
|
sl@0
|
685 |
|
|
sl@0
|
686 |
if (KErrNone == err)
|
|
sl@0
|
687 |
{
|
|
sl@0
|
688 |
breakAddress = *(TUint32 *)destination.Ptr();
|
|
sl@0
|
689 |
if ((breakAddress & 0x00000001) == 1)
|
|
sl@0
|
690 |
{
|
|
sl@0
|
691 |
aChangingModes = ETrue;
|
|
sl@0
|
692 |
}
|
|
sl@0
|
693 |
breakAddress &= 0xFFFFFFFE;
|
|
sl@0
|
694 |
}
|
|
sl@0
|
695 |
else
|
|
sl@0
|
696 |
{
|
|
sl@0
|
697 |
LOG_MSG("Error reading memory in decoding step instruction");
|
|
sl@0
|
698 |
}
|
|
sl@0
|
699 |
}
|
|
sl@0
|
700 |
}
|
|
sl@0
|
701 |
}
|
|
sl@0
|
702 |
break;
|
|
sl@0
|
703 |
}
|
|
sl@0
|
704 |
case 5:
|
|
sl@0
|
705 |
{
|
|
sl@0
|
706 |
if ((inst & 0xF0000000) == 0xF0000000)
|
|
sl@0
|
707 |
{
|
|
sl@0
|
708 |
// BLX
|
|
sl@0
|
709 |
{
|
|
sl@0
|
710 |
breakAddress = (TUint32)arm_instr_b_dest(inst, aCurrentPC);
|
|
sl@0
|
711 |
|
|
sl@0
|
712 |
// Unconditionally change into Thumb mode
|
|
sl@0
|
713 |
aChangingModes = ETrue;
|
|
sl@0
|
714 |
|
|
sl@0
|
715 |
breakAddress &= 0xFFFFFFFE;
|
|
sl@0
|
716 |
}
|
|
sl@0
|
717 |
}
|
|
sl@0
|
718 |
else
|
|
sl@0
|
719 |
{
|
|
sl@0
|
720 |
if ((inst & 0x01000000)) // bit 24
|
|
sl@0
|
721 |
{
|
|
sl@0
|
722 |
// BL
|
|
sl@0
|
723 |
{
|
|
sl@0
|
724 |
breakAddress = (TUint32)arm_instr_b_dest(inst, aCurrentPC);
|
|
sl@0
|
725 |
}
|
|
sl@0
|
726 |
}
|
|
sl@0
|
727 |
else
|
|
sl@0
|
728 |
{
|
|
sl@0
|
729 |
// B
|
|
sl@0
|
730 |
breakAddress = (TUint32)arm_instr_b_dest(inst, aCurrentPC);
|
|
sl@0
|
731 |
}
|
|
sl@0
|
732 |
}
|
|
sl@0
|
733 |
break;
|
|
sl@0
|
734 |
}
|
|
sl@0
|
735 |
}
|
|
sl@0
|
736 |
}
|
|
sl@0
|
737 |
}
|
|
sl@0
|
738 |
break;
|
|
sl@0
|
739 |
|
|
sl@0
|
740 |
case Debug::EThumbMode:
|
|
sl@0
|
741 |
{
|
|
sl@0
|
742 |
// Thumb Mode
|
|
sl@0
|
743 |
//
|
|
sl@0
|
744 |
// Notes: This now includes the extra code
|
|
sl@0
|
745 |
// required to decode V6T2 instructions
|
|
sl@0
|
746 |
|
|
sl@0
|
747 |
LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Thumb Instruction");
|
|
sl@0
|
748 |
|
|
sl@0
|
749 |
TUint16 inst;
|
|
sl@0
|
750 |
|
|
sl@0
|
751 |
// Obtain the current instruction bit pattern
|
|
sl@0
|
752 |
TUint32 inst32;
|
|
sl@0
|
753 |
ReturnIfError(CurrentInstruction(aThread,inst32));
|
|
sl@0
|
754 |
|
|
sl@0
|
755 |
inst = static_cast<TUint16>(inst32 & 0xFFFF);
|
|
sl@0
|
756 |
|
|
sl@0
|
757 |
LOG_MSG2("Current Thumb instruction: 0x%x", inst);
|
|
sl@0
|
758 |
|
|
sl@0
|
759 |
// v6T2 instructions
|
|
sl@0
|
760 |
|
|
sl@0
|
761 |
// Note: v6T2 decoding is only enabled for DEBUG builds or if using an
|
|
sl@0
|
762 |
// an ARM_V6T2 supporting build system. At the time of writing, no
|
|
sl@0
|
763 |
// ARM_V6T2 supporting build system exists, so the stepping code cannot
|
|
sl@0
|
764 |
// be said to be known to work. Hence it is not run for release builds
|
|
sl@0
|
765 |
|
|
sl@0
|
766 |
TBool use_v6t2_decodings = EFalse;
|
|
sl@0
|
767 |
|
|
sl@0
|
768 |
#if defined(DEBUG) || defined(__ARMV6T2__)
|
|
sl@0
|
769 |
use_v6t2_decodings = ETrue;
|
|
sl@0
|
770 |
|
|
sl@0
|
771 |
#endif
|
|
sl@0
|
772 |
// coverity[dead_error_line]
|
|
sl@0
|
773 |
if (use_v6t2_decodings)
|
|
sl@0
|
774 |
{
|
|
sl@0
|
775 |
// 16-bit encodings
|
|
sl@0
|
776 |
|
|
sl@0
|
777 |
// A6.2.5 Misc 16-bit instructions
|
|
sl@0
|
778 |
// DONE Compare and branch on zero (page A8-66)
|
|
sl@0
|
779 |
// If then hints
|
|
sl@0
|
780 |
|
|
sl@0
|
781 |
// ARM ARM DDI0406A - section A8.6.27 CBNZ, CBZ
|
|
sl@0
|
782 |
//
|
|
sl@0
|
783 |
// Compare and branch on Nonzero and Compare and Branch on Zero.
|
|
sl@0
|
784 |
if ((inst & 0xF500) == 0xB100)
|
|
sl@0
|
785 |
{
|
|
sl@0
|
786 |
LOG_MSG("ARM ARM DDI0406A - section A8.6.27 CBNZ, CBZ");
|
|
sl@0
|
787 |
|
|
sl@0
|
788 |
// Decoding as per ARM ARM description
|
|
sl@0
|
789 |
TUint32 op = (inst & 0x0800) >> 11;
|
|
sl@0
|
790 |
TUint32 i = (inst & 0x0200) >> 9;
|
|
sl@0
|
791 |
TUint32 imm5 = (inst & 0x00F8) >> 3;
|
|
sl@0
|
792 |
TUint32 Rn = inst & 0x0007;
|
|
sl@0
|
793 |
|
|
sl@0
|
794 |
TUint32 imm32 = (i << 6) | (imm5 << 1);
|
|
sl@0
|
795 |
|
|
sl@0
|
796 |
// Obtain value for register Rn
|
|
sl@0
|
797 |
TUint32 RnVal = 0;
|
|
sl@0
|
798 |
ReturnIfError(RegisterValue(aThread,Rn,RnVal));
|
|
sl@0
|
799 |
|
|
sl@0
|
800 |
if (op)
|
|
sl@0
|
801 |
{
|
|
sl@0
|
802 |
// nonzero
|
|
sl@0
|
803 |
if (RnVal != 0x0)
|
|
sl@0
|
804 |
{
|
|
sl@0
|
805 |
// Branch
|
|
sl@0
|
806 |
breakAddress = aCurrentPC + imm32;
|
|
sl@0
|
807 |
}
|
|
sl@0
|
808 |
}
|
|
sl@0
|
809 |
else
|
|
sl@0
|
810 |
{
|
|
sl@0
|
811 |
// zero
|
|
sl@0
|
812 |
if (RnVal == 0x0)
|
|
sl@0
|
813 |
{
|
|
sl@0
|
814 |
// Branch
|
|
sl@0
|
815 |
breakAddress = aCurrentPC + imm32;
|
|
sl@0
|
816 |
}
|
|
sl@0
|
817 |
}
|
|
sl@0
|
818 |
}
|
|
sl@0
|
819 |
|
|
sl@0
|
820 |
// ARM ARM DDI0406A - section A8.6.50 IT
|
|
sl@0
|
821 |
//
|
|
sl@0
|
822 |
// If Then instruction
|
|
sl@0
|
823 |
if ((inst & 0xFF00) == 0xBF00)
|
|
sl@0
|
824 |
{
|
|
sl@0
|
825 |
LOG_MSG("ARM ARM DDI0406A - section A8.6.50 IT");
|
|
sl@0
|
826 |
|
|
sl@0
|
827 |
// Decoding as per ARM ARM description
|
|
sl@0
|
828 |
TUint32 firstcond = inst & 0x00F0 >> 4;
|
|
sl@0
|
829 |
TUint32 mask = inst & 0x000F;
|
|
sl@0
|
830 |
|
|
sl@0
|
831 |
if (firstcond == 0xF)
|
|
sl@0
|
832 |
{
|
|
sl@0
|
833 |
// unpredictable
|
|
sl@0
|
834 |
LOG_MSG("ARM ARM DDI0406A - section A8.6.50 IT - Unpredictable");
|
|
sl@0
|
835 |
break;
|
|
sl@0
|
836 |
}
|
|
sl@0
|
837 |
|
|
sl@0
|
838 |
if ((firstcond == 0xE) && (BitCount(mask) != 1))
|
|
sl@0
|
839 |
{
|
|
sl@0
|
840 |
// unpredictable
|
|
sl@0
|
841 |
LOG_MSG("ARM ARM DDI0406A - section A8.6.50 IT - Unpredictable");
|
|
sl@0
|
842 |
break;
|
|
sl@0
|
843 |
}
|
|
sl@0
|
844 |
|
|
sl@0
|
845 |
// should check if 'in-it-block'
|
|
sl@0
|
846 |
LOG_MSG("Cannot step IT instructions.");
|
|
sl@0
|
847 |
|
|
sl@0
|
848 |
// all the conds are as per Table A8-1 (i.e. the usual 16 cases)
|
|
sl@0
|
849 |
// no idea how to decode the it block 'after-the-fact'
|
|
sl@0
|
850 |
// so probably need to treat instructions in the it block
|
|
sl@0
|
851 |
// as 'may' be executed. So breakpoints at both possible locations
|
|
sl@0
|
852 |
// depending on whether the instruction is executed or not.
|
|
sl@0
|
853 |
|
|
sl@0
|
854 |
// also, how do we know if we have hit a breakpoint whilst 'in' an it block?
|
|
sl@0
|
855 |
// can we check the status registers to find out?
|
|
sl@0
|
856 |
//
|
|
sl@0
|
857 |
// see arm arm page 390.
|
|
sl@0
|
858 |
//
|
|
sl@0
|
859 |
// seems to depend on the itstate field. this also says what the condition code
|
|
sl@0
|
860 |
// actually is, and how many instructions are left in the itblock.
|
|
sl@0
|
861 |
// perhaps we can just totally ignore this state, and always do the two-instruction
|
|
sl@0
|
862 |
// breakpoint thing? Not if there is any possibility that the address target
|
|
sl@0
|
863 |
// would be invalid for the non-taken branch address...
|
|
sl@0
|
864 |
}
|
|
sl@0
|
865 |
|
|
sl@0
|
866 |
|
|
sl@0
|
867 |
// 32-bit encodings.
|
|
sl@0
|
868 |
//
|
|
sl@0
|
869 |
|
|
sl@0
|
870 |
// Load word A6-23
|
|
sl@0
|
871 |
// Data processing instructions a6-28
|
|
sl@0
|
872 |
//
|
|
sl@0
|
873 |
|
|
sl@0
|
874 |
// ARM ARM DDI0406A - section A8.6.26
|
|
sl@0
|
875 |
if (inst32 & 0xFFF0FFFF == 0xE3C08F00)
|
|
sl@0
|
876 |
{
|
|
sl@0
|
877 |
LOG_MSG("ARM ARM DDI0406A - section A8.6.26 - BXJ is not supported");
|
|
sl@0
|
878 |
|
|
sl@0
|
879 |
// Decoding as per ARM ARM description
|
|
sl@0
|
880 |
// TUint32 Rm = inst32 & 0x000F0000; // not needed yet
|
|
sl@0
|
881 |
}
|
|
sl@0
|
882 |
|
|
sl@0
|
883 |
// return from exception... SUBS PC,LR. page b6-25
|
|
sl@0
|
884 |
//
|
|
sl@0
|
885 |
// ARM ARM DDi046A - section B6.1.13 - SUBS PC,LR
|
|
sl@0
|
886 |
//
|
|
sl@0
|
887 |
// Encoding T1
|
|
sl@0
|
888 |
if (inst32 & 0xFFFFFF00 == 0xF3DE8F00)
|
|
sl@0
|
889 |
{
|
|
sl@0
|
890 |
LOG_MSG("ARM ARM DDI0406A - section B6.1.13 - SUBS PC,LR Encoding T1");
|
|
sl@0
|
891 |
|
|
sl@0
|
892 |
// Decoding as per ARM ARM description
|
|
sl@0
|
893 |
TUint32 imm8 = inst32 & 0x000000FF;
|
|
sl@0
|
894 |
TUint32 imm32 = imm8;
|
|
sl@0
|
895 |
|
|
sl@0
|
896 |
// TUint32 register_form = EFalse; // not needed for this decoding
|
|
sl@0
|
897 |
// TUint32 opcode = 0x2; // SUB // not needed for this decoding
|
|
sl@0
|
898 |
TUint32 n = 14;
|
|
sl@0
|
899 |
|
|
sl@0
|
900 |
// Obtain LR
|
|
sl@0
|
901 |
TUint32 lrVal;
|
|
sl@0
|
902 |
ReturnIfError(RegisterValue(aThread,n,lrVal));
|
|
sl@0
|
903 |
|
|
sl@0
|
904 |
TUint32 operand2 = imm32; // always for Encoding T1
|
|
sl@0
|
905 |
|
|
sl@0
|
906 |
TUint32 result = lrVal - operand2;
|
|
sl@0
|
907 |
|
|
sl@0
|
908 |
breakAddress = result;
|
|
sl@0
|
909 |
}
|
|
sl@0
|
910 |
|
|
sl@0
|
911 |
// ARM ARM DDI0406A - section A8.6.16 - B
|
|
sl@0
|
912 |
//
|
|
sl@0
|
913 |
// Branch Encoding T3
|
|
sl@0
|
914 |
if (inst32 & 0xF800D000 == 0xF0008000)
|
|
sl@0
|
915 |
{
|
|
sl@0
|
916 |
LOG_MSG("ARM ARM DDI0406A - section A8.6.16 - B Encoding T3");
|
|
sl@0
|
917 |
|
|
sl@0
|
918 |
// Decoding as per ARM ARM description
|
|
sl@0
|
919 |
TUint32 S = inst32 & 0x04000000 >> 26;
|
|
sl@0
|
920 |
// TUint32 cond = inst32 & 0x03C00000 >> 22; // not needed for this decoding
|
|
sl@0
|
921 |
TUint32 imm6 = inst32 & 0x003F0000 >> 16;
|
|
sl@0
|
922 |
TUint32 J1 = inst32 & 0x00002000 >> 13;
|
|
sl@0
|
923 |
TUint32 J2 = inst32 & 0x00000800 >> 11;
|
|
sl@0
|
924 |
TUint32 imm11 = inst32 & 0x000007FF;
|
|
sl@0
|
925 |
|
|
sl@0
|
926 |
TUint32 imm32 = S ? 0xFFFFFFFF : 0 ;
|
|
sl@0
|
927 |
imm32 = (imm32 << 1) | J2;
|
|
sl@0
|
928 |
imm32 = (imm32 << 1) | J1;
|
|
sl@0
|
929 |
imm32 = (imm32 << 6) | imm6;
|
|
sl@0
|
930 |
imm32 = (imm32 << 11) | imm11;
|
|
sl@0
|
931 |
imm32 = (imm32 << 1) | 0;
|
|
sl@0
|
932 |
|
|
sl@0
|
933 |
breakAddress = aCurrentPC + imm32;
|
|
sl@0
|
934 |
}
|
|
sl@0
|
935 |
|
|
sl@0
|
936 |
// ARM ARM DDI0406A - section A8.6.16 - B
|
|
sl@0
|
937 |
//
|
|
sl@0
|
938 |
// Branch Encoding T4
|
|
sl@0
|
939 |
if (inst32 & 0xF800D000 == 0xF0009000)
|
|
sl@0
|
940 |
{
|
|
sl@0
|
941 |
LOG_MSG("ARM ARM DDI0406A - section A8.6.16 - B");
|
|
sl@0
|
942 |
|
|
sl@0
|
943 |
// Decoding as per ARM ARM description
|
|
sl@0
|
944 |
TUint32 S = inst32 & 0x04000000 >> 26;
|
|
sl@0
|
945 |
TUint32 imm10 = inst32 & 0x03FF0000 >> 16;
|
|
sl@0
|
946 |
TUint32 J1 = inst32 & 0x00002000 >> 12;
|
|
sl@0
|
947 |
TUint32 J2 = inst32 & 0x00000800 >> 11;
|
|
sl@0
|
948 |
TUint32 imm11 = inst32 & 0x000003FF;
|
|
sl@0
|
949 |
|
|
sl@0
|
950 |
TUint32 I1 = !(J1 ^ S);
|
|
sl@0
|
951 |
TUint32 I2 = !(J2 ^ S);
|
|
sl@0
|
952 |
|
|
sl@0
|
953 |
TUint32 imm32 = S ? 0xFFFFFFFF : 0;
|
|
sl@0
|
954 |
imm32 = (imm32 << 1) | S;
|
|
sl@0
|
955 |
imm32 = (imm32 << 1) | I1;
|
|
sl@0
|
956 |
imm32 = (imm32 << 1) | I2;
|
|
sl@0
|
957 |
imm32 = (imm32 << 10) | imm10;
|
|
sl@0
|
958 |
imm32 = (imm32 << 11) | imm11;
|
|
sl@0
|
959 |
imm32 = (imm32 << 1) | 0;
|
|
sl@0
|
960 |
|
|
sl@0
|
961 |
breakAddress = aCurrentPC + imm32;
|
|
sl@0
|
962 |
}
|
|
sl@0
|
963 |
|
|
sl@0
|
964 |
|
|
sl@0
|
965 |
// ARM ARM DDI0406A - section A8.6.225 - TBB, TBH
|
|
sl@0
|
966 |
//
|
|
sl@0
|
967 |
// Table Branch Byte, Table Branch Halfword
|
|
sl@0
|
968 |
if (inst32 & 0xFFF0FFE0 == 0xE8D0F000)
|
|
sl@0
|
969 |
{
|
|
sl@0
|
970 |
LOG_MSG("ARM ARM DDI0406A - section A8.6.225 TBB,TBH Encoding T1");
|
|
sl@0
|
971 |
|
|
sl@0
|
972 |
// Decoding as per ARM ARM description
|
|
sl@0
|
973 |
TUint32 Rn = inst32 & 0x000F0000 >> 16;
|
|
sl@0
|
974 |
TUint32 H = inst32 & 0x00000010 >> 4;
|
|
sl@0
|
975 |
TUint32 Rm = inst32 & 0x0000000F;
|
|
sl@0
|
976 |
|
|
sl@0
|
977 |
// Unpredictable?
|
|
sl@0
|
978 |
if (Rm == 13 || Rm == 15)
|
|
sl@0
|
979 |
{
|
|
sl@0
|
980 |
LOG_MSG("ARM ARM DDI0406A - section A8.6.225 TBB,TBH Encoding T1 - Unpredictable");
|
|
sl@0
|
981 |
break;
|
|
sl@0
|
982 |
}
|
|
sl@0
|
983 |
|
|
sl@0
|
984 |
TUint32 halfwords;
|
|
sl@0
|
985 |
TUint32 address;
|
|
sl@0
|
986 |
ReturnIfError(RegisterValue(aThread,Rn,address));
|
|
sl@0
|
987 |
|
|
sl@0
|
988 |
TUint32 offset;
|
|
sl@0
|
989 |
ReturnIfError(RegisterValue(aThread,Rm,offset));
|
|
sl@0
|
990 |
|
|
sl@0
|
991 |
if (H)
|
|
sl@0
|
992 |
{
|
|
sl@0
|
993 |
|
|
sl@0
|
994 |
address += offset << 1;
|
|
sl@0
|
995 |
}
|
|
sl@0
|
996 |
else
|
|
sl@0
|
997 |
{
|
|
sl@0
|
998 |
address += offset;
|
|
sl@0
|
999 |
}
|
|
sl@0
|
1000 |
|
|
sl@0
|
1001 |
ReturnIfError(ReadMem32(aThread,address,halfwords));
|
|
sl@0
|
1002 |
|
|
sl@0
|
1003 |
breakAddress = aCurrentPC + 2*halfwords;
|
|
sl@0
|
1004 |
break;
|
|
sl@0
|
1005 |
}
|
|
sl@0
|
1006 |
|
|
sl@0
|
1007 |
// ARM ARM DDI0406A - section A8.6.55 - LDMDB, LDMEA
|
|
sl@0
|
1008 |
//
|
|
sl@0
|
1009 |
// LDMDB Encoding T1
|
|
sl@0
|
1010 |
if (inst32 & 0xFFD02000 == 0xE9100000)
|
|
sl@0
|
1011 |
{
|
|
sl@0
|
1012 |
LOG_MSG("ARM ARM DDI0406 - section A8.6.55 LDMDB Encoding T1");
|
|
sl@0
|
1013 |
|
|
sl@0
|
1014 |
// Decoding as per ARM ARM description
|
|
sl@0
|
1015 |
// TUint32 W = inst32 & 0x00200000 >> 21; // Not needed for this encoding
|
|
sl@0
|
1016 |
TUint32 Rn = inst32 & 0x000F0000 >> 16;
|
|
sl@0
|
1017 |
TUint32 P = inst32 & 0x00008000 >> 15;
|
|
sl@0
|
1018 |
TUint32 M = inst32 & 0x00004000 >> 14;
|
|
sl@0
|
1019 |
TUint32 registers = inst32 & 0x00001FFF;
|
|
sl@0
|
1020 |
|
|
sl@0
|
1021 |
//TBool wback = (W == 1); // not needed for this encoding
|
|
sl@0
|
1022 |
|
|
sl@0
|
1023 |
// Unpredictable?
|
|
sl@0
|
1024 |
if (Rn == 15 || BitCount(registers) < 2 || ((P == 1) && (M==1)))
|
|
sl@0
|
1025 |
{
|
|
sl@0
|
1026 |
LOG_MSG("ARM ARM DDI0406 - section A8.6.55 LDMDB Encoding T1 - Unpredictable");
|
|
sl@0
|
1027 |
break;
|
|
sl@0
|
1028 |
}
|
|
sl@0
|
1029 |
|
|
sl@0
|
1030 |
TUint32 address;
|
|
sl@0
|
1031 |
ReturnIfError(RegisterValue(aThread,Rn,address));
|
|
sl@0
|
1032 |
|
|
sl@0
|
1033 |
address -= 4*BitCount(registers);
|
|
sl@0
|
1034 |
|
|
sl@0
|
1035 |
for(TInt i=0; i<15; i++)
|
|
sl@0
|
1036 |
{
|
|
sl@0
|
1037 |
if (IsBitSet(registers,i))
|
|
sl@0
|
1038 |
{
|
|
sl@0
|
1039 |
address +=4;
|
|
sl@0
|
1040 |
}
|
|
sl@0
|
1041 |
}
|
|
sl@0
|
1042 |
|
|
sl@0
|
1043 |
if (IsBitSet(registers,15))
|
|
sl@0
|
1044 |
{
|
|
sl@0
|
1045 |
TUint32 RnVal = 0;
|
|
sl@0
|
1046 |
ReturnIfError(ReadMem32(aThread,address,RnVal));
|
|
sl@0
|
1047 |
|
|
sl@0
|
1048 |
breakAddress = RnVal;
|
|
sl@0
|
1049 |
}
|
|
sl@0
|
1050 |
break;
|
|
sl@0
|
1051 |
}
|
|
sl@0
|
1052 |
|
|
sl@0
|
1053 |
// ARM ARM DDI0406A - section A8.6.121 POP
|
|
sl@0
|
1054 |
//
|
|
sl@0
|
1055 |
// POP.W Encoding T2
|
|
sl@0
|
1056 |
if (inst32 & 0xFFFF2000 == 0xE8BD0000)
|
|
sl@0
|
1057 |
{
|
|
sl@0
|
1058 |
LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T2");
|
|
sl@0
|
1059 |
|
|
sl@0
|
1060 |
// Decoding as per ARM ARM description
|
|
sl@0
|
1061 |
TUint32 registers = inst32 & 0x00001FFF;
|
|
sl@0
|
1062 |
TUint32 P = inst32 & 0x00008000;
|
|
sl@0
|
1063 |
TUint32 M = inst32 & 0x00004000;
|
|
sl@0
|
1064 |
|
|
sl@0
|
1065 |
// Unpredictable?
|
|
sl@0
|
1066 |
if ( (BitCount(registers)<2) || ((P == 1)&&(M == 1)) )
|
|
sl@0
|
1067 |
{
|
|
sl@0
|
1068 |
LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T2 - Unpredictable");
|
|
sl@0
|
1069 |
break;
|
|
sl@0
|
1070 |
}
|
|
sl@0
|
1071 |
|
|
sl@0
|
1072 |
TUint32 address;
|
|
sl@0
|
1073 |
ReturnIfError(RegisterValue(aThread,13,address));
|
|
sl@0
|
1074 |
|
|
sl@0
|
1075 |
for(TInt i=0; i< 15; i++)
|
|
sl@0
|
1076 |
{
|
|
sl@0
|
1077 |
if (IsBitSet(registers,i))
|
|
sl@0
|
1078 |
{
|
|
sl@0
|
1079 |
address += 4;
|
|
sl@0
|
1080 |
}
|
|
sl@0
|
1081 |
}
|
|
sl@0
|
1082 |
|
|
sl@0
|
1083 |
// Is the PC written?
|
|
sl@0
|
1084 |
if (IsBitSet(registers,15))
|
|
sl@0
|
1085 |
{
|
|
sl@0
|
1086 |
// Yes
|
|
sl@0
|
1087 |
ReturnIfError(ReadMem32(aThread,address,breakAddress));
|
|
sl@0
|
1088 |
}
|
|
sl@0
|
1089 |
}
|
|
sl@0
|
1090 |
|
|
sl@0
|
1091 |
// POP Encoding T3
|
|
sl@0
|
1092 |
if (inst32 & 0xFFFF0FFFF == 0xF85D0B04)
|
|
sl@0
|
1093 |
{
|
|
sl@0
|
1094 |
LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T3");
|
|
sl@0
|
1095 |
|
|
sl@0
|
1096 |
// Decoding as per ARM ARM description
|
|
sl@0
|
1097 |
TUint32 Rt = inst32 & 0x0000F000 >> 12;
|
|
sl@0
|
1098 |
TUint32 registers = 1 << Rt;
|
|
sl@0
|
1099 |
|
|
sl@0
|
1100 |
// Unpredictable?
|
|
sl@0
|
1101 |
if (Rt == 13 || Rt == 15)
|
|
sl@0
|
1102 |
{
|
|
sl@0
|
1103 |
LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T3 - Unpredictable");
|
|
sl@0
|
1104 |
break;
|
|
sl@0
|
1105 |
}
|
|
sl@0
|
1106 |
|
|
sl@0
|
1107 |
TUint32 address;
|
|
sl@0
|
1108 |
ReturnIfError(RegisterValue(aThread,13,address));
|
|
sl@0
|
1109 |
|
|
sl@0
|
1110 |
for(TInt i=0; i< 15; i++)
|
|
sl@0
|
1111 |
{
|
|
sl@0
|
1112 |
if (IsBitSet(registers,i))
|
|
sl@0
|
1113 |
{
|
|
sl@0
|
1114 |
address += 4;
|
|
sl@0
|
1115 |
}
|
|
sl@0
|
1116 |
}
|
|
sl@0
|
1117 |
|
|
sl@0
|
1118 |
// Is the PC written?
|
|
sl@0
|
1119 |
if (IsBitSet(registers,15))
|
|
sl@0
|
1120 |
{
|
|
sl@0
|
1121 |
// Yes
|
|
sl@0
|
1122 |
ReturnIfError(ReadMem32(aThread,address,breakAddress));
|
|
sl@0
|
1123 |
}
|
|
sl@0
|
1124 |
|
|
sl@0
|
1125 |
break;
|
|
sl@0
|
1126 |
}
|
|
sl@0
|
1127 |
|
|
sl@0
|
1128 |
// ARM ARM DDI0406A - section A8.6.53 LDM
|
|
sl@0
|
1129 |
//
|
|
sl@0
|
1130 |
// Load Multiple Encoding T2
|
|
sl@0
|
1131 |
if ((inst32 & 0xFFD02000) == 0xE8900000)
|
|
sl@0
|
1132 |
{
|
|
sl@0
|
1133 |
LOG_MSG("ARM ARM DDI0406A - section A8.6.53 LDM Encoding T2");
|
|
sl@0
|
1134 |
|
|
sl@0
|
1135 |
// Decoding as per ARM ARM description
|
|
sl@0
|
1136 |
TUint32 W = inst32 & 0x0020000 >> 21;
|
|
sl@0
|
1137 |
TUint32 Rn = inst32 & 0x000F0000 >> 16;
|
|
sl@0
|
1138 |
TUint32 P = inst32 & 0x00008000 >> 15;
|
|
sl@0
|
1139 |
TUint32 M = inst32 & 0x00004000 >> 14;
|
|
sl@0
|
1140 |
TUint32 registers = inst32 & 0x0000FFFF;
|
|
sl@0
|
1141 |
TUint32 register_list = inst32 & 0x00001FFF;
|
|
sl@0
|
1142 |
|
|
sl@0
|
1143 |
// POP?
|
|
sl@0
|
1144 |
if ( (W == 1) && (Rn == 13) )
|
|
sl@0
|
1145 |
{
|
|
sl@0
|
1146 |
// POP instruction
|
|
sl@0
|
1147 |
LOG_MSG("ARM ARM DDI0406A - section A8.6.53 LDM Encoding T2 - POP");
|
|
sl@0
|
1148 |
}
|
|
sl@0
|
1149 |
|
|
sl@0
|
1150 |
// Unpredictable?
|
|
sl@0
|
1151 |
if (Rn == 15 || BitCount(register_list) < 2 || ((P == 1) && (M == 1)) )
|
|
sl@0
|
1152 |
{
|
|
sl@0
|
1153 |
LOG_MSG("ARM ARM DDI0406A - section A8.6.53 LDM Encoding T2 - Unpredictable");
|
|
sl@0
|
1154 |
break;
|
|
sl@0
|
1155 |
}
|
|
sl@0
|
1156 |
|
|
sl@0
|
1157 |
TUint32 RnVal;
|
|
sl@0
|
1158 |
ReturnIfError(RegisterValue(aThread,Rn,RnVal));
|
|
sl@0
|
1159 |
|
|
sl@0
|
1160 |
TUint32 address = RnVal;
|
|
sl@0
|
1161 |
|
|
sl@0
|
1162 |
// Calculate offset of address
|
|
sl@0
|
1163 |
for(TInt i = 0; i < 15; i++)
|
|
sl@0
|
1164 |
{
|
|
sl@0
|
1165 |
if (IsBitSet(registers,i))
|
|
sl@0
|
1166 |
{
|
|
sl@0
|
1167 |
address += 4;
|
|
sl@0
|
1168 |
}
|
|
sl@0
|
1169 |
}
|
|
sl@0
|
1170 |
|
|
sl@0
|
1171 |
// Does it load the PC?
|
|
sl@0
|
1172 |
if (IsBitSet(registers,15))
|
|
sl@0
|
1173 |
{
|
|
sl@0
|
1174 |
// Obtain the value loaded into the PC
|
|
sl@0
|
1175 |
ReturnIfError(ReadMem32(aThread,address,breakAddress));
|
|
sl@0
|
1176 |
}
|
|
sl@0
|
1177 |
break;
|
|
sl@0
|
1178 |
|
|
sl@0
|
1179 |
}
|
|
sl@0
|
1180 |
|
|
sl@0
|
1181 |
// ARM ARM DDI0406A - section B6.1.8 RFE
|
|
sl@0
|
1182 |
//
|
|
sl@0
|
1183 |
// Return From Exception Encoding T1 RFEDB
|
|
sl@0
|
1184 |
if ((inst32 & 0xFFD0FFFF) == 0xE810C000)
|
|
sl@0
|
1185 |
{
|
|
sl@0
|
1186 |
LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding T1");
|
|
sl@0
|
1187 |
|
|
sl@0
|
1188 |
// Decoding as per ARM ARM description
|
|
sl@0
|
1189 |
// TUint32 W = (inst32 & 0x00200000) >> 21; // not needed for this encoding
|
|
sl@0
|
1190 |
TUint32 Rn = (inst32 & 0x000F0000) >> 16;
|
|
sl@0
|
1191 |
|
|
sl@0
|
1192 |
// TBool wback = (W == 1); // not needed for this encoding
|
|
sl@0
|
1193 |
TBool increment = EFalse;
|
|
sl@0
|
1194 |
TBool wordhigher = EFalse;
|
|
sl@0
|
1195 |
|
|
sl@0
|
1196 |
// Do calculation
|
|
sl@0
|
1197 |
if (Rn == 15)
|
|
sl@0
|
1198 |
{
|
|
sl@0
|
1199 |
// Unpredictable
|
|
sl@0
|
1200 |
LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding T1 - Unpredictable");
|
|
sl@0
|
1201 |
break;
|
|
sl@0
|
1202 |
}
|
|
sl@0
|
1203 |
|
|
sl@0
|
1204 |
TUint32 RnVal = 0;
|
|
sl@0
|
1205 |
ReturnIfError(RegisterValue(aThread,Rn,RnVal));
|
|
sl@0
|
1206 |
|
|
sl@0
|
1207 |
TUint32 address = 0;
|
|
sl@0
|
1208 |
ReturnIfError(ReadMem32(aThread,RnVal,address));
|
|
sl@0
|
1209 |
|
|
sl@0
|
1210 |
if (increment)
|
|
sl@0
|
1211 |
{
|
|
sl@0
|
1212 |
address -= 8;
|
|
sl@0
|
1213 |
}
|
|
sl@0
|
1214 |
|
|
sl@0
|
1215 |
if (wordhigher)
|
|
sl@0
|
1216 |
{
|
|
sl@0
|
1217 |
address += 4;
|
|
sl@0
|
1218 |
}
|
|
sl@0
|
1219 |
|
|
sl@0
|
1220 |
breakAddress = address;
|
|
sl@0
|
1221 |
break;
|
|
sl@0
|
1222 |
}
|
|
sl@0
|
1223 |
|
|
sl@0
|
1224 |
// Return From Exception Encoding T2 RFEIA
|
|
sl@0
|
1225 |
if ((inst32 & 0xFFD0FFFF) == 0xE990C000)
|
|
sl@0
|
1226 |
{
|
|
sl@0
|
1227 |
LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding T2");
|
|
sl@0
|
1228 |
|
|
sl@0
|
1229 |
// Decoding as per ARM ARM description
|
|
sl@0
|
1230 |
// TUint32 W = (inst32 & 0x00200000) >> 21; // not needed for this encoding
|
|
sl@0
|
1231 |
TUint32 Rn = (inst32 & 0x000F0000) >> 16;
|
|
sl@0
|
1232 |
|
|
sl@0
|
1233 |
// TBool wback = (W == 1); // not needed for this encoding
|
|
sl@0
|
1234 |
TBool increment = ETrue;
|
|
sl@0
|
1235 |
TBool wordhigher = EFalse;
|
|
sl@0
|
1236 |
|
|
sl@0
|
1237 |
// Do calculation
|
|
sl@0
|
1238 |
if (Rn == 15)
|
|
sl@0
|
1239 |
{
|
|
sl@0
|
1240 |
// Unpredictable
|
|
sl@0
|
1241 |
LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding T2 - Unpredictable");
|
|
sl@0
|
1242 |
break;
|
|
sl@0
|
1243 |
}
|
|
sl@0
|
1244 |
|
|
sl@0
|
1245 |
TUint32 RnVal = 0;
|
|
sl@0
|
1246 |
ReturnIfError(RegisterValue(aThread,Rn,RnVal));
|
|
sl@0
|
1247 |
|
|
sl@0
|
1248 |
TUint32 address = 0;
|
|
sl@0
|
1249 |
ReturnIfError(ReadMem32(aThread,RnVal,address));
|
|
sl@0
|
1250 |
|
|
sl@0
|
1251 |
if (increment)
|
|
sl@0
|
1252 |
{
|
|
sl@0
|
1253 |
address -= 8;
|
|
sl@0
|
1254 |
}
|
|
sl@0
|
1255 |
|
|
sl@0
|
1256 |
if (wordhigher)
|
|
sl@0
|
1257 |
{
|
|
sl@0
|
1258 |
address += 4;
|
|
sl@0
|
1259 |
}
|
|
sl@0
|
1260 |
|
|
sl@0
|
1261 |
breakAddress = RnVal;
|
|
sl@0
|
1262 |
break;
|
|
sl@0
|
1263 |
}
|
|
sl@0
|
1264 |
|
|
sl@0
|
1265 |
// Return From Exception Encoding A1 RFE<amode>
|
|
sl@0
|
1266 |
if ((inst32 & 0xFE50FFFF) == 0xF8100A00)
|
|
sl@0
|
1267 |
{
|
|
sl@0
|
1268 |
LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding A1");
|
|
sl@0
|
1269 |
|
|
sl@0
|
1270 |
// Decoding as per ARM ARM description
|
|
sl@0
|
1271 |
TUint32 P = (inst32 & 0x01000000) >> 24;
|
|
sl@0
|
1272 |
TUint32 U = (inst32 & 0x00800000) >> 23;
|
|
sl@0
|
1273 |
// TUint32 W = (inst32 & 0x00200000) >> 21; // not needed for this encoding
|
|
sl@0
|
1274 |
TUint32 Rn = (inst32 & 0x000F0000) >> 16;
|
|
sl@0
|
1275 |
|
|
sl@0
|
1276 |
// TBool wback = (W == 1); // not needed for this encoding
|
|
sl@0
|
1277 |
TBool increment = (U == 1);
|
|
sl@0
|
1278 |
TBool wordhigher = (P == U);
|
|
sl@0
|
1279 |
|
|
sl@0
|
1280 |
// Do calculation
|
|
sl@0
|
1281 |
if (Rn == 15)
|
|
sl@0
|
1282 |
{
|
|
sl@0
|
1283 |
// Unpredictable
|
|
sl@0
|
1284 |
LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding A1 - Unpredictable");
|
|
sl@0
|
1285 |
break;
|
|
sl@0
|
1286 |
}
|
|
sl@0
|
1287 |
|
|
sl@0
|
1288 |
TUint32 RnVal = 0;
|
|
sl@0
|
1289 |
ReturnIfError(RegisterValue(aThread,Rn,RnVal));
|
|
sl@0
|
1290 |
|
|
sl@0
|
1291 |
TUint32 address = 0;
|
|
sl@0
|
1292 |
ReturnIfError(ReadMem32(aThread,RnVal,address));
|
|
sl@0
|
1293 |
|
|
sl@0
|
1294 |
if (increment)
|
|
sl@0
|
1295 |
{
|
|
sl@0
|
1296 |
address -= 8;
|
|
sl@0
|
1297 |
}
|
|
sl@0
|
1298 |
|
|
sl@0
|
1299 |
if (wordhigher)
|
|
sl@0
|
1300 |
{
|
|
sl@0
|
1301 |
address += 4;
|
|
sl@0
|
1302 |
}
|
|
sl@0
|
1303 |
|
|
sl@0
|
1304 |
breakAddress = address;
|
|
sl@0
|
1305 |
break;
|
|
sl@0
|
1306 |
}
|
|
sl@0
|
1307 |
}
|
|
sl@0
|
1308 |
|
|
sl@0
|
1309 |
// v4T/v5T/v6T instructions
|
|
sl@0
|
1310 |
switch(thumb_opcode(inst))
|
|
sl@0
|
1311 |
{
|
|
sl@0
|
1312 |
case 0x08:
|
|
sl@0
|
1313 |
{
|
|
sl@0
|
1314 |
// Data-processing. See ARM ARM DDI0406A, section A6-8, A6.2.2.
|
|
sl@0
|
1315 |
|
|
sl@0
|
1316 |
if ((thumb_inst_7_15(inst) == 0x08F))
|
|
sl@0
|
1317 |
{
|
|
sl@0
|
1318 |
// BLX(2)
|
|
sl@0
|
1319 |
err = iChannel->ReadKernelRegisterValue(aThread, ((inst & 0x0078) >> 3), breakAddress);
|
|
sl@0
|
1320 |
if(err != KErrNone)
|
|
sl@0
|
1321 |
{
|
|
sl@0
|
1322 |
LOG_MSG2("Non-zero error code discarded: %d", err);
|
|
sl@0
|
1323 |
}
|
|
sl@0
|
1324 |
|
|
sl@0
|
1325 |
if ((breakAddress & 0x00000001) == 0)
|
|
sl@0
|
1326 |
{
|
|
sl@0
|
1327 |
aChangingModes = ETrue;
|
|
sl@0
|
1328 |
}
|
|
sl@0
|
1329 |
|
|
sl@0
|
1330 |
breakAddress &= 0xFFFFFFFE;
|
|
sl@0
|
1331 |
|
|
sl@0
|
1332 |
// Report how we decoded this instruction
|
|
sl@0
|
1333 |
LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as BLX (2)");
|
|
sl@0
|
1334 |
}
|
|
sl@0
|
1335 |
else if (thumb_inst_7_15(inst) == 0x08E)
|
|
sl@0
|
1336 |
{
|
|
sl@0
|
1337 |
// BX
|
|
sl@0
|
1338 |
err = iChannel->ReadKernelRegisterValue(aThread, ((inst & 0x0078) >> 3), breakAddress);
|
|
sl@0
|
1339 |
if(err != KErrNone)
|
|
sl@0
|
1340 |
{
|
|
sl@0
|
1341 |
LOG_MSG2("Non-zero error code discarded: %d", err);
|
|
sl@0
|
1342 |
}
|
|
sl@0
|
1343 |
|
|
sl@0
|
1344 |
if ((breakAddress & 0x00000001) == 0)
|
|
sl@0
|
1345 |
{
|
|
sl@0
|
1346 |
aChangingModes = ETrue;
|
|
sl@0
|
1347 |
}
|
|
sl@0
|
1348 |
|
|
sl@0
|
1349 |
breakAddress &= 0xFFFFFFFE;
|
|
sl@0
|
1350 |
|
|
sl@0
|
1351 |
// Report how we decoded this instruction
|
|
sl@0
|
1352 |
LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as BX");
|
|
sl@0
|
1353 |
}
|
|
sl@0
|
1354 |
else if ((thumb_inst_8_15(inst) == 0x46) && ((inst & 0x87) == 0x87))
|
|
sl@0
|
1355 |
{
|
|
sl@0
|
1356 |
// MOV with PC as the destination
|
|
sl@0
|
1357 |
err = iChannel->ReadKernelRegisterValue(aThread, ((inst & 0x0078) >> 3), breakAddress);
|
|
sl@0
|
1358 |
if(err != KErrNone)
|
|
sl@0
|
1359 |
{
|
|
sl@0
|
1360 |
LOG_MSG2("Non-zero error code discarded: %d", err);
|
|
sl@0
|
1361 |
}
|
|
sl@0
|
1362 |
|
|
sl@0
|
1363 |
// Report how we decoded this instruction
|
|
sl@0
|
1364 |
LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as MOV with PC as the destination");
|
|
sl@0
|
1365 |
}
|
|
sl@0
|
1366 |
else if ((thumb_inst_8_15(inst) == 0x44) && ((inst & 0x87) == 0x87))
|
|
sl@0
|
1367 |
{
|
|
sl@0
|
1368 |
// ADD with PC as the destination
|
|
sl@0
|
1369 |
err = iChannel->ReadKernelRegisterValue(aThread, ((inst & 0x0078) >> 3), breakAddress);
|
|
sl@0
|
1370 |
if(err != KErrNone)
|
|
sl@0
|
1371 |
{
|
|
sl@0
|
1372 |
LOG_MSG2("Non-zero error code discarded: %d", err);
|
|
sl@0
|
1373 |
}
|
|
sl@0
|
1374 |
breakAddress += aCurrentPC + 4; // +4 because we need to use the PC+4 according to ARM ARM DDI0406A, section A6.1.2.
|
|
sl@0
|
1375 |
|
|
sl@0
|
1376 |
// Report how we decoded this instruction
|
|
sl@0
|
1377 |
LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as ADD with PC as the destination");
|
|
sl@0
|
1378 |
}
|
|
sl@0
|
1379 |
break;
|
|
sl@0
|
1380 |
}
|
|
sl@0
|
1381 |
case 0x13:
|
|
sl@0
|
1382 |
{
|
|
sl@0
|
1383 |
// Load/Store single data item. See ARM ARM DDI0406A, section A6-10
|
|
sl@0
|
1384 |
|
|
sl@0
|
1385 |
//This instruction doesn't modify the PC.
|
|
sl@0
|
1386 |
|
|
sl@0
|
1387 |
//if (thumb_inst_8_15(inst) == 0x9F)
|
|
sl@0
|
1388 |
//{
|
|
sl@0
|
1389 |
// LDR(4) with the PC as the destination
|
|
sl@0
|
1390 |
// breakAddress = ReadRegister(aThread, SP_REGISTER) + (4 * (inst & 0x00FF));
|
|
sl@0
|
1391 |
//}
|
|
sl@0
|
1392 |
|
|
sl@0
|
1393 |
// Report how we decoded this instruction
|
|
sl@0
|
1394 |
LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as This instruction doesn't modify the PC.");
|
|
sl@0
|
1395 |
break;
|
|
sl@0
|
1396 |
}
|
|
sl@0
|
1397 |
case 0x17:
|
|
sl@0
|
1398 |
{
|
|
sl@0
|
1399 |
// Misc 16-bit instruction. See ARM ARM DDI0406A, section A6-11
|
|
sl@0
|
1400 |
|
|
sl@0
|
1401 |
if (thumb_inst_8_15(inst) == 0xBD)
|
|
sl@0
|
1402 |
{
|
|
sl@0
|
1403 |
// POP with the PC in the list
|
|
sl@0
|
1404 |
TUint32 regList = (inst & 0x00FF);
|
|
sl@0
|
1405 |
TInt offset = 0;
|
|
sl@0
|
1406 |
err = iChannel->ReadKernelRegisterValue(aThread, SP_REGISTER, (T4ByteRegisterValue&)offset);
|
|
sl@0
|
1407 |
if(err != KErrNone)
|
|
sl@0
|
1408 |
{
|
|
sl@0
|
1409 |
LOG_MSG2("Non-zero error code discarded: %d", err);
|
|
sl@0
|
1410 |
}
|
|
sl@0
|
1411 |
offset += (iChannel->Bitcount(regList) * 4);
|
|
sl@0
|
1412 |
|
|
sl@0
|
1413 |
TBuf8<4> destination;
|
|
sl@0
|
1414 |
err = iChannel->DoReadMemory(aThread, offset, 4, destination);
|
|
sl@0
|
1415 |
|
|
sl@0
|
1416 |
if (KErrNone == err)
|
|
sl@0
|
1417 |
{
|
|
sl@0
|
1418 |
breakAddress = *(TUint32 *)destination.Ptr();
|
|
sl@0
|
1419 |
|
|
sl@0
|
1420 |
if ((breakAddress & 0x00000001) == 0)
|
|
sl@0
|
1421 |
{
|
|
sl@0
|
1422 |
aChangingModes = ETrue;
|
|
sl@0
|
1423 |
}
|
|
sl@0
|
1424 |
|
|
sl@0
|
1425 |
breakAddress &= 0xFFFFFFFE;
|
|
sl@0
|
1426 |
}
|
|
sl@0
|
1427 |
else
|
|
sl@0
|
1428 |
{
|
|
sl@0
|
1429 |
LOG_MSG("Error reading memory in decoding step instruction");
|
|
sl@0
|
1430 |
}
|
|
sl@0
|
1431 |
|
|
sl@0
|
1432 |
// Report how we decoded this instruction
|
|
sl@0
|
1433 |
LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as POP with the PC in the list");
|
|
sl@0
|
1434 |
}
|
|
sl@0
|
1435 |
break;
|
|
sl@0
|
1436 |
}
|
|
sl@0
|
1437 |
case 0x1A:
|
|
sl@0
|
1438 |
case 0x1B:
|
|
sl@0
|
1439 |
{
|
|
sl@0
|
1440 |
// Conditional branch, and supervisor call. See ARM ARM DDI0406A, section A6-13
|
|
sl@0
|
1441 |
|
|
sl@0
|
1442 |
if (thumb_inst_8_15(inst) < 0xDE)
|
|
sl@0
|
1443 |
{
|
|
sl@0
|
1444 |
// B(1) conditional branch
|
|
sl@0
|
1445 |
if (IsExecuted(((inst & 0x0F00) >> 8), aStatusRegister))
|
|
sl@0
|
1446 |
{
|
|
sl@0
|
1447 |
TUint32 offset = ((inst & 0x000000FF) << 1);
|
|
sl@0
|
1448 |
if (offset & 0x00000100)
|
|
sl@0
|
1449 |
{
|
|
sl@0
|
1450 |
offset |= 0xFFFFFF00;
|
|
sl@0
|
1451 |
}
|
|
sl@0
|
1452 |
|
|
sl@0
|
1453 |
breakAddress = aCurrentPC + 4 + offset;
|
|
sl@0
|
1454 |
|
|
sl@0
|
1455 |
// Report how we decoded this instruction
|
|
sl@0
|
1456 |
LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as B(1) conditional branch");
|
|
sl@0
|
1457 |
}
|
|
sl@0
|
1458 |
}
|
|
sl@0
|
1459 |
break;
|
|
sl@0
|
1460 |
}
|
|
sl@0
|
1461 |
case 0x1C:
|
|
sl@0
|
1462 |
{
|
|
sl@0
|
1463 |
// Unconditional branch, See ARM ARM DDI0406A, section A8-44.
|
|
sl@0
|
1464 |
|
|
sl@0
|
1465 |
// B(2) unconditional branch
|
|
sl@0
|
1466 |
TUint32 offset = (inst & 0x000007FF) << 1;
|
|
sl@0
|
1467 |
if (offset & 0x00000800)
|
|
sl@0
|
1468 |
{
|
|
sl@0
|
1469 |
offset |= 0xFFFFF800;
|
|
sl@0
|
1470 |
}
|
|
sl@0
|
1471 |
|
|
sl@0
|
1472 |
breakAddress = aCurrentPC + 4 + offset;
|
|
sl@0
|
1473 |
|
|
sl@0
|
1474 |
// Report how we decoded this instruction
|
|
sl@0
|
1475 |
LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as B(2) unconditional branch");
|
|
sl@0
|
1476 |
|
|
sl@0
|
1477 |
break;
|
|
sl@0
|
1478 |
}
|
|
sl@0
|
1479 |
case 0x1D:
|
|
sl@0
|
1480 |
{
|
|
sl@0
|
1481 |
if (!(inst & 0x0001))
|
|
sl@0
|
1482 |
{
|
|
sl@0
|
1483 |
// BLX(1)
|
|
sl@0
|
1484 |
err = iChannel->ReadKernelRegisterValue(aThread, LINK_REGISTER, breakAddress);
|
|
sl@0
|
1485 |
if(err != KErrNone)
|
|
sl@0
|
1486 |
{
|
|
sl@0
|
1487 |
LOG_MSG2("Non-zero error code discarded: %d", err);
|
|
sl@0
|
1488 |
}
|
|
sl@0
|
1489 |
breakAddress += ((inst & 0x07FF) << 1);
|
|
sl@0
|
1490 |
if ((breakAddress & 0x00000001) == 0)
|
|
sl@0
|
1491 |
{
|
|
sl@0
|
1492 |
aChangingModes = ETrue;
|
|
sl@0
|
1493 |
}
|
|
sl@0
|
1494 |
|
|
sl@0
|
1495 |
breakAddress &= 0xFFFFFFFC;
|
|
sl@0
|
1496 |
|
|
sl@0
|
1497 |
// Report how we decoded this instruction
|
|
sl@0
|
1498 |
LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as BLX(1)");
|
|
sl@0
|
1499 |
|
|
sl@0
|
1500 |
}
|
|
sl@0
|
1501 |
break;
|
|
sl@0
|
1502 |
}
|
|
sl@0
|
1503 |
case 0x1E:
|
|
sl@0
|
1504 |
{
|
|
sl@0
|
1505 |
// Check for ARMv7 CPU
|
|
sl@0
|
1506 |
if(cpuid == 0xC0)
|
|
sl@0
|
1507 |
{
|
|
sl@0
|
1508 |
// BL/BLX 32-bit instruction
|
|
sl@0
|
1509 |
aNewRangeEnd += 4;
|
|
sl@0
|
1510 |
|
|
sl@0
|
1511 |
breakAddress = (TUint32)thumb_instr_b_dest(inst32, aCurrentPC);
|
|
sl@0
|
1512 |
|
|
sl@0
|
1513 |
if((inst32 >> 27) == 0x1D)
|
|
sl@0
|
1514 |
{
|
|
sl@0
|
1515 |
// BLX(1)
|
|
sl@0
|
1516 |
if ((breakAddress & 0x00000001) == 0)
|
|
sl@0
|
1517 |
{
|
|
sl@0
|
1518 |
aChangingModes = ETrue;
|
|
sl@0
|
1519 |
}
|
|
sl@0
|
1520 |
|
|
sl@0
|
1521 |
breakAddress &= 0xFFFFFFFC;
|
|
sl@0
|
1522 |
|
|
sl@0
|
1523 |
// Report how we decoded this instruction
|
|
sl@0
|
1524 |
LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as 32-bit BLX(1)");
|
|
sl@0
|
1525 |
}
|
|
sl@0
|
1526 |
else
|
|
sl@0
|
1527 |
{
|
|
sl@0
|
1528 |
// Report how we decoded this instruction
|
|
sl@0
|
1529 |
LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: 32-bit BL instruction");
|
|
sl@0
|
1530 |
}
|
|
sl@0
|
1531 |
LOG_MSG2(" 32-bit BL/BLX instruction: breakAddress = 0x%X", breakAddress);
|
|
sl@0
|
1532 |
}
|
|
sl@0
|
1533 |
else
|
|
sl@0
|
1534 |
{
|
|
sl@0
|
1535 |
// BL/BLX prefix - destination is encoded in this and the next instruction
|
|
sl@0
|
1536 |
aNewRangeEnd += 2;
|
|
sl@0
|
1537 |
|
|
sl@0
|
1538 |
// Report how we decoded this instruction
|
|
sl@0
|
1539 |
LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: BL/BLX prefix - destination is encoded in this and the next instruction");
|
|
sl@0
|
1540 |
}
|
|
sl@0
|
1541 |
|
|
sl@0
|
1542 |
|
|
sl@0
|
1543 |
break;
|
|
sl@0
|
1544 |
}
|
|
sl@0
|
1545 |
case 0x1F:
|
|
sl@0
|
1546 |
{
|
|
sl@0
|
1547 |
{
|
|
sl@0
|
1548 |
// BL
|
|
sl@0
|
1549 |
err = iChannel->ReadKernelRegisterValue(aThread, LINK_REGISTER, breakAddress);
|
|
sl@0
|
1550 |
if(err != KErrNone)
|
|
sl@0
|
1551 |
{
|
|
sl@0
|
1552 |
LOG_MSG2("Non-zero error code discarded: %d", err);
|
|
sl@0
|
1553 |
}
|
|
sl@0
|
1554 |
breakAddress += ((inst & 0x07FF) << 1);
|
|
sl@0
|
1555 |
|
|
sl@0
|
1556 |
// Report how we decoded this instruction
|
|
sl@0
|
1557 |
LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as BL");
|
|
sl@0
|
1558 |
}
|
|
sl@0
|
1559 |
break;
|
|
sl@0
|
1560 |
}
|
|
sl@0
|
1561 |
default:
|
|
sl@0
|
1562 |
{
|
|
sl@0
|
1563 |
// Don't know any better at this point!
|
|
sl@0
|
1564 |
LOG_MSG("DRMDStepping::PCAfterInstructionExecutes:- default to next instruction");
|
|
sl@0
|
1565 |
}
|
|
sl@0
|
1566 |
break;
|
|
sl@0
|
1567 |
}
|
|
sl@0
|
1568 |
}
|
|
sl@0
|
1569 |
break;
|
|
sl@0
|
1570 |
|
|
sl@0
|
1571 |
case Debug::EThumb2EEMode:
|
|
sl@0
|
1572 |
{
|
|
sl@0
|
1573 |
// Not yet supported
|
|
sl@0
|
1574 |
LOG_MSG("DRMDStepping::PCAfterInstructionExecutes - Debug::EThumb2Mode is not supported");
|
|
sl@0
|
1575 |
|
|
sl@0
|
1576 |
}
|
|
sl@0
|
1577 |
break;
|
|
sl@0
|
1578 |
|
|
sl@0
|
1579 |
default:
|
|
sl@0
|
1580 |
LOG_MSG("DRMDStepping::PCAfterInstructionExecutes - Cannot determine CPU mode architecture");
|
|
sl@0
|
1581 |
}
|
|
sl@0
|
1582 |
|
|
sl@0
|
1583 |
LOG_MSG2("DRMDStepping::PCAfterInstructionExecutes : return 0x%08x",breakAddress);
|
|
sl@0
|
1584 |
return breakAddress;
|
|
sl@0
|
1585 |
}
|
|
sl@0
|
1586 |
|
|
sl@0
|
1587 |
// Obtain a 32-bit memory value with minimum fuss
|
|
sl@0
|
1588 |
TInt DRMDStepping::ReadMem32(DThread* aThread, const TUint32 aAddress, TUint32& aValue)
|
|
sl@0
|
1589 |
{
|
|
sl@0
|
1590 |
TBuf8<4> valBuf;
|
|
sl@0
|
1591 |
TInt err = iChannel->DoReadMemory(aThread, aAddress, 4, valBuf);
|
|
sl@0
|
1592 |
if (err != KErrNone)
|
|
sl@0
|
1593 |
{
|
|
sl@0
|
1594 |
LOG_MSG2("DRMDStepping::ReadMem32 failed to read memory at 0x%08x", aAddress);
|
|
sl@0
|
1595 |
return err;
|
|
sl@0
|
1596 |
}
|
|
sl@0
|
1597 |
|
|
sl@0
|
1598 |
aValue = *(TUint32 *)valBuf.Ptr();
|
|
sl@0
|
1599 |
|
|
sl@0
|
1600 |
return KErrNone;
|
|
sl@0
|
1601 |
}
|
|
sl@0
|
1602 |
|
|
sl@0
|
1603 |
// Obtain a 16-bit memory value with minimum fuss
|
|
sl@0
|
1604 |
TInt DRMDStepping::ReadMem16(DThread* aThread, const TUint32 aAddress, TUint16& aValue)
|
|
sl@0
|
1605 |
{
|
|
sl@0
|
1606 |
TBuf8<2> valBuf;
|
|
sl@0
|
1607 |
TInt err = iChannel->DoReadMemory(aThread, aAddress, 2, valBuf);
|
|
sl@0
|
1608 |
if (err != KErrNone)
|
|
sl@0
|
1609 |
{
|
|
sl@0
|
1610 |
LOG_MSG2("DRMDStepping::ReadMem16 failed to read memory at 0x%08x", aAddress);
|
|
sl@0
|
1611 |
return err;
|
|
sl@0
|
1612 |
}
|
|
sl@0
|
1613 |
|
|
sl@0
|
1614 |
aValue = *(TUint16 *)valBuf.Ptr();
|
|
sl@0
|
1615 |
|
|
sl@0
|
1616 |
return KErrNone;
|
|
sl@0
|
1617 |
}
|
|
sl@0
|
1618 |
|
|
sl@0
|
1619 |
// Obtain a 16-bit memory value with minimum fuss
|
|
sl@0
|
1620 |
TInt DRMDStepping::ReadMem8(DThread* aThread, const TUint32 aAddress, TUint8& aValue)
|
|
sl@0
|
1621 |
{
|
|
sl@0
|
1622 |
TBuf8<1> valBuf;
|
|
sl@0
|
1623 |
TInt err = iChannel->DoReadMemory(aThread, aAddress, 1, valBuf);
|
|
sl@0
|
1624 |
if (err != KErrNone)
|
|
sl@0
|
1625 |
{
|
|
sl@0
|
1626 |
LOG_MSG2("DRMDStepping::ReadMem8 failed to read memory at 0x%08x", aAddress);
|
|
sl@0
|
1627 |
return err;
|
|
sl@0
|
1628 |
}
|
|
sl@0
|
1629 |
|
|
sl@0
|
1630 |
aValue = *(TUint8 *)valBuf.Ptr();
|
|
sl@0
|
1631 |
|
|
sl@0
|
1632 |
return KErrNone;
|
|
sl@0
|
1633 |
}
|
|
sl@0
|
1634 |
|
|
sl@0
|
1635 |
// Obtain a core register value with minimum fuss
|
|
sl@0
|
1636 |
TInt DRMDStepping::RegisterValue(DThread *aThread, const TUint32 aKernelRegisterId, TUint32 &aValue)
|
|
sl@0
|
1637 |
{
|
|
sl@0
|
1638 |
TInt err = iChannel->ReadKernelRegisterValue(aThread, aKernelRegisterId, aValue);
|
|
sl@0
|
1639 |
if(err != KErrNone)
|
|
sl@0
|
1640 |
{
|
|
sl@0
|
1641 |
LOG_MSG3("DRMDStepping::RegisterValue failed to read register %d err = %d", aKernelRegisterId, err);
|
|
sl@0
|
1642 |
}
|
|
sl@0
|
1643 |
return err;
|
|
sl@0
|
1644 |
}
|
|
sl@0
|
1645 |
|
|
sl@0
|
1646 |
|
|
sl@0
|
1647 |
// Encodings from ARM ARM DDI0406A, section 9.2.1
|
|
sl@0
|
1648 |
enum TThumb2EEOpcode
|
|
sl@0
|
1649 |
{
|
|
sl@0
|
1650 |
EThumb2HDP, // Handler Branch with Parameter
|
|
sl@0
|
1651 |
EThumb2UNDEF, // UNDEFINED
|
|
sl@0
|
1652 |
EThumb2HB, // Handler Branch, Handler Branch with Link
|
|
sl@0
|
1653 |
EThumb2HBLP, // Handle Branch with Link and Parameter
|
|
sl@0
|
1654 |
EThumb2LDRF, // Load Register from a frame
|
|
sl@0
|
1655 |
EThumb2CHKA, // Check Array
|
|
sl@0
|
1656 |
EThumb2LDRL, // Load Register from a literal pool
|
|
sl@0
|
1657 |
EThumb2LDRA, // Load Register (array operations)
|
|
sl@0
|
1658 |
EThumb2STR // Store Register to a frame
|
|
sl@0
|
1659 |
};
|
|
sl@0
|
1660 |
|
|
sl@0
|
1661 |
//
|
|
sl@0
|
1662 |
// DRMDStepping::ShiftedRegValue
|
|
sl@0
|
1663 |
//
|
|
sl@0
|
1664 |
TUint32 DRMDStepping::ShiftedRegValue(DThread *aThread, TUint32 aInstruction, TUint32 aCurrentPC, TUint32 aStatusRegister)
|
|
sl@0
|
1665 |
{
|
|
sl@0
|
1666 |
LOG_MSG("DRM_DebugChannel::ShiftedRegValue()");
|
|
sl@0
|
1667 |
|
|
sl@0
|
1668 |
TUint32 shift = 0;
|
|
sl@0
|
1669 |
if (aInstruction & 0x10) // bit 4
|
|
sl@0
|
1670 |
{
|
|
sl@0
|
1671 |
shift = (arm_rs(aInstruction) == PC_REGISTER ? aCurrentPC + 8 : aStatusRegister) & 0xFF;
|
|
sl@0
|
1672 |
}
|
|
sl@0
|
1673 |
else
|
|
sl@0
|
1674 |
{
|
|
sl@0
|
1675 |
shift = arm_data_c(aInstruction);
|
|
sl@0
|
1676 |
}
|
|
sl@0
|
1677 |
|
|
sl@0
|
1678 |
TInt rm = arm_rm(aInstruction);
|
|
sl@0
|
1679 |
|
|
sl@0
|
1680 |
TUint32 res = 0;
|
|
sl@0
|
1681 |
if(rm == PC_REGISTER)
|
|
sl@0
|
1682 |
{
|
|
sl@0
|
1683 |
res = aCurrentPC + ((aInstruction & 0x10) ? 12 : 8);
|
|
sl@0
|
1684 |
}
|
|
sl@0
|
1685 |
else
|
|
sl@0
|
1686 |
{
|
|
sl@0
|
1687 |
TInt err = iChannel->ReadKernelRegisterValue(aThread, rm, res);
|
|
sl@0
|
1688 |
if(err != KErrNone)
|
|
sl@0
|
1689 |
{
|
|
sl@0
|
1690 |
LOG_MSG2("DRMDStepping::ShiftedRegValue - Non-zero error code discarded: %d", err);
|
|
sl@0
|
1691 |
}
|
|
sl@0
|
1692 |
}
|
|
sl@0
|
1693 |
|
|
sl@0
|
1694 |
switch(arm_data_shift(aInstruction))
|
|
sl@0
|
1695 |
{
|
|
sl@0
|
1696 |
case 0: // LSL
|
|
sl@0
|
1697 |
{
|
|
sl@0
|
1698 |
res = shift >= 32 ? 0 : res << shift;
|
|
sl@0
|
1699 |
break;
|
|
sl@0
|
1700 |
}
|
|
sl@0
|
1701 |
case 1: // LSR
|
|
sl@0
|
1702 |
{
|
|
sl@0
|
1703 |
res = shift >= 32 ? 0 : res >> shift;
|
|
sl@0
|
1704 |
break;
|
|
sl@0
|
1705 |
}
|
|
sl@0
|
1706 |
case 2: // ASR
|
|
sl@0
|
1707 |
{
|
|
sl@0
|
1708 |
if (shift >= 32)
|
|
sl@0
|
1709 |
shift = 31;
|
|
sl@0
|
1710 |
res = ((res & 0x80000000L) ? ~((~res) >> shift) : res >> shift);
|
|
sl@0
|
1711 |
break;
|
|
sl@0
|
1712 |
}
|
|
sl@0
|
1713 |
case 3: // ROR/RRX
|
|
sl@0
|
1714 |
{
|
|
sl@0
|
1715 |
shift &= 31;
|
|
sl@0
|
1716 |
if (shift == 0)
|
|
sl@0
|
1717 |
{
|
|
sl@0
|
1718 |
res = (res >> 1) | ((aStatusRegister & arm_carry_bit()) ? 0x80000000L : 0);
|
|
sl@0
|
1719 |
}
|
|
sl@0
|
1720 |
else
|
|
sl@0
|
1721 |
{
|
|
sl@0
|
1722 |
res = (res >> shift) | (res << (32 - shift));
|
|
sl@0
|
1723 |
}
|
|
sl@0
|
1724 |
break;
|
|
sl@0
|
1725 |
}
|
|
sl@0
|
1726 |
}
|
|
sl@0
|
1727 |
|
|
sl@0
|
1728 |
return res & 0xFFFFFFFF;
|
|
sl@0
|
1729 |
}
|
|
sl@0
|
1730 |
|
|
sl@0
|
1731 |
//
|
|
sl@0
|
1732 |
// DRMDStepping::CurrentPC
|
|
sl@0
|
1733 |
//
|
|
sl@0
|
1734 |
//
|
|
sl@0
|
1735 |
//
|
|
sl@0
|
1736 |
TInt DRMDStepping::CurrentPC(DThread* aThread, TUint32& aPC)
|
|
sl@0
|
1737 |
{
|
|
sl@0
|
1738 |
LOG_MSG("DRMDStepping::CurrentPC");
|
|
sl@0
|
1739 |
|
|
sl@0
|
1740 |
TInt err = iChannel->ReadKernelRegisterValue(aThread, PC_REGISTER, aPC);
|
|
sl@0
|
1741 |
if(err != KErrNone)
|
|
sl@0
|
1742 |
{
|
|
sl@0
|
1743 |
// We don't know the current PC for this thread!
|
|
sl@0
|
1744 |
LOG_MSG("DRMDStepping::CurrentPC - Failed to read the current PC");
|
|
sl@0
|
1745 |
|
|
sl@0
|
1746 |
return KErrGeneral;
|
|
sl@0
|
1747 |
}
|
|
sl@0
|
1748 |
|
|
sl@0
|
1749 |
LOG_MSG2("DRMDStepping::CurrentPC 0x%08x", aPC);
|
|
sl@0
|
1750 |
|
|
sl@0
|
1751 |
return KErrNone;
|
|
sl@0
|
1752 |
}
|
|
sl@0
|
1753 |
|
|
sl@0
|
1754 |
//
|
|
sl@0
|
1755 |
// DRMDStepping::CurrentCPSR
|
|
sl@0
|
1756 |
//
|
|
sl@0
|
1757 |
//
|
|
sl@0
|
1758 |
//
|
|
sl@0
|
1759 |
TInt DRMDStepping::CurrentCPSR(DThread* aThread, TUint32& aCPSR)
|
|
sl@0
|
1760 |
{
|
|
sl@0
|
1761 |
LOG_MSG("DRMDStepping::CurrentCPSR");
|
|
sl@0
|
1762 |
|
|
sl@0
|
1763 |
TInt err = iChannel->ReadKernelRegisterValue(aThread, STATUS_REGISTER, aCPSR);
|
|
sl@0
|
1764 |
if(err != KErrNone)
|
|
sl@0
|
1765 |
{
|
|
sl@0
|
1766 |
// We don't know the current PC for this thread!
|
|
sl@0
|
1767 |
LOG_MSG("DRMDStepping::CurrentPC - Failed to read the current CPSR");
|
|
sl@0
|
1768 |
|
|
sl@0
|
1769 |
return KErrGeneral;
|
|
sl@0
|
1770 |
}
|
|
sl@0
|
1771 |
|
|
sl@0
|
1772 |
LOG_MSG2("DRMDStepping::CurrentCPSR 0x%08x", aCPSR);
|
|
sl@0
|
1773 |
|
|
sl@0
|
1774 |
return KErrNone;
|
|
sl@0
|
1775 |
}
|
|
sl@0
|
1776 |
|
|
sl@0
|
1777 |
//
|
|
sl@0
|
1778 |
// DRMDStepping::ModifyBreaksForStep
|
|
sl@0
|
1779 |
//
|
|
sl@0
|
1780 |
// Set a temporary breakpoint at the next instruction to be executed after the one at the current PC
|
|
sl@0
|
1781 |
// Disable the breakpoint at the current PC if one exists
|
|
sl@0
|
1782 |
//
|
|
sl@0
|
1783 |
TInt DRMDStepping::ModifyBreaksForStep(DThread *aThread, TUint32 aRangeStart, TUint32 aRangeEnd, /*TBool aStepInto,*/ TBool aResumeOnceOutOfRange, TBool aCheckForStubs, const TUint32 aNumSteps)
|
|
sl@0
|
1784 |
{
|
|
sl@0
|
1785 |
LOG_MSG2("DRMDStepping::ModifyBreaksForStep() Numsteps 0x%d",aNumSteps);
|
|
sl@0
|
1786 |
|
|
sl@0
|
1787 |
// Validate arguments
|
|
sl@0
|
1788 |
if (!aThread)
|
|
sl@0
|
1789 |
{
|
|
sl@0
|
1790 |
LOG_MSG("DRMDStepping::ModifyBreaksForStep() - No aThread specified to step");
|
|
sl@0
|
1791 |
return KErrArgument;
|
|
sl@0
|
1792 |
}
|
|
sl@0
|
1793 |
|
|
sl@0
|
1794 |
// Current PC
|
|
sl@0
|
1795 |
TUint32 currentPC;
|
|
sl@0
|
1796 |
|
|
sl@0
|
1797 |
ReturnIfError(CurrentPC(aThread,currentPC));
|
|
sl@0
|
1798 |
LOG_MSG2("Current PC: 0x%x", currentPC);
|
|
sl@0
|
1799 |
|
|
sl@0
|
1800 |
// disable breakpoint at the current PC if necessary
|
|
sl@0
|
1801 |
ReturnIfError(iChannel->iBreakManager->DisableBreakAtAddress(currentPC));
|
|
sl@0
|
1802 |
|
|
sl@0
|
1803 |
// Current CPSR
|
|
sl@0
|
1804 |
TUint32 statusRegister;
|
|
sl@0
|
1805 |
|
|
sl@0
|
1806 |
ReturnIfError(CurrentCPSR(aThread,statusRegister));
|
|
sl@0
|
1807 |
LOG_MSG2("Current CPSR: %x", statusRegister);
|
|
sl@0
|
1808 |
|
|
sl@0
|
1809 |
TBool thumbMode = (statusRegister & ECpuThumb);
|
|
sl@0
|
1810 |
if (thumbMode)
|
|
sl@0
|
1811 |
LOG_MSG("Thumb Mode");
|
|
sl@0
|
1812 |
|
|
sl@0
|
1813 |
TInt instSize = thumbMode ? 2 : 4;
|
|
sl@0
|
1814 |
|
|
sl@0
|
1815 |
TBool changingModes = EFalse;
|
|
sl@0
|
1816 |
|
|
sl@0
|
1817 |
TUint32 breakAddress = 0;
|
|
sl@0
|
1818 |
|
|
sl@0
|
1819 |
TUint32 newRangeEnd = aRangeEnd;
|
|
sl@0
|
1820 |
|
|
sl@0
|
1821 |
breakAddress = PCAfterInstructionExecutes(aThread, currentPC, statusRegister, instSize, /* aStepInto, */ newRangeEnd, changingModes);
|
|
sl@0
|
1822 |
|
|
sl@0
|
1823 |
/*
|
|
sl@0
|
1824 |
If there is already a user breakpoint at this address, we do not need to set a temp breakpoint. The program
|
|
sl@0
|
1825 |
should simply stop at that address.
|
|
sl@0
|
1826 |
*/
|
|
sl@0
|
1827 |
TBreakEntry* breakEntry = NULL;
|
|
sl@0
|
1828 |
do
|
|
sl@0
|
1829 |
{
|
|
sl@0
|
1830 |
breakEntry = iChannel->iBreakManager->GetNextBreak(breakEntry);
|
|
sl@0
|
1831 |
if(breakEntry && !iChannel->iBreakManager->IsTemporaryBreak(*breakEntry))
|
|
sl@0
|
1832 |
{
|
|
sl@0
|
1833 |
if ((breakEntry->iAddress == breakAddress) && ((breakEntry->iThreadSpecific && breakEntry->iId == aThread->iId) || (!breakEntry->iThreadSpecific && breakEntry->iId == aThread->iOwningProcess->iId)))
|
|
sl@0
|
1834 |
{
|
|
sl@0
|
1835 |
LOG_MSG("DRMDStepping::ModifyBreaksForStep - Breakpoint already exists at the step target address\n");
|
|
sl@0
|
1836 |
|
|
sl@0
|
1837 |
// note also that if this is the case, we will not keep stepping if we hit a real breakpoint, so may as well set
|
|
sl@0
|
1838 |
// the step count = 0.
|
|
sl@0
|
1839 |
breakEntry->iNumSteps = 0;
|
|
sl@0
|
1840 |
|
|
sl@0
|
1841 |
return KErrNone;
|
|
sl@0
|
1842 |
}
|
|
sl@0
|
1843 |
}
|
|
sl@0
|
1844 |
} while(breakEntry);
|
|
sl@0
|
1845 |
|
|
sl@0
|
1846 |
breakEntry = NULL;
|
|
sl@0
|
1847 |
do
|
|
sl@0
|
1848 |
{
|
|
sl@0
|
1849 |
breakEntry = iChannel->iBreakManager->GetNextBreak(breakEntry);
|
|
sl@0
|
1850 |
if(breakEntry && iChannel->iBreakManager->IsTemporaryBreak(*breakEntry))
|
|
sl@0
|
1851 |
{
|
|
sl@0
|
1852 |
if (breakEntry->iAddress == 0)
|
|
sl@0
|
1853 |
{
|
|
sl@0
|
1854 |
breakEntry->iId = aThread->iId;
|
|
sl@0
|
1855 |
breakEntry->iAddress = breakAddress;
|
|
sl@0
|
1856 |
breakEntry->iThreadSpecific = ETrue;
|
|
sl@0
|
1857 |
|
|
sl@0
|
1858 |
TBool realThumbMode = (thumbMode && !changingModes) || (!thumbMode && changingModes);
|
|
sl@0
|
1859 |
|
|
sl@0
|
1860 |
// Need to set the correct type of breakpoint for the mode we are in
|
|
sl@0
|
1861 |
// and the the one we are changing into
|
|
sl@0
|
1862 |
if(realThumbMode)
|
|
sl@0
|
1863 |
{
|
|
sl@0
|
1864 |
// We are remaining in Thumb mode
|
|
sl@0
|
1865 |
breakEntry->iMode = EThumbMode;
|
|
sl@0
|
1866 |
}
|
|
sl@0
|
1867 |
else
|
|
sl@0
|
1868 |
{
|
|
sl@0
|
1869 |
// We are switching to ARM mode
|
|
sl@0
|
1870 |
breakEntry->iMode = EArmMode;
|
|
sl@0
|
1871 |
}
|
|
sl@0
|
1872 |
|
|
sl@0
|
1873 |
breakEntry->iResumeOnceOutOfRange = aResumeOnceOutOfRange;
|
|
sl@0
|
1874 |
breakEntry->iSteppingInto = ETrue /* aStepInto */;
|
|
sl@0
|
1875 |
breakEntry->iRangeStart = 0; // no longer used
|
|
sl@0
|
1876 |
breakEntry->iRangeEnd = 0; // no longer used
|
|
sl@0
|
1877 |
|
|
sl@0
|
1878 |
LOG_MSG2("Adding temp breakpoint with id: %d", breakEntry->iBreakId);
|
|
sl@0
|
1879 |
LOG_MSG2("Adding temp breakpoint with thread id: %d", aThread->iId);
|
|
sl@0
|
1880 |
|
|
sl@0
|
1881 |
// Record how many more steps to go after we hit this one
|
|
sl@0
|
1882 |
breakEntry->iNumSteps = aNumSteps;
|
|
sl@0
|
1883 |
|
|
sl@0
|
1884 |
LOG_MSG3("Setting temp breakpoint id %d with %d steps to go\n", breakEntry->iBreakId, aNumSteps);
|
|
sl@0
|
1885 |
|
|
sl@0
|
1886 |
return iChannel->iBreakManager->DoEnableBreak(*breakEntry, ETrue);
|
|
sl@0
|
1887 |
}
|
|
sl@0
|
1888 |
}
|
|
sl@0
|
1889 |
} while(breakEntry);
|
|
sl@0
|
1890 |
LOG_MSG("ModifyBreaksForStep : Failed to set suitable breakpoint for stepping");
|
|
sl@0
|
1891 |
return KErrNoMemory; // should never get here
|
|
sl@0
|
1892 |
}
|
|
sl@0
|
1893 |
|
|
sl@0
|
1894 |
// End of file - d-rmd-stepping.cpp
|