sl@0: // Copyright (c) 2004-2009 Nokia Corporation and/or its subsidiary(-ies).
sl@0: // All rights reserved.
sl@0: // This component and the accompanying materials are made available
sl@0: // under the terms of the License "Eclipse Public License v1.0"
sl@0: // which accompanies this distribution, and is available
sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
sl@0: //
sl@0: // Initial Contributors:
sl@0: // Nokia Corporation - initial contribution.
sl@0: //
sl@0: // Contributors:
sl@0: //
sl@0: // Description:
sl@0: // This file contains stepping code refactored from rm_debug_kerneldriver.cpp/rm_debug_kerneldriver.h
sl@0: //
sl@0: 
sl@0: #include <e32def.h>
sl@0: #include <e32def_private.h>
sl@0: #include <e32cmn.h>
sl@0: #include <e32cmn_private.h>
sl@0: #include <kernel/kernel.h> 
sl@0: #include <kernel/kern_priv.h>
sl@0: #include <nk_trace.h>
sl@0: #include <arm.h>
sl@0: #include <rm_debug_api.h>
sl@0: 
sl@0: #include "d_rmd_stepping.h"
sl@0: #include "d_rmd_breakpoints.h"
sl@0: #include "rm_debug_kerneldriver.h"	// needed to access DRM_DebugChannel
sl@0: #include "rm_debug_driver.h"
sl@0: #include "debug_logging.h"
sl@0: 
sl@0: using namespace Debug;
sl@0: 
sl@0: //
sl@0: // DRMDStepping::DRMDStepping
sl@0: //
sl@0: DRMDStepping::DRMDStepping(DRM_DebugChannel* aChannel)
sl@0: :
sl@0: 	iChannel(aChannel)
sl@0: 	{
sl@0: 	// to do
sl@0: 	}
sl@0: 
sl@0: //
sl@0: // DRMDStepping::~DRM_DebugChannel
sl@0: //
sl@0: DRMDStepping::~DRMDStepping()
sl@0: {
sl@0: 	// to do
sl@0: }
sl@0: 
sl@0: //
sl@0: // DRMDStepping::IsExecuted
sl@0: //
sl@0: TBool DRMDStepping::IsExecuted(TUint8 aCondition ,TUint32 aStatusRegister)
sl@0: {
sl@0: 	LOG_MSG("DRMDStepping::IsExecuted()");
sl@0: 
sl@0: 	TBool N = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000008;
sl@0: 	TBool Z = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000004;
sl@0: 	TBool C = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000002;
sl@0: 	TBool V = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000001;
sl@0: 
sl@0: 	switch(aCondition)
sl@0: 	{
sl@0: 		case 0:
sl@0: 			return Z;
sl@0: 		case 1:
sl@0: 			return !Z;
sl@0: 		case 2:
sl@0: 			return C;
sl@0: 		case 3:
sl@0: 			return !C;
sl@0: 		case 4:
sl@0: 			return N;
sl@0: 		case 5:
sl@0: 			return !N;
sl@0: 		case 6:
sl@0: 			return V;
sl@0: 		case 7:
sl@0: 			return !V;
sl@0: 		case 8:
sl@0: 			return (C && !Z);
sl@0: 		case 9:
sl@0: 			return (!C || Z);
sl@0: 		case 10:
sl@0: 			return (N == V);
sl@0: 		case 11:
sl@0: 			return (N != V);
sl@0: 		case 12:
sl@0: 			return ((N == V) && !Z);
sl@0: 		case 13:
sl@0: 			return (Z || (N != V));
sl@0: 		case 14:
sl@0: 		case 15:
sl@0: 			return ETrue;
sl@0: 	}
sl@0: 	
sl@0: 	return EFalse;
sl@0: }
sl@0: 
sl@0: //
sl@0: // DRMDStepping::IsPreviousInstructionMovePCToLR
sl@0: //
sl@0: TBool DRMDStepping::IsPreviousInstructionMovePCToLR(DThread *aThread)
sl@0: {
sl@0: 	LOG_MSG("DRMDStepping::IsPreviousInstructionMovePCToLR()");
sl@0: 
sl@0: 	TInt err = KErrNone;
sl@0: 	
sl@0: 	// there are several types of instructions that modify the PC that aren't
sl@0: 	// designated as linked or non linked branches.  the way gcc generates the
sl@0: 	// code can tell us whether or not these instructions are to be treated as
sl@0: 	// linked branches.  the main cases are bx and any type of mov or load or
sl@0: 	// arithmatic operation that changes the PC.  if these are really just
sl@0: 	// function calls that will return, gcc will generate a mov	lr, pc
sl@0: 	// instruction as the previous instruction.  note that this is just for arm
sl@0: 	// and armi
sl@0: 	
sl@0: 	// get the address of the previous instruction
sl@0: 	TUint32 address = 0;
sl@0: 	err = iChannel->ReadKernelRegisterValue(aThread, PC_REGISTER, address);
sl@0: 	if(err != KErrNone)
sl@0: 	{
sl@0: 		LOG_MSG2("Non-zero error code discarded: %d", err);
sl@0: 	}
sl@0: 	address -= 4;
sl@0: 
sl@0: 	TBuf8<4> previousInstruction;
sl@0: 	err = iChannel->DoReadMemory(aThread, address, 4, previousInstruction);
sl@0: 	if (KErrNone != err)
sl@0: 	{
sl@0: 		LOG_MSG2("Error %d reading memory at address %x", address);
sl@0: 		return EFalse;
sl@0: 	}
sl@0: 
sl@0: 	const TUint32 movePCToLRIgnoringCondition = 0x01A0E00F;
sl@0: 
sl@0: 	TUint32 inst = *(TUint32 *)previousInstruction.Ptr();
sl@0: 	
sl@0: 	if ((inst & 0x0FFFFFFF) == movePCToLRIgnoringCondition)
sl@0: 	{
sl@0: 		return ETrue;
sl@0: 	}
sl@0: 		
sl@0: 	return EFalse;
sl@0: }
sl@0: 
sl@0: //
sl@0: // DRMDStepping::DecodeDataProcessingInstruction
sl@0: //
sl@0: void DRMDStepping::DecodeDataProcessingInstruction(TUint8 aOpcode, TUint32 aOp1, TUint32 aOp2, TUint32 aStatusRegister, TUint32 &aBreakAddress)
sl@0: {
sl@0: 	LOG_MSG("DRMDStepping::DecodeDataProcessingInstruction()");
sl@0: 
sl@0: 	switch(aOpcode)
sl@0: 	{
sl@0: 		case 0:
sl@0: 		{
sl@0: 			// AND
sl@0: 			aBreakAddress = aOp1 & aOp2;
sl@0: 			break;
sl@0: 		}
sl@0: 		case 1:
sl@0: 		{
sl@0: 			// EOR
sl@0: 			aBreakAddress = aOp1 ^ aOp2;
sl@0: 			break;
sl@0: 		}
sl@0: 		case 2:
sl@0: 		{
sl@0: 			// SUB
sl@0: 			aBreakAddress = aOp1 - aOp2;
sl@0: 			break;
sl@0: 		}
sl@0: 		case 3:
sl@0: 		{
sl@0: 			// RSB
sl@0: 			aBreakAddress = aOp2 - aOp1;
sl@0: 			break;
sl@0: 		}
sl@0: 		case 4:
sl@0: 		{
sl@0: 			// ADD
sl@0: 			aBreakAddress = aOp1 + aOp2;
sl@0: 			break;
sl@0: 		}
sl@0: 		case 5:
sl@0: 		{
sl@0: 			// ADC
sl@0: 			aBreakAddress = aOp1 + aOp2 + (aStatusRegister & arm_carry_bit()) ? 1 : 0;
sl@0: 			break;
sl@0: 		}
sl@0: 		case 6:
sl@0: 		{
sl@0: 			// SBC
sl@0: 			aBreakAddress = aOp1 - aOp2 - (aStatusRegister & arm_carry_bit()) ? 0 : 1;
sl@0: 			break;
sl@0: 		}
sl@0: 		case 7:
sl@0: 		{
sl@0: 			// RSC
sl@0: 			aBreakAddress = aOp2 - aOp1 - (aStatusRegister & arm_carry_bit()) ? 0 : 1;
sl@0: 			break;
sl@0: 		}
sl@0: 		case 12:
sl@0: 		{
sl@0: 			// ORR
sl@0: 			aBreakAddress = aOp1 | aOp2;
sl@0: 			break;
sl@0: 		}
sl@0: 		case 13:
sl@0: 		{
sl@0: 			// MOV
sl@0: 			aBreakAddress = aOp2;
sl@0: 			break;
sl@0: 		}
sl@0: 		case 14:
sl@0: 		{
sl@0: 			// BIC
sl@0: 			aBreakAddress = aOp1 & ~aOp2;
sl@0: 			break;
sl@0: 		}
sl@0: 		case 15:
sl@0: 		{
sl@0: 			// MVN
sl@0: 			aBreakAddress = ~aOp2;
sl@0: 			break;
sl@0: 		}
sl@0: 	}
sl@0: }
sl@0: 
sl@0: //
sl@0: // DRMDStepping::CurrentInstruction
sl@0: //
sl@0: // Returns the current instruction bitpattern (either 32-bits or 16-bits) if possible
sl@0: TInt DRMDStepping::CurrentInstruction(DThread* aThread, TUint32& aInstruction)
sl@0: 	{
sl@0: 	LOG_MSG("DRMDStepping::CurrentInstruction");
sl@0: 
sl@0: 	// What is the current PC?
sl@0: 	TUint32 pc;	
sl@0: 	ReturnIfError(CurrentPC(aThread,pc));
sl@0: 
sl@0: 	// Read it one byte at a time to ensure alignment doesn't matter
sl@0: 	TUint32 inst = 0;
sl@0: 	for(TInt i=3;i>=0;i--)
sl@0: 		{
sl@0: 
sl@0: 		TBuf8<1> instruction;
sl@0: 		TInt err = iChannel->DoReadMemory(aThread, (pc+i), 1, instruction); 
sl@0: 		if (KErrNone != err)
sl@0: 			{
sl@0: 			LOG_MSG2("DRMDStepping::CurrentInstruction : Failed to read memory at current PC: return 0x%08x",pc);
sl@0: 			return err;
sl@0: 			}
sl@0: 
sl@0: 		inst = (inst << 8) | (*(TUint8 *)instruction.Ptr());
sl@0: 		}
sl@0: 
sl@0: 	aInstruction = inst;
sl@0: 
sl@0: 	LOG_MSG2("DRMDStepping::CurrentInstruction 0x%08x", aInstruction);
sl@0: 
sl@0: 	return KErrNone;
sl@0: 	}
sl@0: 
sl@0: //
sl@0: // DRMDStepping::CurrentArchMode
sl@0: //
sl@0: // Determines architecture mode from the supplied cpsr
sl@0: TInt DRMDStepping::CurrentArchMode(const TUint32 aCpsr, Debug::TArchitectureMode& aMode)
sl@0: 	{
sl@0: // Thumb2 work will depend on having a suitable cpu architecture to compile for...
sl@0: #ifdef ECpuJf
sl@0: 	// State table as per ARM ARM DDI0406A, section A.2.5.1
sl@0: 	if(aCpsr & ECpuJf)
sl@0: 		{
sl@0: 		if (aCpsr & ECpuThumb)
sl@0: 			{
sl@0: 			// ThumbEE (Thumb2)
sl@0: 			aMode = Debug::EThumb2EEMode;
sl@0: 			}
sl@0: 		else
sl@0: 			{
sl@0: 			// Jazelle mode - not supported
sl@0: 			return KErrNotSupported;
sl@0: 			}
sl@0: 		}
sl@0: 	else
sl@0: #endif
sl@0: 		{
sl@0: 		if (aCpsr & ECpuThumb)
sl@0: 			{
sl@0: 			// Thumb mode
sl@0: 			aMode = Debug::EThumbMode;
sl@0: 			}
sl@0: 		else
sl@0: 			{
sl@0: 			// ARM mode
sl@0: 			aMode = Debug::EArmMode;
sl@0: 			}
sl@0: 		}
sl@0: 
sl@0: 	return KErrNone;
sl@0: 	}
sl@0: 
sl@0: //
sl@0: // DRMDStepping::PCAfterInstructionExecutes
sl@0: //
sl@0: // Note, this function pretty much ignores all the arguments except for aThread.
sl@0: // The arguments continue to exist so that the function has the same prototype as
sl@0: // the original from Nokia. In the long term this function will be re-factored
sl@0: // to remove obsolete parameters.
sl@0: //
sl@0: TUint32 DRMDStepping::PCAfterInstructionExecutes(DThread *aThread, TUint32 aCurrentPC, TUint32 aStatusRegister, TInt aInstSize, /*TBool aStepInto,*/ TUint32 &aNewRangeEnd, TBool &aChangingModes)
sl@0: {
sl@0: 	LOG_MSG("DRMDStepping::PCAfterInstructionExecutes()");
sl@0: 
sl@0: 	// by default we will set the breakpoint at the next instruction
sl@0: 	TUint32 breakAddress = aCurrentPC + aInstSize;
sl@0: 
sl@0: 	TInt err = KErrNone;
sl@0: 
sl@0: 	// determine the architecture
sl@0:     TUint32 cpuid;
sl@0:    	asm("mrc p15, 0, cpuid, c0, c0, 0 ");
sl@0: 	LOG_MSG2("DRMDStepping::PCAfterInstructionExecutes() - cpuid = 0x%08x\n",cpuid);
sl@0: 
sl@0:     cpuid >>= 8;
sl@0:     cpuid &= 0xFF;
sl@0: 
sl@0: 	// determine the architecture mode for the current instruction
sl@0: 	TArchitectureMode mode = EArmMode;	// Default assumption is ARM 
sl@0: 
sl@0: 	// Now we must examine the CPSR to read the T and J bits. See ARM ARM DDI0406A, section B1.3.3
sl@0: 	TUint32 cpsr;
sl@0: 
sl@0: 	ReturnIfError(CurrentCPSR(aThread,cpsr));
sl@0: 	LOG_MSG2("DRMDStepping::PCAfterInstructionExecutes() - cpsr = 0x%08x\n",cpsr);
sl@0: 
sl@0: 	// Determine the mode
sl@0: 	ReturnIfError(CurrentArchMode(cpsr,mode));
sl@0: 
sl@0: 	// Decode instruction based on current CPU mode
sl@0: 	switch(mode)
sl@0: 	{
sl@0: 		case Debug::EArmMode:
sl@0: 		{
sl@0: 			// Obtain the current instruction bit pattern
sl@0: 			TUint32 inst;
sl@0: 			ReturnIfError(CurrentInstruction(aThread,inst));
sl@0: 			
sl@0: 			LOG_MSG2("Current instruction: %x", inst);
sl@0: 
sl@0: 			// check the conditions to see if this will actually get executed
sl@0: 			if (IsExecuted(((inst>>28) & 0x0000000F), aStatusRegister)) 
sl@0: 			{
sl@0: 				switch(arm_opcode(inst)) // bits 27-25
sl@0: 				{
sl@0: 					case 0:
sl@0: 					{
sl@0: 						switch((inst & 0x00000010) >> 4) // bit 4
sl@0: 						{
sl@0: 							case 0:
sl@0: 							{
sl@0: 								switch((inst & 0x01800000) >> 23) // bits 24-23
sl@0: 								{
sl@0: 									case 2:
sl@0: 									{
sl@0: 										// move to/from status register.  pc updates not allowed
sl@0: 										// or TST, TEQ, CMP, CMN which don't modify the PC
sl@0: 										break;
sl@0: 									}
sl@0: 									default:
sl@0: 									{
sl@0: 										// Data processing immediate shift
sl@0: 										if (arm_rd(inst) == PC_REGISTER)
sl@0: 										{
sl@0: 											TUint32 rn = aCurrentPC + 8;
sl@0: 											if (arm_rn(inst) != PC_REGISTER) // bits 19-16
sl@0: 											{
sl@0: 												err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn);
sl@0: 												if(err != KErrNone)
sl@0: 												{
sl@0: 													LOG_MSG2("Non-zero error code discarded: %d", err);
sl@0: 												}
sl@0: 											}
sl@0: 
sl@0: 											TUint32 shifter = ShiftedRegValue(aThread, inst, aCurrentPC, aStatusRegister);
sl@0: 
sl@0: 											DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress);
sl@0: 										}
sl@0: 										break;
sl@0: 									}
sl@0: 								}
sl@0: 								break;
sl@0: 							}					
sl@0: 							case 1:
sl@0: 							{
sl@0: 								switch((inst & 0x00000080) >> 7) // bit 7
sl@0: 								{
sl@0: 									case 0:
sl@0: 									{
sl@0: 										switch((inst & 0x01900000) >> 20) // bits 24-23 and bit 20
sl@0: 										{
sl@0: 											case 0x10:
sl@0: 											{
sl@0: 												// from figure 3-3
sl@0: 												switch((inst & 0x000000F0) >> 4) // bits 7-4
sl@0: 												{
sl@0: 													case 1:
sl@0: 													{
sl@0: 														if (((inst & 0x00400000) >> 22) == 0) // bit 22
sl@0: 														{
sl@0: 															// BX
sl@0: 															// this is a strange case.  normally this is used in the epilogue to branch the the link
sl@0: 															// register.  sometimes it is used to call a function, and the LR is stored in the previous
sl@0: 															// instruction.  since what we want to do is different for the two cases when stepping over,
sl@0: 															// we need to read the previous instruction to see what we should do
sl@0: 															err = iChannel->ReadKernelRegisterValue(aThread, (inst & 0x0000000F), breakAddress);
sl@0: 															if(err != KErrNone)
sl@0: 															{
sl@0: 																LOG_MSG2("Non-zero error code discarded: %d", err);
sl@0: 															}
sl@0: 
sl@0: 															if ((breakAddress & 0x00000001) == 1)
sl@0: 															{
sl@0: 																aChangingModes = ETrue;
sl@0: 															}
sl@0: 
sl@0: 															breakAddress &= 0xFFFFFFFE;
sl@0: 														}
sl@0: 														break;
sl@0: 													}
sl@0: 													case 3:
sl@0: 													{
sl@0: 														// BLX
sl@0: 														{
sl@0: 															err = iChannel->ReadKernelRegisterValue(aThread, (inst & 0x0000000F), breakAddress);
sl@0: 															if(err != KErrNone)
sl@0: 															{
sl@0: 																LOG_MSG2("Non-zero error code discarded: %d", err);
sl@0: 															}
sl@0: 
sl@0: 															if ((breakAddress & 0x00000001) == 1)
sl@0: 															{
sl@0: 																aChangingModes = ETrue;
sl@0: 															}
sl@0: 															
sl@0: 															breakAddress &= 0xFFFFFFFE;
sl@0: 														}
sl@0: 														break;
sl@0: 													}
sl@0: 													default:
sl@0: 													{
sl@0: 														// either doesn't modify the PC or it is illegal to
sl@0: 														break;
sl@0: 													}
sl@0: 												}
sl@0: 												break;
sl@0: 											}
sl@0: 											default:
sl@0: 											{
sl@0: 												// Data processing register shift
sl@0: 												if (((inst & 0x01800000) >> 23) == 2) // bits 24-23
sl@0: 												{
sl@0: 													// TST, TEQ, CMP, CMN don't modify the PC
sl@0: 												}
sl@0: 												else if (arm_rd(inst) == PC_REGISTER)
sl@0: 												{
sl@0: 													// destination register is the PC
sl@0: 													TUint32 rn = aCurrentPC + 8;
sl@0: 													if (arm_rn(inst) != PC_REGISTER) // bits 19-16
sl@0: 													{
sl@0: 														err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn);
sl@0: 														if(err != KErrNone)
sl@0: 														{
sl@0: 															LOG_MSG2("Non-zero error code discarded: %d", err);
sl@0: 														}
sl@0: 													}
sl@0: 													
sl@0: 													TUint32 shifter = ShiftedRegValue(aThread, inst, aCurrentPC, aStatusRegister);
sl@0: 													
sl@0: 													DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress);
sl@0: 												}
sl@0: 												break;
sl@0: 											}
sl@0: 										}
sl@0: 										break;
sl@0: 									}
sl@0: 									default:
sl@0: 									{
sl@0: 										// from figure 3-2, updates to the PC illegal
sl@0: 										break;
sl@0: 									}
sl@0: 								}
sl@0: 								break;
sl@0: 							}
sl@0: 						}
sl@0: 						break;
sl@0: 					}
sl@0: 					case 1:
sl@0: 					{
sl@0: 						if (((inst & 0x01800000) >> 23) == 2) // bits 24-23
sl@0: 						{
sl@0: 							// cannot modify the PC
sl@0: 							break;
sl@0: 						}
sl@0: 						else if (arm_rd(inst) == PC_REGISTER)
sl@0: 						{
sl@0: 							// destination register is the PC
sl@0: 							TUint32 rn;
sl@0: 							err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn); // bits 19-16
sl@0: 							if(err != KErrNone)
sl@0: 							{
sl@0: 								LOG_MSG2("Non-zero error code discarded: %d", err);
sl@0: 							}
sl@0: 							TUint32 shifter = ((arm_data_imm(inst) >> arm_data_rot(inst)) | (arm_data_imm(inst) << (32 - arm_data_rot(inst)))) & 0xffffffff;
sl@0: 
sl@0: 							DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress);
sl@0: 						}
sl@0: 						break;
sl@0: 					}
sl@0: 					case 2:
sl@0: 					{
sl@0: 						// load/store immediate offset
sl@0: 						if (arm_load(inst)) // bit 20
sl@0: 						{
sl@0: 							// loading a register from memory
sl@0: 							if (arm_rd(inst) == PC_REGISTER)
sl@0: 							{
sl@0: 								// loading the PC register
sl@0: 								TUint32 base;
sl@0: 								err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), base);
sl@0: 								if(err != KErrNone)
sl@0: 								{
sl@0: 									LOG_MSG2("Non-zero error code discarded: %d", err);
sl@0: 								}
sl@0: 
sl@0: 								/* Note: At runtime the PC would be 8 further on
sl@0: 								 */
sl@0: 								if (arm_rn(inst) == PC_REGISTER)
sl@0: 								{
sl@0: 									base = aCurrentPC + 8;
sl@0: 								}
sl@0: 
sl@0: 								TUint32 offset = 0;
sl@0: 					    		
sl@0: 					    		if (arm_single_pre(inst))
sl@0: 					    		{
sl@0: 					    			// Pre-indexing
sl@0: 					    			offset = arm_single_imm(inst);
sl@0: 									
sl@0: 									if (arm_single_u(inst))
sl@0: 									{
sl@0: 							    		base += offset;
sl@0: 									}
sl@0: 									else
sl@0: 									{
sl@0: 							    		base -= offset;
sl@0: 									}
sl@0: 								}
sl@0: 
sl@0: 								TBuf8<4> destination;
sl@0: 								err = iChannel->DoReadMemory(aThread, base, 4, destination);
sl@0: 								
sl@0: 								if (KErrNone == err)
sl@0: 								{
sl@0: 									breakAddress = *(TUint32 *)destination.Ptr();
sl@0: 								
sl@0: 									if ((breakAddress & 0x00000001) == 1)
sl@0: 									{
sl@0: 										aChangingModes = ETrue;
sl@0: 									}								
sl@0: 									breakAddress &= 0xFFFFFFFE;
sl@0: 								}
sl@0: 								else
sl@0: 								{
sl@0: 									LOG_MSG("Error reading memory in decoding step instruction");
sl@0: 								}
sl@0: 							}
sl@0: 						}	
sl@0: 						break;
sl@0: 					}
sl@0: 					case 3:
sl@0: 					{
sl@0: 						if (((inst & 0xF0000000) != 0xF0000000) && ((inst & 0x00000010) == 0))
sl@0: 						{
sl@0: 							// load/store register offset
sl@0: 							if (arm_load(inst)) // bit 20
sl@0: 							{
sl@0: 								// loading a register from memory
sl@0: 								if (arm_rd(inst) == PC_REGISTER)
sl@0: 								{
sl@0: 									// loading the PC register
sl@0: 									TUint32 base = 0;
sl@0: 									if(arm_rn(inst) == PC_REGISTER)
sl@0: 									{
sl@0: 										base = aCurrentPC + 8;
sl@0: 									}
sl@0: 									else
sl@0: 									{
sl@0: 										err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), base);
sl@0: 										if(err != KErrNone)
sl@0: 										{
sl@0: 											LOG_MSG2("Non-zero error code discarded: %d", err);
sl@0: 										}
sl@0: 									}
sl@0: 
sl@0: 									TUint32 offset = 0;
sl@0: 
sl@0: 									if (arm_single_pre(inst))
sl@0: 									{
sl@0: 										offset = ShiftedRegValue(aThread, inst, aCurrentPC, aStatusRegister);
sl@0: 
sl@0: 										if (arm_single_u(inst))
sl@0: 										{
sl@0: 											base += offset;
sl@0: 										}
sl@0: 										else
sl@0: 										{
sl@0: 											base -= offset;
sl@0: 										}
sl@0: 									}
sl@0: 
sl@0: 									TBuf8<4> destination;
sl@0: 									err = iChannel->DoReadMemory(aThread, base, 4, destination);
sl@0: 
sl@0: 									if (KErrNone == err)
sl@0: 									{
sl@0: 										breakAddress = *(TUint32 *)destination.Ptr();
sl@0: 
sl@0: 										if ((breakAddress & 0x00000001) == 1)
sl@0: 										{
sl@0: 											aChangingModes = ETrue;
sl@0: 										}								
sl@0: 										breakAddress &= 0xFFFFFFFE;
sl@0: 									}
sl@0: 									else
sl@0: 									{
sl@0: 										LOG_MSG("Error reading memory in decoding step instruction");
sl@0: 									}
sl@0: 								}
sl@0: 							}	
sl@0: 						}
sl@0: 						break;
sl@0: 					}
sl@0: 					case 4:
sl@0: 					{
sl@0: 						if ((inst & 0xF0000000) != 0xF0000000)
sl@0: 						{
sl@0: 							// load/store multiple
sl@0: 							if (arm_load(inst)) // bit 20
sl@0: 							{
sl@0: 								// loading a register from memory
sl@0: 								if (((inst & 0x00008000) >> 15))
sl@0: 								{
sl@0: 									// loading the PC register
sl@0: 									TInt offset = 0;	
sl@0: 									if (arm_block_u(inst))
sl@0: 									{
sl@0: 										TUint32 reglist = arm_block_reglist(inst);
sl@0: 										offset = iChannel->Bitcount(reglist) * 4 - 4;
sl@0: 										if (arm_block_pre(inst))
sl@0: 											offset += 4;
sl@0: 									}
sl@0: 									else if (arm_block_pre(inst))
sl@0: 									{
sl@0: 										offset = -4;
sl@0: 									}
sl@0: 										
sl@0: 									TUint32 temp = 0;
sl@0: 									err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), temp);
sl@0: 									if(err != KErrNone)
sl@0: 									{
sl@0: 										LOG_MSG2("Non-zero error code discarded: %d", err);
sl@0: 									}
sl@0: 									
sl@0: 									temp += offset;
sl@0: 
sl@0: 									TBuf8<4> destination;
sl@0: 									err = iChannel->DoReadMemory(aThread, temp, 4, destination);
sl@0: 									
sl@0: 									if (KErrNone == err)
sl@0: 									{
sl@0: 										breakAddress = *(TUint32 *)destination.Ptr();
sl@0: 										if ((breakAddress & 0x00000001) == 1)
sl@0: 										{
sl@0: 											aChangingModes = ETrue;
sl@0: 										}
sl@0: 										breakAddress &= 0xFFFFFFFE;
sl@0: 									}
sl@0: 									else
sl@0: 									{
sl@0: 										LOG_MSG("Error reading memory in decoding step instruction");
sl@0: 									}
sl@0: 								}
sl@0: 							}					
sl@0: 						}
sl@0: 						break;
sl@0: 					}
sl@0: 					case 5:
sl@0: 					{
sl@0: 						if ((inst & 0xF0000000) == 0xF0000000)
sl@0: 						{
sl@0: 							// BLX
sl@0: 							{
sl@0: 								breakAddress = (TUint32)arm_instr_b_dest(inst, aCurrentPC);
sl@0: 
sl@0: 								// Unconditionally change into Thumb mode
sl@0: 								aChangingModes = ETrue;
sl@0: 								
sl@0: 								breakAddress &= 0xFFFFFFFE;
sl@0: 							}
sl@0: 						}
sl@0: 						else
sl@0: 						{
sl@0: 							if ((inst & 0x01000000)) // bit 24
sl@0: 							{
sl@0: 								// BL
sl@0: 								{
sl@0: 									breakAddress = (TUint32)arm_instr_b_dest(inst, aCurrentPC);
sl@0: 								}
sl@0: 							}
sl@0: 							else
sl@0: 							{
sl@0: 								// B
sl@0: 								breakAddress = (TUint32)arm_instr_b_dest(inst, aCurrentPC);
sl@0: 							}
sl@0: 						}
sl@0: 						break;
sl@0: 					}
sl@0: 				}	
sl@0: 			}
sl@0: 		}
sl@0: 		break;
sl@0: 
sl@0: 		case Debug::EThumbMode:
sl@0: 		{
sl@0: 			// Thumb Mode
sl@0: 			//
sl@0: 			// Notes: This now includes the extra code
sl@0: 			// required to decode V6T2 instructions
sl@0: 			
sl@0: 			LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Thumb Instruction");
sl@0: 
sl@0: 			TUint16 inst;
sl@0: 
sl@0: 			// Obtain the current instruction bit pattern
sl@0: 			TUint32 inst32;
sl@0: 			ReturnIfError(CurrentInstruction(aThread,inst32));
sl@0: 
sl@0: 			inst = static_cast<TUint16>(inst32 & 0xFFFF);
sl@0: 
sl@0: 			LOG_MSG2("Current Thumb instruction: 0x%x", inst);
sl@0: 
sl@0: 			// v6T2 instructions
sl@0: 
sl@0: // Note: v6T2 decoding is only enabled for DEBUG builds or if using an
sl@0: // an ARM_V6T2 supporting build system. At the time of writing, no
sl@0: // ARM_V6T2 supporting build system exists, so the stepping code cannot
sl@0: // be said to be known to work. Hence it is not run for release builds
sl@0: 
sl@0: 			TBool use_v6t2_decodings = EFalse;
sl@0: 
sl@0: #if defined(DEBUG) || defined(__ARMV6T2__)
sl@0: 			use_v6t2_decodings = ETrue;
sl@0: 
sl@0: #endif
sl@0: 			// coverity[dead_error_line]
sl@0: 			if (use_v6t2_decodings)
sl@0: 			{
sl@0: 				// 16-bit encodings
sl@0: 	 
sl@0: 				// A6.2.5 Misc 16-bit instructions
sl@0: 				// DONE Compare and branch on zero (page A8-66)
sl@0: 				// If then hints
sl@0: 
sl@0: 				// ARM ARM DDI0406A - section A8.6.27 CBNZ, CBZ
sl@0: 				//
sl@0: 				// Compare and branch on Nonzero and Compare and Branch on Zero.
sl@0: 				if ((inst & 0xF500) == 0xB100)
sl@0: 				{
sl@0: 					LOG_MSG("ARM ARM DDI0406A - section A8.6.27 CBNZ, CBZ");
sl@0: 
sl@0: 					// Decoding as per ARM ARM description
sl@0: 					TUint32 op = (inst & 0x0800) >> 11;
sl@0: 					TUint32 i = (inst & 0x0200) >> 9;
sl@0: 					TUint32 imm5 = (inst & 0x00F8) >> 3;
sl@0: 					TUint32 Rn = inst & 0x0007;
sl@0: 
sl@0: 					TUint32 imm32 = (i << 6) | (imm5 << 1);
sl@0: 
sl@0: 					// Obtain value for register Rn
sl@0: 					TUint32 RnVal = 0;
sl@0: 					ReturnIfError(RegisterValue(aThread,Rn,RnVal));
sl@0: 
sl@0: 					if (op)
sl@0: 						{
sl@0: 						// nonzero
sl@0: 						if (RnVal != 0x0)
sl@0: 							{
sl@0: 							// Branch
sl@0: 							breakAddress = aCurrentPC + imm32;
sl@0: 							}
sl@0: 						}
sl@0: 					else
sl@0: 						{
sl@0: 						// zero
sl@0: 						if (RnVal == 0x0)
sl@0: 							{
sl@0: 							// Branch
sl@0: 							breakAddress = aCurrentPC + imm32;
sl@0: 							}
sl@0: 						}
sl@0: 				}
sl@0: 
sl@0: 				// ARM ARM DDI0406A - section A8.6.50 IT
sl@0: 				//
sl@0: 				// If Then instruction
sl@0: 				if ((inst & 0xFF00) == 0xBF00)
sl@0: 				{
sl@0: 					LOG_MSG("ARM ARM DDI0406A - section A8.6.50 IT");
sl@0: 
sl@0: 					// Decoding as per ARM ARM description
sl@0: 					TUint32 firstcond = inst & 0x00F0 >> 4;
sl@0: 					TUint32 mask = inst & 0x000F;
sl@0: 
sl@0: 					if (firstcond == 0xF)
sl@0: 					{
sl@0: 						// unpredictable
sl@0: 						LOG_MSG("ARM ARM DDI0406A - section A8.6.50 IT - Unpredictable");
sl@0: 						break;
sl@0: 					}
sl@0: 
sl@0: 					if ((firstcond == 0xE) && (BitCount(mask) != 1))
sl@0: 					{
sl@0: 						// unpredictable
sl@0: 						LOG_MSG("ARM ARM DDI0406A - section A8.6.50 IT - Unpredictable");
sl@0: 						break;
sl@0: 					}
sl@0: 
sl@0: 					// should check if 'in-it-block'
sl@0: 					LOG_MSG("Cannot step IT instructions.");
sl@0: 
sl@0: 					// all the conds are as per Table A8-1 (i.e. the usual 16 cases)
sl@0: 					// no idea how to decode the it block 'after-the-fact'
sl@0: 					// so probably need to treat instructions in the it block
sl@0: 					// as 'may' be executed. So breakpoints at both possible locations
sl@0: 					// depending on whether the instruction is executed or not.
sl@0: 
sl@0: 					// also, how do we know if we have hit a breakpoint whilst 'in' an it block?
sl@0: 					// can we check the status registers to find out?
sl@0: 					//
sl@0: 					// see arm arm page 390.
sl@0: 					//
sl@0: 					// seems to depend on the itstate field. this also says what the condition code
sl@0: 					// actually is, and how many instructions are left in the itblock.
sl@0: 					// perhaps we can just totally ignore this state, and always do the two-instruction
sl@0: 					// breakpoint thing? Not if there is any possibility that the address target
sl@0: 					// would be invalid for the non-taken branch address...
sl@0: 				}
sl@0: 
sl@0: 
sl@0: 				// 32-bit encodings.
sl@0: 				//
sl@0: 
sl@0: 				// Load word A6-23
sl@0: 				// Data processing instructions a6-28
sl@0: 				// 
sl@0: 
sl@0: 				// ARM ARM DDI0406A - section A8.6.26
sl@0: 				if (inst32 & 0xFFF0FFFF == 0xE3C08F00)
sl@0: 				{
sl@0: 					LOG_MSG("ARM ARM DDI0406A - section A8.6.26 - BXJ is not supported");
sl@0: 
sl@0: 					// Decoding as per ARM ARM description
sl@0: 					// TUint32 Rm = inst32 & 0x000F0000;	// not needed yet
sl@0: 				}
sl@0: 
sl@0: 				// return from exception... SUBS PC,LR. page b6-25
sl@0: 				//
sl@0: 				// ARM ARM DDi046A - section B6.1.13 - SUBS PC,LR
sl@0: 				//
sl@0: 				// Encoding T1
sl@0: 				if (inst32 & 0xFFFFFF00 == 0xF3DE8F00)
sl@0: 				{
sl@0: 					LOG_MSG("ARM ARM DDI0406A - section B6.1.13 - SUBS PC,LR Encoding T1");
sl@0: 
sl@0: 					// Decoding as per ARM ARM description
sl@0: 					TUint32 imm8 = inst32 & 0x000000FF;
sl@0: 					TUint32 imm32 = imm8;
sl@0: 
sl@0: 					// TUint32 register_form = EFalse;	// not needed for this decoding
sl@0: 					// TUint32 opcode = 0x2;	// SUB	// not needed for this decoding
sl@0: 					TUint32 n = 14;
sl@0: 
sl@0: 					// Obtain LR
sl@0: 					TUint32 lrVal;
sl@0: 					ReturnIfError(RegisterValue(aThread,n,lrVal));
sl@0: 
sl@0: 					TUint32 operand2 = imm32;	// always for Encoding T1
sl@0: 					
sl@0: 					TUint32 result = lrVal - operand2;
sl@0: 					
sl@0: 					breakAddress = result;
sl@0: 				}
sl@0: 				
sl@0: 				// ARM ARM DDI0406A - section A8.6.16 - B
sl@0: 				//
sl@0: 				// Branch Encoding T3
sl@0: 				if (inst32 & 0xF800D000 == 0xF0008000)
sl@0: 				{
sl@0: 					LOG_MSG("ARM ARM DDI0406A - section A8.6.16 - B Encoding T3");
sl@0: 
sl@0: 					// Decoding as per ARM ARM description
sl@0: 					TUint32 S = inst32 & 0x04000000 >> 26;
sl@0: 					// TUint32 cond = inst32 & 0x03C00000 >> 22;	// not needed for this decoding
sl@0: 					TUint32 imm6 = inst32 & 0x003F0000 >> 16;
sl@0: 					TUint32 J1 = inst32 & 0x00002000 >> 13;
sl@0: 					TUint32 J2 = inst32 & 0x00000800 >> 11;
sl@0: 					TUint32 imm11 = inst32 & 0x000007FF;
sl@0: 
sl@0: 					TUint32 imm32 = S ? 0xFFFFFFFF : 0 ;
sl@0: 					imm32 = (imm32 << 1) | J2;
sl@0: 					imm32 = (imm32 << 1) | J1;
sl@0: 					imm32 = (imm32 << 6) | imm6;
sl@0: 					imm32 = (imm32 << 11) | imm11;
sl@0: 					imm32 = (imm32 << 1) | 0;
sl@0: 
sl@0: 					breakAddress = aCurrentPC + imm32;
sl@0: 				}
sl@0: 
sl@0: 				// ARM ARM DDI0406A - section A8.6.16 - B
sl@0: 				//
sl@0: 				// Branch Encoding T4
sl@0: 				if (inst32 & 0xF800D000 == 0xF0009000)
sl@0: 				{
sl@0: 					LOG_MSG("ARM ARM DDI0406A - section A8.6.16 - B");
sl@0: 
sl@0: 					// Decoding as per ARM ARM description
sl@0: 					TUint32 S = inst32 & 0x04000000 >> 26;
sl@0: 					TUint32 imm10 = inst32 & 0x03FF0000 >> 16;
sl@0: 					TUint32 J1 = inst32 & 0x00002000 >> 12;
sl@0: 					TUint32 J2 = inst32 & 0x00000800 >> 11;
sl@0: 					TUint32 imm11 = inst32 & 0x000003FF;
sl@0: 
sl@0: 					TUint32 I1 = !(J1 ^ S);
sl@0: 					TUint32 I2 = !(J2 ^ S);
sl@0: 
sl@0: 					TUint32 imm32 = S ? 0xFFFFFFFF : 0;
sl@0: 					imm32 = (imm32 << 1) | S;
sl@0: 					imm32 = (imm32 << 1) | I1;
sl@0: 					imm32 = (imm32 << 1) | I2;
sl@0: 					imm32 = (imm32 << 10) | imm10;
sl@0: 					imm32 = (imm32 << 11) | imm11;
sl@0: 					imm32 = (imm32 << 1) | 0;
sl@0: 
sl@0: 					breakAddress = aCurrentPC + imm32;
sl@0: 				}
sl@0: 
sl@0: 
sl@0: 				// ARM ARM DDI0406A - section A8.6.225 - TBB, TBH
sl@0: 				//
sl@0: 				// Table Branch Byte, Table Branch Halfword
sl@0: 				if (inst32 & 0xFFF0FFE0 == 0xE8D0F000)
sl@0: 				{
sl@0: 					LOG_MSG("ARM ARM DDI0406A - section A8.6.225 TBB,TBH Encoding T1");
sl@0: 
sl@0: 					// Decoding as per ARM ARM description
sl@0: 					TUint32 Rn = inst32 & 0x000F0000 >> 16;
sl@0: 					TUint32 H = inst32 & 0x00000010 >> 4;
sl@0: 					TUint32 Rm = inst32 & 0x0000000F;
sl@0: 
sl@0: 					// Unpredictable?
sl@0: 					if (Rm == 13 || Rm == 15)
sl@0: 					{
sl@0: 						LOG_MSG("ARM ARM DDI0406A - section A8.6.225 TBB,TBH Encoding T1 - Unpredictable");
sl@0: 						break;
sl@0: 					}
sl@0: 
sl@0: 					TUint32 halfwords;
sl@0: 					TUint32 address;
sl@0: 					ReturnIfError(RegisterValue(aThread,Rn,address));
sl@0: 
sl@0: 					TUint32 offset;
sl@0: 					ReturnIfError(RegisterValue(aThread,Rm,offset));
sl@0: 
sl@0: 					if (H)
sl@0: 					{
sl@0: 
sl@0: 						address += offset << 1;
sl@0: 					}
sl@0: 					else
sl@0: 					{
sl@0: 						address += offset;
sl@0: 					}
sl@0: 
sl@0: 					ReturnIfError(ReadMem32(aThread,address,halfwords));
sl@0: 
sl@0: 					breakAddress = aCurrentPC + 2*halfwords;
sl@0: 					break;
sl@0: 				}
sl@0: 
sl@0: 				// ARM ARM DDI0406A - section A8.6.55 - LDMDB, LDMEA
sl@0: 				//
sl@0: 				// LDMDB Encoding T1
sl@0: 				if (inst32 & 0xFFD02000 == 0xE9100000)
sl@0: 				{
sl@0: 					LOG_MSG("ARM ARM DDI0406 - section A8.6.55 LDMDB Encoding T1");
sl@0: 
sl@0: 					// Decoding as per ARM ARM description
sl@0: 					// TUint32 W = inst32 & 0x00200000 >> 21;	// Not needed for this encoding
sl@0: 					TUint32 Rn = inst32 & 0x000F0000 >> 16;
sl@0: 					TUint32 P = inst32 & 0x00008000 >> 15;
sl@0: 					TUint32 M = inst32 & 0x00004000 >> 14;
sl@0: 					TUint32 registers = inst32 & 0x00001FFF;
sl@0: 
sl@0: 					//TBool wback = (W == 1);	// not needed for this encoding
sl@0: 
sl@0: 					// Unpredictable?
sl@0: 					if (Rn == 15 || BitCount(registers) < 2 || ((P == 1) && (M==1)))
sl@0: 					{
sl@0: 						LOG_MSG("ARM ARM DDI0406 - section A8.6.55 LDMDB Encoding T1 - Unpredictable");
sl@0: 						break;
sl@0: 					}
sl@0: 
sl@0: 					TUint32 address;
sl@0: 					ReturnIfError(RegisterValue(aThread,Rn,address));
sl@0: 
sl@0: 					address -= 4*BitCount(registers);
sl@0: 
sl@0: 					for(TInt i=0; i<15; i++)
sl@0: 					{
sl@0: 						if (IsBitSet(registers,i))
sl@0: 						{
sl@0: 							address +=4;
sl@0: 						}
sl@0: 					}
sl@0: 
sl@0: 					if (IsBitSet(registers,15))
sl@0: 					{
sl@0: 						TUint32 RnVal = 0;
sl@0: 						ReturnIfError(ReadMem32(aThread,address,RnVal));
sl@0: 
sl@0: 						breakAddress = RnVal;
sl@0: 					}
sl@0: 					break;
sl@0: 				}
sl@0: 
sl@0: 				// ARM ARM DDI0406A - section A8.6.121 POP
sl@0: 				//
sl@0: 				// POP.W Encoding T2
sl@0: 				if (inst32 & 0xFFFF2000 == 0xE8BD0000)
sl@0: 				{
sl@0: 					LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T2");
sl@0: 
sl@0: 					// Decoding as per ARM ARM description
sl@0: 					TUint32 registers = inst32 & 0x00001FFF;
sl@0: 					TUint32 P = inst32 & 0x00008000;
sl@0: 					TUint32 M = inst32 & 0x00004000;
sl@0: 
sl@0: 					// Unpredictable?
sl@0: 					if ( (BitCount(registers)<2) || ((P == 1)&&(M == 1)) )
sl@0: 					{
sl@0: 						LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T2 - Unpredictable");
sl@0: 						break;
sl@0: 					}
sl@0: 
sl@0: 					TUint32 address;
sl@0: 					ReturnIfError(RegisterValue(aThread,13,address));
sl@0: 					
sl@0: 					for(TInt i=0; i< 15; i++)
sl@0: 					{
sl@0: 						if (IsBitSet(registers,i))
sl@0: 						{
sl@0: 							address += 4;
sl@0: 						}
sl@0: 					}
sl@0: 
sl@0: 					// Is the PC written?
sl@0: 					if (IsBitSet(registers,15))
sl@0: 					{
sl@0: 						// Yes
sl@0: 						ReturnIfError(ReadMem32(aThread,address,breakAddress));
sl@0: 					}
sl@0: 				}
sl@0: 
sl@0: 				// POP Encoding T3
sl@0: 				if (inst32 & 0xFFFF0FFFF == 0xF85D0B04)
sl@0: 				{
sl@0: 					LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T3");
sl@0: 
sl@0: 					// Decoding as per ARM ARM description
sl@0: 					TUint32 Rt = inst32 & 0x0000F000 >> 12;
sl@0: 					TUint32 registers = 1 << Rt;
sl@0: 
sl@0: 					// Unpredictable?
sl@0: 					if (Rt == 13 || Rt == 15)
sl@0: 					{
sl@0: 						LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T3 - Unpredictable");
sl@0: 						break;
sl@0: 					}
sl@0: 					
sl@0: 					TUint32 address;
sl@0: 					ReturnIfError(RegisterValue(aThread,13,address));
sl@0: 					
sl@0: 					for(TInt i=0; i< 15; i++)
sl@0: 					{
sl@0: 						if (IsBitSet(registers,i))
sl@0: 						{
sl@0: 							address += 4;
sl@0: 						}
sl@0: 					}
sl@0: 
sl@0: 					// Is the PC written?
sl@0: 					if (IsBitSet(registers,15))
sl@0: 					{
sl@0: 						// Yes
sl@0: 						ReturnIfError(ReadMem32(aThread,address,breakAddress));
sl@0: 					}
sl@0: 
sl@0: 					break;
sl@0: 				}
sl@0: 
sl@0: 				// ARM ARM DDI0406A - section A8.6.53 LDM
sl@0: 				//
sl@0: 				// Load Multiple Encoding T2 
sl@0: 				if ((inst32 & 0xFFD02000) == 0xE8900000)
sl@0: 				{
sl@0: 					LOG_MSG("ARM ARM DDI0406A - section A8.6.53 LDM Encoding T2");
sl@0: 
sl@0: 					// Decoding as per ARM ARM description
sl@0: 					TUint32 W = inst32 & 0x0020000 >> 21;
sl@0: 					TUint32 Rn = inst32 & 0x000F0000 >> 16;
sl@0: 					TUint32 P = inst32 & 0x00008000 >> 15;
sl@0: 					TUint32 M = inst32 & 0x00004000 >> 14;
sl@0: 					TUint32 registers = inst32 & 0x0000FFFF;
sl@0: 					TUint32 register_list = inst32 & 0x00001FFF;
sl@0: 				
sl@0: 					// POP?
sl@0: 					if ( (W == 1) && (Rn == 13) )
sl@0: 					{
sl@0: 						// POP instruction
sl@0: 						LOG_MSG("ARM ARM DDI0406A - section A8.6.53 LDM Encoding T2 - POP");
sl@0: 					}
sl@0: 
sl@0: 					// Unpredictable?
sl@0: 					if (Rn == 15 || BitCount(register_list) < 2 || ((P == 1) && (M == 1)) )
sl@0: 					{
sl@0: 						LOG_MSG("ARM ARM DDI0406A - section A8.6.53 LDM Encoding T2 - Unpredictable");
sl@0: 						break;
sl@0: 					}
sl@0: 					
sl@0: 					TUint32 RnVal;
sl@0: 					ReturnIfError(RegisterValue(aThread,Rn,RnVal));
sl@0: 
sl@0: 					TUint32 address = RnVal;
sl@0: 
sl@0: 					// Calculate offset of address
sl@0: 					for(TInt i = 0; i < 15; i++)
sl@0: 					{
sl@0: 						if (IsBitSet(registers,i))
sl@0: 						{
sl@0: 							address += 4;
sl@0: 						}
sl@0: 					}
sl@0: 
sl@0: 					// Does it load the PC?
sl@0: 					if (IsBitSet(registers,15))
sl@0: 					{
sl@0: 						// Obtain the value loaded into the PC
sl@0: 						ReturnIfError(ReadMem32(aThread,address,breakAddress));
sl@0: 					}
sl@0: 					break;
sl@0: 
sl@0: 				}
sl@0: 
sl@0: 				// ARM ARM DDI0406A - section B6.1.8 RFE
sl@0: 				//
sl@0: 				// Return From Exception Encoding T1 RFEDB
sl@0: 				if ((inst32 & 0xFFD0FFFF) == 0xE810C000)
sl@0: 				{
sl@0: 					LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding T1");
sl@0: 
sl@0: 					// Decoding as per ARM ARM description
sl@0: 					// TUint32 W = (inst32 & 0x00200000) >> 21;	// not needed for this encoding
sl@0: 					TUint32 Rn = (inst32 & 0x000F0000) >> 16;
sl@0: 					
sl@0: 					// TBool wback = (W == 1);	// not needed for this encoding
sl@0: 					TBool increment = EFalse;
sl@0: 					TBool wordhigher = EFalse;
sl@0: 
sl@0: 					// Do calculation
sl@0: 					if (Rn == 15)
sl@0: 					{
sl@0: 						// Unpredictable 
sl@0: 						LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding T1 - Unpredictable");
sl@0: 						break;
sl@0: 					}
sl@0: 
sl@0: 					TUint32 RnVal = 0;
sl@0: 					ReturnIfError(RegisterValue(aThread,Rn,RnVal));
sl@0: 
sl@0: 					TUint32 address = 0;
sl@0: 					ReturnIfError(ReadMem32(aThread,RnVal,address));
sl@0: 
sl@0: 					if (increment)
sl@0: 					{
sl@0: 						address -= 8;
sl@0: 					}
sl@0: 
sl@0: 					if (wordhigher)
sl@0: 					{
sl@0: 						address += 4;
sl@0: 					}				
sl@0: 
sl@0: 					breakAddress = address;
sl@0: 					break;
sl@0: 				}
sl@0: 
sl@0: 				// Return From Exception Encoding T2 RFEIA
sl@0: 				if ((inst32 & 0xFFD0FFFF) == 0xE990C000)
sl@0: 				{
sl@0: 					LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding T2");
sl@0: 
sl@0: 					// Decoding as per ARM ARM description
sl@0: 					// TUint32 W = (inst32 & 0x00200000) >> 21;	// not needed for this encoding
sl@0: 					TUint32 Rn = (inst32 & 0x000F0000) >> 16;
sl@0: 					
sl@0: 					// TBool wback = (W == 1);	// not needed for this encoding
sl@0: 					TBool increment = ETrue;
sl@0: 					TBool wordhigher = EFalse;
sl@0: 
sl@0: 					// Do calculation
sl@0: 					if (Rn == 15)
sl@0: 					{
sl@0: 						// Unpredictable 
sl@0: 						LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding T2 - Unpredictable");
sl@0: 						break;
sl@0: 					}
sl@0: 
sl@0: 					TUint32 RnVal = 0;
sl@0: 					ReturnIfError(RegisterValue(aThread,Rn,RnVal));
sl@0: 
sl@0: 					TUint32 address = 0;
sl@0: 					ReturnIfError(ReadMem32(aThread,RnVal,address));
sl@0: 
sl@0: 					if (increment)
sl@0: 					{
sl@0: 						address -= 8;
sl@0: 					}
sl@0: 
sl@0: 					if (wordhigher)
sl@0: 					{
sl@0: 						address += 4;
sl@0: 					}				
sl@0: 
sl@0: 					breakAddress = RnVal;
sl@0: 					break;
sl@0: 				}
sl@0: 
sl@0: 				// Return From Exception Encoding A1 RFE<amode>
sl@0: 				if ((inst32 & 0xFE50FFFF) == 0xF8100A00)
sl@0: 				{
sl@0: 					LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding A1");
sl@0: 
sl@0: 					// Decoding as per ARM ARM description
sl@0: 					TUint32 P = (inst32 & 0x01000000) >> 24;
sl@0: 					TUint32 U = (inst32 & 0x00800000) >> 23;
sl@0: 					// TUint32 W = (inst32 & 0x00200000) >> 21; // not needed for this encoding
sl@0: 					TUint32 Rn = (inst32 & 0x000F0000) >> 16;	
sl@0: 					
sl@0: 					// TBool wback = (W == 1);	// not needed for this encoding
sl@0: 					TBool increment = (U == 1);
sl@0: 					TBool wordhigher = (P == U);
sl@0: 
sl@0: 					// Do calculation
sl@0: 					if (Rn == 15)
sl@0: 					{
sl@0: 						// Unpredictable 
sl@0: 						LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding A1 - Unpredictable");
sl@0: 						break;
sl@0: 					}
sl@0: 
sl@0: 					TUint32 RnVal = 0;
sl@0: 					ReturnIfError(RegisterValue(aThread,Rn,RnVal));
sl@0: 
sl@0: 					TUint32 address = 0;
sl@0: 					ReturnIfError(ReadMem32(aThread,RnVal,address));
sl@0: 
sl@0: 					if (increment)
sl@0: 					{
sl@0: 						address -= 8;
sl@0: 					}
sl@0: 
sl@0: 					if (wordhigher)
sl@0: 					{
sl@0: 						address += 4;
sl@0: 					}				
sl@0: 
sl@0: 					breakAddress = address;
sl@0: 					break;
sl@0: 				}
sl@0: 			}
sl@0: 
sl@0: 			// v4T/v5T/v6T instructions
sl@0: 			switch(thumb_opcode(inst))
sl@0: 			{		
sl@0: 				case 0x08:
sl@0: 				{
sl@0: 					// Data-processing. See ARM ARM DDI0406A, section A6-8, A6.2.2.
sl@0: 
sl@0: 					if ((thumb_inst_7_15(inst) == 0x08F))
sl@0: 					{
sl@0: 						// BLX(2)
sl@0: 						err = iChannel->ReadKernelRegisterValue(aThread, ((inst & 0x0078) >> 3), breakAddress);
sl@0: 						if(err != KErrNone)
sl@0: 						{
sl@0: 							LOG_MSG2("Non-zero error code discarded: %d", err);
sl@0: 						}
sl@0: 
sl@0: 						if ((breakAddress & 0x00000001) == 0)
sl@0: 						{
sl@0: 							aChangingModes = ETrue;
sl@0: 						}
sl@0: 						
sl@0: 						breakAddress &= 0xFFFFFFFE;
sl@0: 
sl@0: 						// Report how we decoded this instruction
sl@0: 						LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as BLX (2)");
sl@0: 					}
sl@0: 					else if (thumb_inst_7_15(inst) == 0x08E)
sl@0: 					{
sl@0: 						// BX
sl@0: 						err = iChannel->ReadKernelRegisterValue(aThread, ((inst & 0x0078) >> 3), breakAddress);
sl@0: 						if(err != KErrNone)
sl@0: 						{
sl@0: 							LOG_MSG2("Non-zero error code discarded: %d", err);
sl@0: 						}
sl@0: 
sl@0: 						if ((breakAddress & 0x00000001) == 0)
sl@0: 						{
sl@0: 							aChangingModes = ETrue;
sl@0: 						}
sl@0: 						
sl@0: 						breakAddress &= 0xFFFFFFFE;
sl@0: 
sl@0: 						// Report how we decoded this instruction
sl@0: 						LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as BX");
sl@0: 					}
sl@0: 					else if ((thumb_inst_8_15(inst) == 0x46) && ((inst & 0x87) == 0x87))
sl@0: 					{
sl@0: 						// MOV with PC as the destination
sl@0: 						err = iChannel->ReadKernelRegisterValue(aThread, ((inst & 0x0078) >> 3), breakAddress);
sl@0: 						if(err != KErrNone)
sl@0: 						{
sl@0: 							LOG_MSG2("Non-zero error code discarded: %d", err);
sl@0: 						}
sl@0: 
sl@0: 						// Report how we decoded this instruction
sl@0: 						LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as MOV with PC as the destination");
sl@0: 					}
sl@0: 					else if ((thumb_inst_8_15(inst) == 0x44) && ((inst & 0x87) == 0x87))
sl@0: 					{
sl@0: 						// ADD with PC as the destination
sl@0: 						err = iChannel->ReadKernelRegisterValue(aThread, ((inst & 0x0078) >> 3), breakAddress);
sl@0: 						if(err != KErrNone)
sl@0: 						{
sl@0: 							LOG_MSG2("Non-zero error code discarded: %d", err);
sl@0: 						}
sl@0: 						breakAddress += aCurrentPC + 4; // +4 because we need to use the PC+4 according to ARM ARM DDI0406A, section A6.1.2.
sl@0: 
sl@0: 						// Report how we decoded this instruction
sl@0: 						LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as ADD with PC as the destination");
sl@0: 					}
sl@0: 					break;
sl@0: 				}
sl@0: 				case 0x13:
sl@0: 				{
sl@0: 					// Load/Store single data item. See ARM ARM DDI0406A, section A6-10
sl@0: 
sl@0: 					//This instruction doesn't modify the PC.
sl@0: 
sl@0: 					//if (thumb_inst_8_15(inst) == 0x9F)
sl@0: 					//{
sl@0: 						// LDR(4) with the PC as the destination
sl@0: 					//	breakAddress = ReadRegister(aThread, SP_REGISTER) + (4 * (inst & 0x00FF));
sl@0: 					//}
sl@0: 
sl@0: 					// Report how we decoded this instruction
sl@0: 					LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as This instruction doesn't modify the PC.");
sl@0: 					break;
sl@0: 				}
sl@0: 				case 0x17:
sl@0: 				{	
sl@0: 					// Misc 16-bit instruction. See ARM ARM DDI0406A, section A6-11
sl@0: 
sl@0: 					if (thumb_inst_8_15(inst) == 0xBD)
sl@0: 					{
sl@0: 						// POP with the PC in the list
sl@0: 						TUint32 regList = (inst & 0x00FF);
sl@0: 						TInt offset = 0;
sl@0: 						err = iChannel->ReadKernelRegisterValue(aThread,  SP_REGISTER, (T4ByteRegisterValue&)offset);
sl@0: 						if(err != KErrNone)
sl@0: 						{
sl@0: 							LOG_MSG2("Non-zero error code discarded: %d", err);
sl@0: 						}
sl@0: 						offset += (iChannel->Bitcount(regList) * 4);
sl@0: 
sl@0: 						TBuf8<4> destination;
sl@0: 						err = iChannel->DoReadMemory(aThread, offset, 4, destination);
sl@0: 						
sl@0: 						if (KErrNone == err)
sl@0: 						{
sl@0: 							breakAddress = *(TUint32 *)destination.Ptr();
sl@0: 
sl@0: 							if ((breakAddress & 0x00000001) == 0)
sl@0: 							{
sl@0: 								aChangingModes = ETrue;
sl@0: 							}
sl@0: 
sl@0: 							breakAddress &= 0xFFFFFFFE;
sl@0: 						}
sl@0: 						else
sl@0: 						{
sl@0: 							LOG_MSG("Error reading memory in decoding step instruction");
sl@0: 						}
sl@0: 
sl@0: 						// Report how we decoded this instruction
sl@0: 						LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as POP with the PC in the list");
sl@0: 					}
sl@0: 					break;
sl@0: 				}
sl@0: 				case 0x1A:
sl@0: 				case 0x1B:
sl@0: 				{	
sl@0: 					// Conditional branch, and supervisor call. See ARM ARM DDI0406A, section A6-13
sl@0: 
sl@0: 					if (thumb_inst_8_15(inst) < 0xDE)
sl@0: 					{
sl@0: 						// B(1) conditional branch
sl@0: 						if (IsExecuted(((inst & 0x0F00) >> 8), aStatusRegister))
sl@0: 						{
sl@0: 							TUint32 offset = ((inst & 0x000000FF) << 1);
sl@0: 							if (offset & 0x00000100)
sl@0: 							{
sl@0: 								offset |= 0xFFFFFF00;
sl@0: 							}
sl@0: 							
sl@0: 							breakAddress = aCurrentPC + 4 + offset;
sl@0: 
sl@0: 							// Report how we decoded this instruction
sl@0: 							LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as B(1) conditional branch");
sl@0: 						}
sl@0: 					}
sl@0: 					break;
sl@0: 				}
sl@0: 				case 0x1C:
sl@0: 				{
sl@0: 					// Unconditional branch, See ARM ARM DDI0406A, section A8-44.
sl@0: 
sl@0: 					// B(2) unconditional branch
sl@0: 					TUint32 offset = (inst & 0x000007FF) << 1;
sl@0: 					if (offset & 0x00000800)
sl@0: 					{
sl@0: 						offset |= 0xFFFFF800;
sl@0: 					}
sl@0: 					
sl@0: 					breakAddress = aCurrentPC + 4 + offset;
sl@0: 
sl@0: 					// Report how we decoded this instruction
sl@0: 					LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as B(2) unconditional branch");
sl@0: 
sl@0: 					break;
sl@0: 				}
sl@0: 				case 0x1D:
sl@0: 				{
sl@0: 					if (!(inst & 0x0001))
sl@0: 					{
sl@0: 						// BLX(1)
sl@0: 						err = iChannel->ReadKernelRegisterValue(aThread, LINK_REGISTER, breakAddress);
sl@0: 						if(err != KErrNone)
sl@0: 						{
sl@0: 							LOG_MSG2("Non-zero error code discarded: %d", err);
sl@0: 						}
sl@0: 						breakAddress +=  ((inst & 0x07FF) << 1);
sl@0: 						if ((breakAddress & 0x00000001) == 0)
sl@0: 						{
sl@0: 							aChangingModes = ETrue;
sl@0: 						}
sl@0: 
sl@0: 						breakAddress &= 0xFFFFFFFC;
sl@0: 
sl@0: 						// Report how we decoded this instruction
sl@0: 						LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as BLX(1)");
sl@0: 
sl@0: 					}
sl@0: 					break;
sl@0: 				}
sl@0: 				case 0x1E:
sl@0: 				{
sl@0:                     // Check for ARMv7 CPU
sl@0:                     if(cpuid == 0xC0)
sl@0:                     {
sl@0:     					// BL/BLX 32-bit instruction
sl@0: 	    				aNewRangeEnd += 4;
sl@0: 
sl@0: 						breakAddress = (TUint32)thumb_instr_b_dest(inst32, aCurrentPC);
sl@0: 
sl@0:             			if((inst32 >> 27) == 0x1D)
sl@0:             			{
sl@0:             			    // BLX(1)
sl@0:     						if ((breakAddress & 0x00000001) == 0)
sl@0: 	    					{
sl@0: 		    					aChangingModes = ETrue;
sl@0: 			    			}
sl@0:     
sl@0: 	    					breakAddress &= 0xFFFFFFFC;
sl@0: 
sl@0:     						// Report how we decoded this instruction
sl@0: 	    					LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as 32-bit BLX(1)");
sl@0:                         }
sl@0:                         else
sl@0:                         {                            
sl@0:     					    // Report how we decoded this instruction
sl@0: 	        				LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: 32-bit BL instruction");
sl@0:                         }
sl@0:         				LOG_MSG2(" 32-bit BL/BLX instruction: breakAddress = 0x%X", breakAddress);
sl@0:                     }            
sl@0:                     else
sl@0:                     {
sl@0: 					    // BL/BLX prefix - destination is encoded in this and the next instruction
sl@0: 					    aNewRangeEnd += 2;
sl@0: 
sl@0: 					    // Report how we decoded this instruction
sl@0: 					    LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: BL/BLX prefix - destination is encoded in this and the next instruction");
sl@0:                     }
sl@0: 
sl@0: 
sl@0: 					break;
sl@0: 				}
sl@0: 				case 0x1F:
sl@0: 				{
sl@0: 					{
sl@0: 						// BL
sl@0: 						err = iChannel->ReadKernelRegisterValue(aThread, LINK_REGISTER, breakAddress);
sl@0: 						if(err != KErrNone)
sl@0: 						{
sl@0: 							LOG_MSG2("Non-zero error code discarded: %d", err);
sl@0: 						}
sl@0: 						breakAddress += ((inst & 0x07FF) << 1);
sl@0: 
sl@0: 						// Report how we decoded this instruction
sl@0: 						LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as BL");
sl@0: 					}
sl@0: 					break;
sl@0: 				}
sl@0: 				default:
sl@0: 					{
sl@0: 						// Don't know any better at this point!
sl@0: 						LOG_MSG("DRMDStepping::PCAfterInstructionExecutes:- default to next instruction");
sl@0: 					}
sl@0: 					break;
sl@0: 			}
sl@0: 		}
sl@0: 		break;
sl@0: 		
sl@0: 		case Debug::EThumb2EEMode:
sl@0: 		{
sl@0: 			// Not yet supported
sl@0: 			LOG_MSG("DRMDStepping::PCAfterInstructionExecutes - Debug::EThumb2Mode is not supported");
sl@0: 
sl@0: 		}
sl@0: 		break;
sl@0: 
sl@0: 		default:
sl@0: 			LOG_MSG("DRMDStepping::PCAfterInstructionExecutes - Cannot determine CPU mode architecture");
sl@0: 	}	
sl@0: 
sl@0: 	LOG_MSG2("DRMDStepping::PCAfterInstructionExecutes : return 0x%08x",breakAddress);
sl@0: 	return breakAddress;
sl@0: }
sl@0: 
sl@0: // Obtain a 32-bit memory value with minimum fuss
sl@0: TInt DRMDStepping::ReadMem32(DThread* aThread, const TUint32 aAddress, TUint32& aValue)
sl@0: 	{
sl@0: 	TBuf8<4> valBuf;
sl@0: 	TInt err = iChannel->DoReadMemory(aThread, aAddress, 4, valBuf);
sl@0: 	if (err != KErrNone)
sl@0: 		{
sl@0: 		LOG_MSG2("DRMDStepping::ReadMem32 failed to read memory at 0x%08x", aAddress);
sl@0: 		return err;
sl@0: 		}
sl@0: 
sl@0: 	aValue = *(TUint32 *)valBuf.Ptr();
sl@0: 
sl@0: 	return KErrNone;
sl@0: 	}
sl@0: 
sl@0: // Obtain a 16-bit memory value with minimum fuss
sl@0: TInt DRMDStepping::ReadMem16(DThread* aThread, const TUint32 aAddress, TUint16& aValue)
sl@0: 	{
sl@0: 	TBuf8<2> valBuf;
sl@0: 	TInt err = iChannel->DoReadMemory(aThread, aAddress, 2, valBuf);
sl@0: 	if (err != KErrNone)
sl@0: 		{
sl@0: 		LOG_MSG2("DRMDStepping::ReadMem16 failed to read memory at 0x%08x", aAddress);
sl@0: 		return err;
sl@0: 		}
sl@0: 
sl@0: 	aValue = *(TUint16 *)valBuf.Ptr();
sl@0: 
sl@0: 	return KErrNone;
sl@0: 	}
sl@0: 
sl@0: // Obtain a 16-bit memory value with minimum fuss
sl@0: TInt DRMDStepping::ReadMem8(DThread* aThread, const TUint32 aAddress, TUint8& aValue)
sl@0: 	{
sl@0: 	TBuf8<1> valBuf;
sl@0: 	TInt err = iChannel->DoReadMemory(aThread, aAddress, 1, valBuf);
sl@0: 	if (err != KErrNone)
sl@0: 		{
sl@0: 		LOG_MSG2("DRMDStepping::ReadMem8 failed to read memory at 0x%08x", aAddress);
sl@0: 		return err;
sl@0: 		}
sl@0: 
sl@0: 	aValue = *(TUint8 *)valBuf.Ptr();
sl@0: 
sl@0: 	return KErrNone;
sl@0: 	}
sl@0: 
sl@0: // Obtain a core register value with minimum fuss
sl@0: TInt DRMDStepping::RegisterValue(DThread *aThread, const TUint32 aKernelRegisterId, TUint32 &aValue)
sl@0: 	{
sl@0: 	TInt err = iChannel->ReadKernelRegisterValue(aThread, aKernelRegisterId, aValue);
sl@0: 	if(err != KErrNone)
sl@0: 		{
sl@0: 		LOG_MSG3("DRMDStepping::RegisterValue failed to read register %d err = %d", aKernelRegisterId, err);
sl@0: 		}
sl@0: 		return err;
sl@0: 	}
sl@0: 
sl@0: 
sl@0: // Encodings from ARM ARM DDI0406A, section 9.2.1
sl@0: enum TThumb2EEOpcode
sl@0: {
sl@0: 	EThumb2HDP,		// Handler Branch with Parameter
sl@0: 	EThumb2UNDEF,	// UNDEFINED
sl@0: 	EThumb2HB,		// Handler Branch, Handler Branch with Link
sl@0: 	EThumb2HBLP,	// Handle Branch with Link and Parameter
sl@0: 	EThumb2LDRF,	// Load Register from a frame
sl@0: 	EThumb2CHKA,	// Check Array
sl@0: 	EThumb2LDRL,	// Load Register from a literal pool
sl@0: 	EThumb2LDRA,	// Load Register (array operations)
sl@0: 	EThumb2STR		// Store Register to a frame
sl@0: };
sl@0: 
sl@0: //
sl@0: // DRMDStepping::ShiftedRegValue
sl@0: //
sl@0: TUint32 DRMDStepping::ShiftedRegValue(DThread *aThread, TUint32 aInstruction, TUint32 aCurrentPC, TUint32 aStatusRegister)
sl@0: {
sl@0: 	LOG_MSG("DRM_DebugChannel::ShiftedRegValue()");
sl@0: 
sl@0: 	TUint32 shift = 0;
sl@0: 	if (aInstruction & 0x10)	// bit 4
sl@0: 	{
sl@0: 		shift = (arm_rs(aInstruction) == PC_REGISTER ? aCurrentPC + 8 : aStatusRegister) & 0xFF;
sl@0: 	}
sl@0: 	else
sl@0: 	{
sl@0: 		shift = arm_data_c(aInstruction);
sl@0: 	}
sl@0: 	
sl@0: 	TInt rm = arm_rm(aInstruction);
sl@0: 	
sl@0: 	TUint32 res = 0;
sl@0: 	if(rm == PC_REGISTER)
sl@0: 	{
sl@0: 		res = aCurrentPC + ((aInstruction & 0x10) ? 12 : 8);
sl@0: 	}
sl@0: 	else
sl@0: 	{
sl@0: 		TInt err = iChannel->ReadKernelRegisterValue(aThread, rm, res);
sl@0: 		if(err != KErrNone)
sl@0: 		{
sl@0: 			LOG_MSG2("DRMDStepping::ShiftedRegValue - Non-zero error code discarded: %d", err);
sl@0: 		}
sl@0: 	}
sl@0: 
sl@0: 	switch(arm_data_shift(aInstruction))
sl@0: 	{
sl@0: 		case 0:			// LSL
sl@0: 		{
sl@0: 			res = shift >= 32 ? 0 : res << shift;
sl@0: 			break;
sl@0: 		}
sl@0: 		case 1:			// LSR
sl@0: 		{
sl@0: 			res = shift >= 32 ? 0 : res >> shift;
sl@0: 			break;
sl@0: 		}
sl@0: 		case 2:			// ASR
sl@0: 		{
sl@0: 			if (shift >= 32)
sl@0: 			shift = 31;
sl@0: 			res = ((res & 0x80000000L) ? ~((~res) >> shift) : res >> shift);
sl@0: 			break;
sl@0: 		}
sl@0: 		case 3:			// ROR/RRX
sl@0: 		{
sl@0: 			shift &= 31;
sl@0: 			if (shift == 0)
sl@0: 			{
sl@0: 				res = (res >> 1) | ((aStatusRegister & arm_carry_bit()) ? 0x80000000L : 0);
sl@0: 			}
sl@0: 			else
sl@0: 			{
sl@0: 				res = (res >> shift) | (res << (32 - shift));
sl@0: 			}
sl@0: 			break;
sl@0:     	}
sl@0:     }
sl@0: 
sl@0:   	return res & 0xFFFFFFFF;
sl@0: }
sl@0: 
sl@0: //
sl@0: // DRMDStepping::CurrentPC
sl@0: //
sl@0: // 
sl@0: //
sl@0: TInt DRMDStepping::CurrentPC(DThread* aThread, TUint32& aPC)
sl@0: 	{
sl@0: 	LOG_MSG("DRMDStepping::CurrentPC");
sl@0: 
sl@0: 	TInt err = iChannel->ReadKernelRegisterValue(aThread, PC_REGISTER, aPC);
sl@0: 	if(err != KErrNone)
sl@0: 		{
sl@0: 		// We don't know the current PC for this thread!
sl@0: 		LOG_MSG("DRMDStepping::CurrentPC - Failed to read the current PC");
sl@0: 		
sl@0: 		return KErrGeneral;
sl@0: 		}
sl@0: 
sl@0: 	LOG_MSG2("DRMDStepping::CurrentPC 0x%08x", aPC);
sl@0: 
sl@0: 	return KErrNone;
sl@0: 	}
sl@0: 
sl@0: //
sl@0: // DRMDStepping::CurrentCPSR
sl@0: //
sl@0: // 
sl@0: //
sl@0: TInt DRMDStepping::CurrentCPSR(DThread* aThread, TUint32& aCPSR)
sl@0: 	{
sl@0: 	LOG_MSG("DRMDStepping::CurrentCPSR");
sl@0: 
sl@0: 	TInt err = iChannel->ReadKernelRegisterValue(aThread, STATUS_REGISTER, aCPSR);
sl@0: 	if(err != KErrNone)
sl@0: 		{
sl@0: 		// We don't know the current PC for this thread!
sl@0: 		LOG_MSG("DRMDStepping::CurrentPC - Failed to read the current CPSR");
sl@0: 		
sl@0: 		return KErrGeneral;
sl@0: 		}
sl@0: 
sl@0: 	LOG_MSG2("DRMDStepping::CurrentCPSR 0x%08x", aCPSR);
sl@0: 	
sl@0: 	return KErrNone;
sl@0: 	}
sl@0: 
sl@0: //
sl@0: // DRMDStepping::ModifyBreaksForStep
sl@0: //
sl@0: // Set a temporary breakpoint at the next instruction to be executed after the one at the current PC
sl@0: // Disable the breakpoint at the current PC if one exists
sl@0: //
sl@0: TInt DRMDStepping::ModifyBreaksForStep(DThread *aThread, TUint32 aRangeStart, TUint32 aRangeEnd, /*TBool aStepInto,*/ TBool aResumeOnceOutOfRange, TBool aCheckForStubs, const TUint32 aNumSteps)
sl@0: 	{
sl@0: 	LOG_MSG2("DRMDStepping::ModifyBreaksForStep() Numsteps 0x%d",aNumSteps);
sl@0: 
sl@0: 	// Validate arguments
sl@0: 	if (!aThread)
sl@0: 		{
sl@0: 		LOG_MSG("DRMDStepping::ModifyBreaksForStep() - No aThread specified to step");
sl@0: 		return KErrArgument;
sl@0: 		}
sl@0: 
sl@0: 	// Current PC
sl@0: 	TUint32 currentPC;
sl@0: 
sl@0: 	ReturnIfError(CurrentPC(aThread,currentPC));
sl@0: 	LOG_MSG2("Current PC: 0x%x", currentPC);
sl@0: 
sl@0: 	// disable breakpoint at the current PC if necessary
sl@0: 	ReturnIfError(iChannel->iBreakManager->DisableBreakAtAddress(currentPC));
sl@0: 
sl@0: 	// Current CPSR
sl@0: 	TUint32 statusRegister;
sl@0: 
sl@0: 	ReturnIfError(CurrentCPSR(aThread,statusRegister));
sl@0: 	LOG_MSG2("Current CPSR: %x", statusRegister);
sl@0: 
sl@0: 	TBool thumbMode = (statusRegister & ECpuThumb);
sl@0: 	if (thumbMode)
sl@0: 		LOG_MSG("Thumb Mode");
sl@0: 
sl@0: 	TInt instSize = thumbMode ? 2 : 4;
sl@0: 
sl@0: 	TBool changingModes = EFalse;
sl@0: 
sl@0: 	TUint32 breakAddress = 0;
sl@0: 
sl@0: 	TUint32 newRangeEnd = aRangeEnd;
sl@0: 
sl@0: 	breakAddress = PCAfterInstructionExecutes(aThread, currentPC, statusRegister, instSize, /* aStepInto, */ newRangeEnd, changingModes);
sl@0: 
sl@0: 	/*
sl@0: 	If there is already a user breakpoint at this address, we do not need to set a temp breakpoint. The program
sl@0: 	should simply stop at that address.	
sl@0: 	*/
sl@0: 	TBreakEntry* breakEntry = NULL;
sl@0: 	do
sl@0: 		{
sl@0: 		breakEntry = iChannel->iBreakManager->GetNextBreak(breakEntry);
sl@0: 		if(breakEntry && !iChannel->iBreakManager->IsTemporaryBreak(*breakEntry))
sl@0: 			{
sl@0: 			if ((breakEntry->iAddress == breakAddress) && ((breakEntry->iThreadSpecific && breakEntry->iId == aThread->iId) || (!breakEntry->iThreadSpecific && breakEntry->iId == aThread->iOwningProcess->iId)))
sl@0: 				{
sl@0: 				LOG_MSG("DRMDStepping::ModifyBreaksForStep - Breakpoint already exists at the step target address\n");
sl@0: 
sl@0: 				// note also that if this is the case, we will not keep stepping if we hit a real breakpoint, so may as well set
sl@0: 				// the step count = 0.
sl@0: 				breakEntry->iNumSteps = 0;
sl@0: 
sl@0: 				return KErrNone;
sl@0: 				}
sl@0: 			}
sl@0: 		} while(breakEntry);
sl@0: 
sl@0: 	breakEntry = NULL;
sl@0: 	do
sl@0: 		{
sl@0: 		breakEntry = iChannel->iBreakManager->GetNextBreak(breakEntry);
sl@0: 		if(breakEntry && iChannel->iBreakManager->IsTemporaryBreak(*breakEntry))
sl@0: 			{
sl@0: 			if (breakEntry->iAddress == 0)
sl@0: 				{
sl@0: 				breakEntry->iId = aThread->iId;
sl@0: 				breakEntry->iAddress = breakAddress;
sl@0: 				breakEntry->iThreadSpecific = ETrue;
sl@0: 
sl@0: 				TBool realThumbMode = (thumbMode && !changingModes) || (!thumbMode && changingModes);
sl@0: 
sl@0: 				// Need to set the correct type of breakpoint for the mode we are in
sl@0: 				// and the the one we are changing into
sl@0: 				if(realThumbMode)
sl@0: 					{
sl@0: 					// We are remaining in Thumb mode
sl@0: 					breakEntry->iMode = EThumbMode;
sl@0: 					}
sl@0: 				else
sl@0: 					{
sl@0: 					// We are switching to ARM mode
sl@0: 					breakEntry->iMode = EArmMode;
sl@0: 					}
sl@0: 
sl@0: 				breakEntry->iResumeOnceOutOfRange = aResumeOnceOutOfRange;
sl@0: 				breakEntry->iSteppingInto = ETrue /* aStepInto */;
sl@0: 				breakEntry->iRangeStart = 0;	// no longer used
sl@0: 				breakEntry->iRangeEnd = 0;		// no longer used
sl@0: 
sl@0: 				LOG_MSG2("Adding temp breakpoint with id: %d", breakEntry->iBreakId);
sl@0: 				LOG_MSG2("Adding temp breakpoint with thread id: %d", aThread->iId);
sl@0: 
sl@0: 				// Record how many more steps to go after we hit this one
sl@0: 				breakEntry->iNumSteps = aNumSteps;
sl@0: 
sl@0: 				LOG_MSG3("Setting temp breakpoint id %d with %d steps to go\n", breakEntry->iBreakId, aNumSteps);
sl@0: 
sl@0: 				return iChannel->iBreakManager->DoEnableBreak(*breakEntry, ETrue);			
sl@0: 				}
sl@0: 			}
sl@0: 		} while(breakEntry);
sl@0: 	LOG_MSG("ModifyBreaksForStep : Failed to set suitable breakpoint for stepping");
sl@0: 	return KErrNoMemory;	// should never get here
sl@0: }
sl@0: 
sl@0: // End of file - d-rmd-stepping.cpp