williamr@4: // Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies).
williamr@4: // All rights reserved.
williamr@4: // This component and the accompanying materials are made available
williamr@4: // under the terms of the License "Eclipse Public License v1.0"
williamr@4: // which accompanies this distribution, and is available
williamr@4: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
williamr@4: //
williamr@4: // Initial Contributors:
williamr@4: // Nokia Corporation - initial contribution.
williamr@4: //
williamr@4: // Contributors:
williamr@4: //
williamr@4: // Description:
williamr@4: //
williamr@4: 
williamr@4: #ifndef TPS65950_REGISTERS_H
williamr@4: #define TPS65950_REGISTERS_H
williamr@4: 
williamr@4: #include <e32cmn.h>
williamr@4: 
williamr@4: namespace TPS65950
williamr@4: {
williamr@4: 
williamr@4: namespace Register
williamr@4: 	{
williamr@4: 	const TUint KGroupShift = 8;
williamr@4: 	const TUint KRegisterMask = 0xFF;
williamr@4: 	const TUint KGroupMask = 0xFF00;
williamr@4: 
williamr@4: 	enum TGroup
williamr@4: 		{
williamr@4: 		EGroup12 = (0 << KGroupShift),
williamr@4: 		EGroup48 = (1 << KGroupShift),
williamr@4: 		EGroup49 = (2 << KGroupShift),
williamr@4: 		EGroup4a = (3 << KGroupShift),
williamr@4: 		EGroup4b = (4 << KGroupShift)
williamr@4: 		};
williamr@4: 
williamr@4: 	enum TGroup12Registers
williamr@4: 		{
williamr@4: 		VDD1_SR_CONTROL = EGroup12,
williamr@4: 		VDD2_SR_CONTROL
williamr@4: 		};
williamr@4: 
williamr@4: 
williamr@4: 	enum TGroup48Registers
williamr@4: 		{
williamr@4: 		VENDOR_ID_LO =  EGroup48,
williamr@4: 		VENDOR_ID_HI, 
williamr@4: 		PRODUCT_ID_LO,
williamr@4: 		PRODUCT_ID_HI,
williamr@4: 		FUNC_CTRL,
williamr@4: 		FUNC_CTRL_SET,
williamr@4: 		FUNC_CTRL_CLR,
williamr@4: 		IFC_CTRL,
williamr@4: 		IFC_CTRL_SET, 
williamr@4: 		IFC_CTRL_CLR, 
williamr@4: 		OTG_CTRL,
williamr@4: 		OTG_CTRL_SET,
williamr@4: 		OTG_CTRL_CLR,
williamr@4: 		USB_INT_EN_RISE, 
williamr@4: 		USB_INT_EN_RISE_SET,
williamr@4: 		USB_INT_EN_RISE_CLR,
williamr@4: 		USB_INT_EN_FALL, 
williamr@4: 		USB_INT_EN_FALL_SET, 
williamr@4: 		USB_INT_EN_FALL_CLR,
williamr@4: 		USB_INT_STS, 
williamr@4: 		USB_INT_LATCH,
williamr@4: 		DEBUG, 
williamr@4: 		SCRATCH_REG, 
williamr@4: 		SCRATCH_REG_SET,
williamr@4: 		SCRATCH_REG_CLR,
williamr@4: 		CARKIT_CTRL, 
williamr@4: 		CARKIT_CTRL_SET, 
williamr@4: 		CARKIT_CTRL_CLR, 
williamr@4: 		CARKIT_INT_DELAY,
williamr@4: 		CARKIT_INT_EN, 
williamr@4: 		CARKIT_INT_EN_SET,
williamr@4: 		CARKIT_INT_EN_CLR,
williamr@4: 		CARKIT_INT_STS, 
williamr@4: 		CARKIT_INT_LATCH, 
williamr@4: 		CARKIT_PLS_CTRL, 
williamr@4: 		CARKIT_PLS_CTRL_SET, 
williamr@4: 		CARKIT_PLS_CTRL_CLR,
williamr@4: 		TRANS_POS_WIDTH, 
williamr@4: 		TRANS_NEG_WIDTH,
williamr@4: 		RCV_PLTY_RECOVERY,
williamr@4: 		MCPC_CTRL = 0x30, 
williamr@4: 		MCPC_CTRL_SET,
williamr@4: 		MCPC_CTRL_CLR,
williamr@4: 		MCPC_IO_CTRL,
williamr@4: 		MCPC_IO_CTRL_SET, 
williamr@4: 		MCPC_IO_CTRL_CLR,
williamr@4: 		MCPC_CTRL2, 
williamr@4: 		MCPC_CTRL2_SET, 
williamr@4: 		MCPC_CTRL2_CLR, 
williamr@4: 		OTHER_FUNC_CTRL = EGroup48 + 0x80, 
williamr@4: 		OTHER_FUNC_CTRL_SET, 
williamr@4: 		OTHER_FUNC_CTRL_CLR, 
williamr@4: 		OTHER_IFC_CTRL,
williamr@4: 		OTHER_IFC_CTRL_SET,
williamr@4: 		OTHER_IFC_CTRL_CLR,
williamr@4: 		OTHER_INT_EN_RISE,
williamr@4: 		OTHER_INT_EN_RISE_SET,
williamr@4: 		OTHER_INT_EN_RISE_CLR,
williamr@4: 		OTHER_INT_EN_FALL,
williamr@4: 		OTHER_INT_EN_FALL_SET,
williamr@4: 		OTHER_INT_EN_FALL_CLR,
williamr@4: 		OTHER_INT_STS,
williamr@4: 		OTHER_INT_LATCH,
williamr@4: 		ID_INT_EN_RISE,
williamr@4: 		ID_INT_EN_RISE_SET,
williamr@4: 		ID_INT_EN_RISE_CLR,
williamr@4: 		ID_INT_EN_FALL,
williamr@4: 		ID_INT_EN_FALL_SET,
williamr@4: 		ID_INT_EN_FALL_CLR,
williamr@4: 		ID_INT_STS,
williamr@4: 		ID_INT_LATCH,
williamr@4: 		ID_STATUS,
williamr@4: 		CARKIT_SM_1_INT_EN,
williamr@4: 		CARKIT_SM_1_INT_EN_SET,
williamr@4: 		CARKIT_SM_1_INT_EN_CLR,
williamr@4: 		CARKIT_SM_1_INT_STS,
williamr@4: 		CARKIT_SM_1_INT_LATCH,
williamr@4: 		CARKIT_SM_2_INT_EN,
williamr@4: 		CARKIT_SM_2_INT_EN_SET,
williamr@4: 		CARKIT_SM_2_INT_EN_CLR,
williamr@4: 		CARKIT_SM_2_INT_STS,
williamr@4: 		CARKIT_SM_2_INT_LATCH,
williamr@4: 		CARKIT_SM_CTRL,
williamr@4: 		CARKIT_SM_CTRL_SET,
williamr@4: 		CARKIT_SM_CTRL_CLR,
williamr@4: 		CARKIT_SM_CMD,
williamr@4: 		CARKIT_SM_CMD_SET,
williamr@4: 		CARKIT_SM_CMD_CLR,
williamr@4: 		CARKIT_SM_CMD_STS,
williamr@4: 		CARKIT_SM_STATUS,
williamr@4: 		CARKIT_SM_NEXT_STATUS,
williamr@4: 		CARKIT_SM_ERR_STATUS,
williamr@4: 		CARKIT_SM_CTRL_STATE,
williamr@4: 		POWER_CTRL,
williamr@4: 		POWER_CTRL_SET,
williamr@4: 		POWER_CTRL_CLR,
williamr@4: 		OTHER_IFC_CTRL2,
williamr@4: 		OTHER_IFC_CTRL2_SET,
williamr@4: 		OTHER_IFC_CTRL2_CLR,
williamr@4: 		REG_CTRL_EN,
williamr@4: 		REG_CTRL_EN_SET,
williamr@4: 		REG_CTRL_EN_CLR,
williamr@4: 		REG_CTRL_ERROR,
williamr@4: 		OTHER_FUNC_CTRL2,
williamr@4: 		OTHER_FUNC_CTRL2_SET,
williamr@4: 		OTHER_FUNC_CTRL2_CLR,
williamr@4: 		CARKIT_ANA_CTRL,
williamr@4: 		CARKIT_ANA_CTRL_SET,
williamr@4: 		CARKIT_ANA_CTRL_CLR,
williamr@4: 		VBUS_DEBOUNCE = EGroup48 + 0xC0,
williamr@4: 		ID_DEBOUNCE,
williamr@4: 		TPH_DP_CON_MIN,
williamr@4: 		TPH_DP_CON_MAX,
williamr@4: 		TCR_DP_CON_MIN,
williamr@4: 		TCR_DP_CON_MAX,
williamr@4: 		TPH_DP_PD_SHORT,
williamr@4: 		TPH_CMD_DLY,
williamr@4: 		TPH_DET_RST,
williamr@4: 		TPH_AUD_BIAS,
williamr@4: 		TCR_UART_DET_MIN,
williamr@4: 		TCR_UART_DET_MAX,
williamr@4: 		TPH_ID_INT_PW = EGroup48 + 0xCC,
williamr@4: 		TACC_ID_INT_WAIT,
williamr@4: 		TACC_ID_INT_PW,
williamr@4: 		TPH_CMD_WAIT = EGroup48 + 0xD0,
williamr@4: 		TPH_ACK_WAIT,
williamr@4: 		TPH_DP_DISC_DET,
williamr@4: 		VBAT_TIMER,
williamr@4: 		CARKIT_4W_DEBUG = EGroup48 + 0xE0,
williamr@4: 		CARKIT_5W_DEBUG,
williamr@4: 		TEST_CTRL_CLR = EGroup48 + 0xEB,
williamr@4: 		TEST_CARKIT_SET,
williamr@4: 		TEST_CARKIT_CLR,
williamr@4: 		TEST_POWER_SET,
williamr@4: 		TEST_POWER_CLR,
williamr@4: 		TEST_ULPI,
williamr@4: 		TXVR_EN_TEST_SET,
williamr@4: 		TXVR_EN_TEST_CLR,
williamr@4: 		VBUS_EN_TEST,
williamr@4: 		ID_EN_TEST,
williamr@4: 		PSM_EN_TEST_SET,
williamr@4: 		PSM_EN_TEST_CLR,
williamr@4: 		PHY_TRIM_CTRL = EGroup48 + 0xFC,
williamr@4: 		PHY_PWR_CTRL,
williamr@4: 		PHY_CLK_CTRL,
williamr@4: 		PHY_CLK_CTRL_STS // 0x000000ff
williamr@4: 		};
williamr@4: 
williamr@4: 
williamr@4: 	enum TGroup49Registers
williamr@4: 		{
williamr@4: 		CODEC_MODE = EGroup49 + 1,
williamr@4: 		OPTION , 
williamr@4: 		MICBIAS_CTL = EGroup49 + 0x04,
williamr@4: 		ANAMICL,
williamr@4: 		ANAMICR,
williamr@4: 		AVADC_CTL,
williamr@4: 		ADCMICSEL,
williamr@4: 		DIGMIXING,
williamr@4: 		ATXL1PGA,
williamr@4: 		ATXR1PGA,
williamr@4: 		AVTXL2PGA,
williamr@4: 		AVTXR2PGA,
williamr@4: 		AUDIO_IF,
williamr@4: 		VOICE_IF,
williamr@4: 		ARXR1PGA,
williamr@4: 		ARXL1PGA,
williamr@4: 		ARXR2PGA,
williamr@4: 		ARXL2PGA,
williamr@4: 		VRXPGA,
williamr@4: 		VSTPGA,
williamr@4: 		VRX2ARXPGA,
williamr@4: 		AVDAC_CTL,
williamr@4: 		ARX2VTXPGA,
williamr@4: 		ARXL1_APGA_CTL,
williamr@4: 		ARXR1_APGA_CTL,
williamr@4: 		ARXL2_APGA_CTL,
williamr@4: 		ARXR2_APGA_CTL,
williamr@4: 		ATX2ARXPGA,
williamr@4: 		BT_IF,
williamr@4: 		BTPGA,
williamr@4: 		BTSTPGA,
williamr@4: 		EAR_CTL,
williamr@4: 		HS_SEL,
williamr@4: 		HS_GAIN_SET,
williamr@4: 		HS_POPN_SET,
williamr@4: 		PREDL_CTL,
williamr@4: 		PREDR_CTL,
williamr@4: 		PRECKL_CTL,
williamr@4: 		PRECKR_CTL,
williamr@4: 		HFL_CTL,
williamr@4: 		HFR_CTL, 
williamr@4: 		ALC_CTL, 
williamr@4: 		ALC_SET1,
williamr@4: 		ALC_SET2,
williamr@4: 		BOOST_CTL,
williamr@4: 		SOFTVOL_CTL,
williamr@4: 		DTMF_FREQSEL,
williamr@4: 		DTMF_TONEXT1H,
williamr@4: 		DTMF_TONEXT1L,
williamr@4: 		DTMF_TONEXT2H,
williamr@4: 		DTMF_TONEXT2L,
williamr@4: 		DTMF_TONOFF,
williamr@4: 		DTMF_WANONOFF,//  8 0x0000 0036
williamr@4: 		
williamr@4: 		I2S_RX_SCRAMBLE_H, 
williamr@4: 		I2S_RX_SCRAMBLE_M, 
williamr@4: 		I2S_RX_SCRAMBLE_L,
williamr@4: 		APLL_CTL,
williamr@4: 		DTMF_CTL,
williamr@4: 		DTMF_PGA_CTL2,
williamr@4: 		DTMF_PGA_CTL1,
williamr@4: 		MISC_SET_1,
williamr@4: 		PCMBTMUX,
williamr@4: 		RX_PATH_SEL,
williamr@4: 		VDL_APGA_CTL,
williamr@4: 		VIBRA_CTL,
williamr@4: 		VIBRA_SET,
williamr@4: 		ANAMIC_GAIN,
williamr@4: 		MISC_SET_2,// RW 8 0x0000 0049
williamr@4: 		
williamr@4: 		AUDIO_TEST_CTL = EGroup49 + 0x0000004C,
williamr@4: 		INT_TEST_CTL,
williamr@4: 		DAC_ADC_TEST_CTL,
williamr@4: 		RXTX_TRIM_IB,
williamr@4: 		CLD_CONTROL,
williamr@4: 		CLD_MODE_TIMING,
williamr@4: 		CLD_TRIM_RAMP,
williamr@4: 		CLD_TESTV_CTL,
williamr@4: 		APLL_TEST_CTL,
williamr@4: 		APLL_TEST_DIV,
williamr@4: 		APLL_TEST_CTL2,
williamr@4: 		APLL_TEST_CUR,
williamr@4: 		DIGMIC_BIAS1_CTL,
williamr@4: 		DIGMIC_BIAS2_CTL,
williamr@4: 		RX_OFFSET_VOICE,
williamr@4: 		RX_OFFSET_AL1,
williamr@4: 		RX_OFFSET_AR1,
williamr@4: 		RX_OFFSET_AL2,
williamr@4: 		RX_OFFSET_AR2,
williamr@4: 		OFFSET1,
williamr@4: 		OFFSET2,
williamr@4: 		
williamr@4: 		
williamr@4: 		GPIODATAIN1  = EGroup49 + 0x00000098,
williamr@4: 		GPIODATAIN2, 
williamr@4: 		GPIODATAIN3, 
williamr@4: 		GPIODATADIR1, 
williamr@4: 		GPIODATADIR2, 
williamr@4: 		GPIODATADIR3, 
williamr@4: 		GPIODATAOUT1,
williamr@4: 		GPIODATAOUT2,
williamr@4: 		GPIODATAOUT3,
williamr@4: 		CLEARGPIODATAOUT1,
williamr@4: 		CLEARGPIODATAOUT2,
williamr@4: 		CLEARGPIODATAOUT3,
williamr@4: 		SETGPIODATAOUT1,
williamr@4: 		SETGPIODATAOUT2,
williamr@4: 		SETGPIODATAOUT3,
williamr@4: 		GPIO_DEBEN1,
williamr@4: 		GPIO_DEBEN3,
williamr@4: 		GPIO_CTRL ,
williamr@4: 		GPIOPUPDCTR1,
williamr@4: 		GPIOPUPDCTR2,
williamr@4: 		GPIOPUPDCTR3,
williamr@4: 		GPIOPUPDCTR4,
williamr@4: 		GPIOPUPDCTR5,
williamr@4: 		GPIO_TEST,
williamr@4: 		GPIO_ISR1A = EGroup49 + 0xb1,
williamr@4: 		GPIO_ISR2A,
williamr@4: 		GPIO_ISR3A,
williamr@4: 		GPIO_IMR1A, // 
williamr@4: 		GPIO_IMR2A,
williamr@4: 		GPIO_IMR3A,
williamr@4: 		GPIO_ISR1B,
williamr@4: 		GPIO_ISR2B,
williamr@4: 		GPIO_ISR3B,
williamr@4: 		GPIO_IMR1B,
williamr@4: 		GPIO_IMR2B,
williamr@4: 		GPIO_IMR3B,
williamr@4: 		GPIO_SIR1,
williamr@4: 		GPIO_SIR2,
williamr@4: 		GPIO_SIR3,
williamr@4: 		GPIO_EDR1,
williamr@4: 		GPIO_EDR2,
williamr@4: 		GPIO_EDR3,
williamr@4: 		GPIO_EDR4,
williamr@4: 		GPIO_EDR5,
williamr@4: 		GPIO_SIH_CTRL,
williamr@4: 		
williamr@4: 		PIH_ISR_P1 = EGroup49 + 0x00000081,
williamr@4: 		PIH_ISR_P2,
williamr@4: 		PIH_SIR ,
williamr@4: 		IDCODE_7_0 = EGroup49 + 0x00000085,
williamr@4: 		IDCODE_15_8,
williamr@4: 		IDCODE_23_16,
williamr@4: 		IDCODE_31_24,
williamr@4: 		DIEID_7_0,
williamr@4: 		DIEID_15_8,
williamr@4: 		DIEID_23_16,
williamr@4: 		DIEID_31_24,
williamr@4: 		DIEID_39_32,
williamr@4: 		DIEID_47_40,
williamr@4: 		DIEID_55_48,
williamr@4: 		DIEID_63_56,
williamr@4: 		GPBR1,
williamr@4: 		PMBR1,
williamr@4: 		PMBR2,
williamr@4: 		GPPUPDCTR1,
williamr@4: 		GPPUPDCTR2,
williamr@4: 		GPPUPDCTR3,
williamr@4: 		UNLOCK_TEST_REG,
williamr@4: 		};
williamr@4: 
williamr@4: 
williamr@4: 
williamr@4: 	/*
williamr@4: 	Note: Access to the following registers is protected:
williamr@4: 	· IDCODE_7_0
williamr@4: 	· IDCODE_15_8
williamr@4: 	· IDCODE_23_16
williamr@4: 	· IDCODE_31_24
williamr@4: 	· DIEID_7_0
williamr@4: 	· DIEID_15_8
williamr@4: 	· DIEID_23_16
williamr@4: 	· DIEID_31_24
williamr@4: 	· DIEID_39_32
williamr@4: 	· DIEID_47_40
williamr@4: 	· DIEID_55_48
williamr@4: 	· DIEID_63_56
williamr@4: 	To read these registers, the UNLOCK_TEST_REG register must first be written with 0x49.
williamr@4: 	Table 2-29. GPPUPDCTR1
williamr@4: 	Address Offset 0x0F
williamr@4: 	Physical Address 0x0000 0094 Instance INT_SCINTBR
williamr@4: 	*/
williamr@4: 
williamr@4: 	enum TGroup4aRegisters
williamr@4: 		{
williamr@4: 		CTRL1 = EGroup4a + 0,
williamr@4: 		CTRL2,
williamr@4: 		RTSELECT_LSB,
williamr@4: 		RTSELECT_MSB,
williamr@4: 		RTAVERAGE_LSB,
williamr@4: 		RTAVERAGE_MSB,
williamr@4: 		SW1SELECT_LSB,
williamr@4: 		SW1SELECT_MSB,
williamr@4: 		SW1AVERAGE_LSB,
williamr@4: 		SW1AVERAGE_MSB,
williamr@4: 		SW2SELECT_LSB,
williamr@4: 		SW2SELECT_MSB,
williamr@4: 		SW2AVERAGE_LSB,
williamr@4: 		SW2AVERAGE_MSB,
williamr@4: 		BCI_USBAVERAGE,
williamr@4: 		ACQUISITION,
williamr@4: 		USBREF_LSB,
williamr@4: 		USBREF_MSB,
williamr@4: 		CTRL_SW1,
williamr@4: 		CTRL_SW2,
williamr@4: 		MADC_TEST,
williamr@4: 		GP_MADC_TEST1,
williamr@4: 		GP_MADC_TEST2,
williamr@4: 		RTCH0_LSB, 
williamr@4: 		RTCH0_MSB, 
williamr@4: 		RTCH1_LSB, 
williamr@4: 		RTCH1_MSB, 
williamr@4: 		RTCH2_LSB, 
williamr@4: 		RTCH2_MSB, 
williamr@4: 		RTCH3_LSB, 
williamr@4: 		RTCH3_MSB,
williamr@4: 		RTCH4_LSB,
williamr@4: 		RTCH4_MSB,
williamr@4: 		RTCH5_LSB,
williamr@4: 		RTCH5_MSB,
williamr@4: 		RTCH6_LSB,
williamr@4: 		RTCH6_MSB,
williamr@4: 		RTCH7_LSB,
williamr@4: 		RTCH7_MSB,
williamr@4: 		RTCH8_LSB,
williamr@4: 		RTCH8_MSB,
williamr@4: 		RTCH9_LSB,
williamr@4: 		RTCH9_MSB,
williamr@4: 		RTCH10_LSB,
williamr@4: 		RTCH10_MSB,
williamr@4: 		RTCH11_LSB,
williamr@4: 		RTCH11_MSB,
williamr@4: 		RTCH12_LSB,
williamr@4: 		RTCH12_MSB,
williamr@4: 		RTCH13_LSB,
williamr@4: 		RTCH13_MSB,
williamr@4: 		RTCH14_LSB,
williamr@4: 		RTCH14_MSB,
williamr@4: 		RTCH15_LSB,
williamr@4: 		RTCH15_MSB,
williamr@4: 		GPCH0_LSB,
williamr@4: 		GPCH0_MSB,
williamr@4: 		GPCH1_LSB,
williamr@4: 		GPCH1_MSB,
williamr@4: 		GPCH2_LSB,
williamr@4: 		GPCH2_MSB, 
williamr@4: 		GPCH3_LSB,
williamr@4: 		GPCH3_MSB,
williamr@4: 		GPCH4_LSB,
williamr@4: 		GPCH4_MSB,
williamr@4: 		GPCH5_LSB,
williamr@4: 		GPCH5_MSB,
williamr@4: 		GPCH6_LSB,
williamr@4: 		GPCH6_MSB,
williamr@4: 		GPCH7_LSB,
williamr@4: 		GPCH7_MSB,
williamr@4: 		GPCH8_LSB,
williamr@4: 		GPCH8_MSB,
williamr@4: 		GPCH9_LSB,
williamr@4: 		GPCH9_MSB,
williamr@4: 		GPCH10_LSB,
williamr@4: 		GPCH10_MSB,
williamr@4: 		GPCH11_LSB,
williamr@4: 		GPCH11_MSB,
williamr@4: 		GPCH12_LSB,
williamr@4: 		GPCH12_MSB,
williamr@4: 		GPCH13_LSB,
williamr@4: 		GPCH13_MSB,
williamr@4: 		GPCH14_LSB,
williamr@4: 		GPCH14_MSB,
williamr@4: 		GPCH15_LSB,
williamr@4: 		GPCH15_MSB,
williamr@4: 		BCICH0_LSB,
williamr@4: 		BCICH0_MSB,
williamr@4: 		BCICH1_LSB,
williamr@4: 		BCICH1_MSB,
williamr@4: 		BCICH2_LSB,
williamr@4: 		BCICH2_MSB,
williamr@4: 		BCICH3_LSB,
williamr@4: 		BCICH3_MSB,
williamr@4: 		BCICH4_LSB,
williamr@4: 		BCICH4_MSB,
williamr@4: 		MADC_ISR1,
williamr@4: 		MADC_IMR1,
williamr@4: 		MADC_ISR2,
williamr@4: 		MADC_IMR2,
williamr@4: 		MADC_SIR,
williamr@4: 		MADC_EDR,
williamr@4: 		MADC_SIH_CTRL,
williamr@4: 		BCIMDEN,
williamr@4: 		BCIMDKEY,
williamr@4: 		BCIMSTATEC,
williamr@4: 		BCIMSTATEP,
williamr@4: 		BCIVBAT1,
williamr@4: 		BCIVBAT2,
williamr@4: 		BCITBAT1,
williamr@4: 		BCITBAT2,
williamr@4: 		BCIICHG1,
williamr@4: 		BCIICHG2,
williamr@4: 		BCIVAC1,
williamr@4: 		BCIVAC2,
williamr@4: 		BCIVBUS1,
williamr@4: 		BCIVBUS2,
williamr@4: 		BCIMFSTS2,
williamr@4: 		BCIMFSTS3,
williamr@4: 		BCIMFSTS4,
williamr@4: 		BCIMFKEY,
williamr@4: 		BCIMFEN1,
williamr@4: 		BCIMFEN2,
williamr@4: 		BCIMFEN3,
williamr@4: 		BCIMFEN4,
williamr@4: 		BCIMFTH1,
williamr@4: 		BCIMFTH2,
williamr@4: 		BCIMFTH3,
williamr@4: 		BCIMFTH4,
williamr@4: 		BCIMFTH5,
williamr@4: 		BCIMFTH6,
williamr@4: 		BCIMFTH7,
williamr@4: 		BCIMFTH8,	
williamr@4: 		BCIMFTH9, 
williamr@4: 		BCITIMER1,
williamr@4: 		BCITIMER2,
williamr@4: 		BCIWDKEY,
williamr@4: 		BCIWD,
williamr@4: 		BCICTL1,
williamr@4: 		BCICTL2,
williamr@4: 		BCIVREF1,
williamr@4: 		BCIVREF2,
williamr@4: 		BCIIREF1,
williamr@4: 		BCIIREF2,
williamr@4: 		BCIPWM2,
williamr@4: 		BCIPWM1,
williamr@4: 		BCITRIM1,
williamr@4: 		BCITRIM2,
williamr@4: 		BCITRIM3,
williamr@4: 		BCITRIM4,
williamr@4: 		BCIVREFCOMB1,
williamr@4: 		BCIVREFCOMB2,
williamr@4: 		BCIIREFCOMB1,
williamr@4: 		BCIIREFCOMB2,
williamr@4: 
williamr@4: 		BCIISR1A  = EGroup4a + 0x000000B9,
williamr@4: 		BCIISR2A, 
williamr@4: 		BCIIMR1A,
williamr@4: 		BCIIMR2A, 
williamr@4: 		BCIISR1B, 
williamr@4: 		BCIISR2B,
williamr@4: 		BCIIMR1B, 
williamr@4: 		BCIIMR2B, //0x000000c0 
williamr@4: 		 
williamr@4: 		BCIEDR1  = EGroup4a + 0x000000c3, 
williamr@4: 		BCIEDR2, 
williamr@4: 		BCIEDR3, 
williamr@4: 		BCISIHCTRL, // c6
williamr@4: 		
williamr@4: 		KEYP_CTRL_REG = EGroup4a + 0x000000D2,
williamr@4: 		KEY_DEB_REG,
williamr@4: 		LONG_KEY_REG1,
williamr@4: 		LK_PTV_REG,
williamr@4: 		TIME_OUT_REG1,
williamr@4: 		TIME_OUT_REG2,
williamr@4: 		KBC_REG,
williamr@4: 		KBR_REG,
williamr@4: 		KEYP_SMS,
williamr@4: 		FULL_CODE_7_0,
williamr@4: 		FULL_CODE_15_8,
williamr@4: 		FULL_CODE_23_16,	
williamr@4: 		FULL_CODE_31_24,
williamr@4: 		FULL_CODE_39_32,
williamr@4: 		FULL_CODE_47_40,
williamr@4: 		FULL_CODE_55_48,
williamr@4: 		FULL_CODE_63_56,
williamr@4: 		KEYP_ISR1,
williamr@4: 		KEYP_IMR1,
williamr@4: 		KEYP_ISR2,
williamr@4: 		KEYP_IMR2,
williamr@4: 		KEYP_SIR,
williamr@4: 		KEYP_EDR,
williamr@4: 		KEYP_SIH_CTRL,
williamr@4: 		
williamr@4: 		LEDEN = EGroup4a + 0x000000EE,
williamr@4: 		PWMAON,
williamr@4: 		PWMAOFF,
williamr@4: 		PWMBON, 
williamr@4: 		PWMBOFF,
williamr@4: 		
williamr@4: 		PWM1ON= EGroup4a + 0x000000FB,
williamr@4: 		PWM1OFF,
williamr@4: 		PWM0ON = EGroup4a + 0x000000F8,
williamr@4: 		PWM0OFF,
williamr@4: 		};
williamr@4: 
williamr@4: 	enum TGroup4bRegisters
williamr@4: 		{
williamr@4: 		SECURED_REG_A = EGroup4b + 0,
williamr@4: 		SECURED_REG_B,
williamr@4: 		SECURED_REG_C,
williamr@4: 		SECURED_REG_D,
williamr@4: 		SECURED_REG_E,
williamr@4: 		SECURED_REG_F,
williamr@4: 		SECURED_REG_G,
williamr@4: 		SECURED_REG_H, 
williamr@4: 		SECURED_REG_I, 
williamr@4: 		SECURED_REG_J,
williamr@4: 		SECURED_REG_K,
williamr@4: 		SECURED_REG_L,
williamr@4: 		SECURED_REG_M,
williamr@4: 		SECURED_REG_N,
williamr@4: 		SECURED_REG_O,
williamr@4: 		SECURED_REG_P,
williamr@4: 		SECURED_REG_Q,
williamr@4: 		SECURED_REG_R,
williamr@4: 		SECURED_REG_S,
williamr@4: 		SECURED_REG_U,
williamr@4: 		BACKUP_REG_A,
williamr@4: 		BACKUP_REG_B, 
williamr@4: 		BACKUP_REG_C,
williamr@4: 		BACKUP_REG_D, 
williamr@4: 		BACKUP_REG_E, 
williamr@4: 		BACKUP_REG_F,
williamr@4: 		BACKUP_REG_G,
williamr@4: 		BACKUP_REG_H,
williamr@4: 		PWR_ISR1 = EGroup4b + 0x2e,
williamr@4: 		PWR_IMR1,
williamr@4: 		PWR_ISR2,
williamr@4: 		PWR_IMR2,
williamr@4: 		PWR_SIR, 
williamr@4: 		PWR_EDR1,
williamr@4: 		PWR_EDR2,
williamr@4: 		PWR_SIH_CTRL,
williamr@4: 		CFG_P1_TRANSITION,
williamr@4: 		CFG_P2_TRANSITION,
williamr@4: 		CFG_P3_TRANSITION,
williamr@4: 		CFG_P123_TRANSITION,
williamr@4: 		STS_BOOT,
williamr@4: 		CFG_BOOT, 
williamr@4: 		SHUNDAN,
williamr@4: 		BOOT_BCI,
williamr@4: 		CFG_PWRANA1,
williamr@4: 		CFG_PWRANA2,
williamr@4: 		BGAP_TRIM,
williamr@4: 		BACKUP_MISC_STS,
williamr@4: 		BACKUP_MISC_CFG,
williamr@4: 		BACKUP_MISC_TST,
williamr@4: 		PROTECT_KEY, 
williamr@4: 		STS_HW_CONDITIONS, 
williamr@4: 		P1_SW_EVENTS, 
williamr@4: 		P2_SW_EVENTS, 
williamr@4: 		P3_SW_EVENTS, 
williamr@4: 		STS_P123_STATE,
williamr@4: 		PB_CFG, 
williamr@4: 		PB_WORD_MSB,
williamr@4: 		PB_WORD_LSB,
williamr@4: 		RESERVED_A,
williamr@4: 		RESERVED_B,
williamr@4: 		RESERVED_C,
williamr@4: 		RESERVED_D,
williamr@4: 		RESERVED_E,
williamr@4: 		SEQ_ADD_W2P,
williamr@4: 		SEQ_ADD_P2A,
williamr@4: 		SEQ_ADD_A2W,
williamr@4: 		SEQ_ADD_A2S,
williamr@4: 		SEQ_ADD_S2A12,
williamr@4: 		SEQ_ADD_S2A3,
williamr@4: 		SEQ_ADD_WARM,
williamr@4: 		MEMORY_ADDRESS,
williamr@4: 		MEMORY_DATA,
williamr@4: 		SC_CONFIG, 
williamr@4: 		SC_DETECT1,
williamr@4: 		SC_DETECT2,
williamr@4: 		WATCHDOG_CFG,
williamr@4: 		IT_CHECK_CFG,
williamr@4: 		VIBRATOR_CFG,
williamr@4: 		DCDC_GLOBAL_CFG,
williamr@4: 		VDD1_TRIM1,
williamr@4: 		VDD1_TRIM2,
williamr@4: 		VDD2_TRIM1,
williamr@4: 		VDD2_TRIM2,
williamr@4: 		VIO_TRIM1,
williamr@4: 		VIO_TRIM2,
williamr@4: 		MISC_CFG,
williamr@4: 		LS_TST_A,
williamr@4: 		LS_TST_B,
williamr@4: 		LS_TST_C,
williamr@4: 		LS_TST_D,
williamr@4: 		BB_CFG,
williamr@4: 		MISC_TST,
williamr@4: 		TRIM1,
williamr@4: 		TRIM2,
williamr@4: 		DCDC_TIMEOUT,
williamr@4: 		VAUX1_DEV_GRP,
williamr@4: 		VAUX1_TYPE,
williamr@4: 		VAUX1_REMAP,
williamr@4: 		VAUX1_DEDICATED,
williamr@4: 		VAUX2_DEV_GRP, 
williamr@4: 		VAUX2_TYPE, 
williamr@4: 		VAUX2_REMAP,
williamr@4: 		VAUX2_DEDICATED, 
williamr@4: 		VAUX3_DEV_GRP,
williamr@4: 		VAUX3_TYPE, 
williamr@4: 		VAUX3_REMAP, 
williamr@4: 		VAUX3_DEDICATED,
williamr@4: 		VAUX4_DEV_GRP,
williamr@4: 		VAUX4_TYPE,
williamr@4: 		VAUX4_REMAP,
williamr@4: 		VAUX4_DEDICATED, 
williamr@4: 		VMMC1_DEV_GRP,
williamr@4: 		VMMC1_TYPE,
williamr@4: 		VMMC1_REMAP,
williamr@4: 		VMMC1_DEDICATED,
williamr@4: 		VMMC2_DEV_GRP,
williamr@4: 		VMMC2_TYPE,
williamr@4: 		VMMC2_REMAP,
williamr@4: 		VMMC2_DEDICATED,
williamr@4: 		VPLL1_DEV_GRP,
williamr@4: 		VPLL1_TYPE,
williamr@4: 		VPLL1_REMAP,
williamr@4: 		VPLL1_DEDICATED,
williamr@4: 		VPLL2_DEV_GRP,
williamr@4: 		VPLL2_TYPE,
williamr@4: 		VPLL2_REMAP,
williamr@4: 		VPLL2_DEDICATED,
williamr@4: 		VSIM_DEV_GRP,
williamr@4: 		VSIM_TYPE,
williamr@4: 		VSIM_REMAP,
williamr@4: 		VSIM_DEDICATED,
williamr@4: 		VDAC_DEV_GRP,
williamr@4: 		VDAC_TYPE,
williamr@4: 		VDAC_REMAP,
williamr@4: 		VDAC_DEDICATED,
williamr@4: 		VINTANA1_DEV_GRP,
williamr@4: 		VINTANA1_TYPE,
williamr@4: 		VINTANA1_REMAP,
williamr@4: 		VINTANA1_DEDICATED,
williamr@4: 		VINTANA2_DEV_GRP,
williamr@4: 		VINTANA2_TYPE,
williamr@4: 		VINTANA2_REMAP,
williamr@4: 		VINTANA2_DEDICATED,
williamr@4: 		VINTDIG_DEV_GRP,
williamr@4: 		VINTDIG_TYPE,
williamr@4: 		VINTDIG_REMAP,
williamr@4: 		VINTDIG_DEDICATED,
williamr@4: 		VIO_DEV_GRP,
williamr@4: 		VIO_TYPE,
williamr@4: 		VIO_REMAP,
williamr@4: 		VIO_CFG,
williamr@4: 		VIO_MISC_CFG,
williamr@4: 		VIO_TEST1,
williamr@4: 		VIO_TEST2,
williamr@4: 		VIO_OSC,
williamr@4: 		VIO_RESERVED,
williamr@4: 		VIO_VSEL,
williamr@4: 		VDD1_DEV_GRP,
williamr@4: 		VDD1_TYPE,
williamr@4: 		VDD1_REMAP,
williamr@4: 		VDD1_CFG,
williamr@4: 		VDD1_MISC_CFG,
williamr@4: 		VDD1_TEST1,
williamr@4: 		VDD1_TEST2,
williamr@4: 		VDD1_OSC,
williamr@4: 		VDD1_RESERVED,
williamr@4: 		VDD1_VSEL,
williamr@4: 		VDD1_VMODE_CFG,
williamr@4: 		VDD1_VFLOOR,
williamr@4: 		VDD1_VROOF,
williamr@4: 		VDD1_STEP,
williamr@4: 		VDD2_DEV_GRP,
williamr@4: 		VDD2_TYPE,
williamr@4: 		VDD2_REMAP,
williamr@4: 		VDD2_CFG,
williamr@4: 		VDD2_MISC_CFG,
williamr@4: 		VDD2_TEST1,
williamr@4: 		VDD2_TEST2,
williamr@4: 		VDD2_OSC,
williamr@4: 		VDD2_RESERVED,
williamr@4: 		VDD2_VSEL,
williamr@4: 		VDD2_VMODE_CFG,
williamr@4: 		VDD2_VFLOOR,
williamr@4: 		VDD2_VROOF,
williamr@4: 		VDD2_STEP,
williamr@4: 		VUSB1V5_DEV_GRP,
williamr@4: 		VUSB1V5_TYPE,
williamr@4: 		VUSB1V5_REMAP,
williamr@4: 		VUSB1V8_DEV_GRP,
williamr@4: 		VUSB1V8_TYPE,
williamr@4: 		VUSB1V8_REMAP,
williamr@4: 		VUSB3V1_DEV_GRP,
williamr@4: 		VUSB3V1_TYPE,
williamr@4: 		VUSB3V1_REMAP,
williamr@4: 		VUSBCP_DEV_GRP,
williamr@4: 		VUSBCP_TYPE,
williamr@4: 		VUSBCP_REMAP,
williamr@4: 		VUSB_DEDICATED1,
williamr@4: 		VUSB_DEDICATED2,
williamr@4: 		REGEN_DEV_GRP,
williamr@4: 		REGEN_TYPE,
williamr@4: 		REGEN_REMAP,
williamr@4: 		NRESPWRON_DEV_GRP,
williamr@4: 		NRESPWRON_TYPE,
williamr@4: 		NRESPWRON_REMAP,
williamr@4: 		CLKEN_DEV_GRP,
williamr@4: 		CLKEN_TYPE,
williamr@4: 		CLKEN_REMAP,
williamr@4: 		SYSEN_DEV_GRP,
williamr@4: 		SYSEN_TYPE,
williamr@4: 		SYSEN_REMAP,
williamr@4: 		HFCLKOUT_DEV_GRP,
williamr@4: 		HFCLKOUT_TYPE,
williamr@4: 		HFCLKOUT_REMAP,
williamr@4: 		E32KCLKOUT_DEV_GRP,
williamr@4: 		E32KCLKOUT_TYPE,
williamr@4: 		E32KCLKOUT_REMAP,
williamr@4: 		TRITON_RESET_DEV_GRP,
williamr@4: 		TRITON_RESET_TYPE,
williamr@4: 		TRITON_RESET_REMAP,
williamr@4: 		MAINREF_DEV_GRP,
williamr@4: 		MAINREF_TYPE,
williamr@4: 		MAINREF_REMAP,
williamr@4: 		SECONDS_REG,
williamr@4: 		MINUTES_REG,
williamr@4: 		HOURS_REG,
williamr@4: 		DAYS_REG,
williamr@4: 		MONTHS_REG,
williamr@4: 		YEARS_REG,
williamr@4: 		WEEKS_REG,
williamr@4: 		ALARM_SECONDS_REG,
williamr@4: 		ALARM_MINUTES_REG,
williamr@4: 		ALARM_HOURS_REG,
williamr@4: 		ALARM_DAYS_REG,
williamr@4: 		ALARM_MONTHS_REG,
williamr@4: 		ALARM_YEARS_REG,
williamr@4: 		RTC_CTRL_REG,
williamr@4: 		RTC_STATUS_REG,
williamr@4: 		RTC_INTERRUPTS_REG,
williamr@4: 		RTC_COMP_LSB_REG,
williamr@4: 		RTC_COMP_MSB_REG, //2d
williamr@4: 		};
williamr@4: 	} // namespace Register
williamr@4: 
williamr@4: 	namespace DCDC_GLOBAL_CFG
williamr@4: 		{
williamr@4: 		const TUint16		Addr = Register::DCDC_GLOBAL_CFG;
williamr@4: 
williamr@4: 		const TUint8	CARD_DETECT_2_LEVEL = KBit7;
williamr@4: 		const TUint8	CARD_DETECT_1_LEVEL = KBit6;
williamr@4: 		const TUint8	REGEN_PU_DISABLE = KBit5;
williamr@4: 		const TUint8	SYSEN_PU_DISABLE = KBit4;
williamr@4: 		const TUint8	SMARTREFLEX_ENABLE = KBit3;
williamr@4: 		const TUint8	CARD_DETECT_CFG = KBit2;
williamr@4: 		const TUint8	CLK_32K_DEGATE = KBit1;
williamr@4: 		const TUint8	CLK_HF_DEGATE = KBit0;
williamr@4: 		};
williamr@4: 
williamr@4: 
williamr@4: 	namespace _VMODE_CFG_
williamr@4: 		{
williamr@4: 		const TUint8	STS_BUSY	= KBit5;
williamr@4: 		const TUint8	STS_ROOF	= KBit4;
williamr@4: 		const TUint8	STS_FLOOR	= KBit3;
williamr@4: 		const TUint8	DCDC_SLP	= KBit2;
williamr@4: 		const TUint8	READ_REG	= KBit1;
williamr@4: 		const TUint8	ENABLE_VMODE	= KBit0;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace VDD1_VMODE_CFG
williamr@4: 		{
williamr@4: 		const TUint16		Addr = Register::VDD1_VMODE_CFG;
williamr@4: 		using namespace _VMODE_CFG_;
williamr@4: 		};
williamr@4: 
williamr@4: 	namespace VDD2_VMODE_CFG
williamr@4: 		{
williamr@4: 		const TUint16		Addr = Register::VDD2_VMODE_CFG;
williamr@4: 		using namespace _VMODE_CFG_;
williamr@4: 		};
williamr@4: 
williamr@4: 	namespace _VDDx_VSEL_
williamr@4: 		{
williamr@4: 		namespace Mask
williamr@4: 			{
williamr@4: 			const TUint8	VSEL	= 0x7F;
williamr@4: 			}
williamr@4: 
williamr@4: 		namespace Shift
williamr@4: 			{
williamr@4: 			const TUint		VSEL = 0;
williamr@4: 			}
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace VDD1_VSEL
williamr@4: 		{
williamr@4: 		const TUint16		Addr = Register::VDD1_VSEL;
williamr@4: 		using namespace _VDDx_VSEL_;
williamr@4: 		};
williamr@4: 
williamr@4: 	namespace VDD2_VSEL
williamr@4: 		{
williamr@4: 		const TUint16	Addr = Register::VDD2_VSEL;
williamr@4: 		using namespace _VDDx_VSEL_;
williamr@4: 		};
williamr@4: 
williamr@4: 	namespace _PWR_I_1_
williamr@4: 		{
williamr@4: 		const TUint8 PWR_SC_DETECT 		= KBit7;
williamr@4: 		const TUint8 PWR_MBCHG	   		= KBit6;
williamr@4: 		const TUint8 PWR_PWROK_TIMEOUT	= KBit5;
williamr@4: 		const TUint8 PWR_HOT_DIE		= KBit4;
williamr@4: 		const TUint8 PWR_RTC_IT			= KBit3;
williamr@4: 		const TUint8 PWR_USB_PRES		= KBit2;
williamr@4: 		const TUint8 PWR_CHG_PRES		= KBit1;
williamr@4: 		const TUint8 PWR_CHG_PWRONS		= KBit0;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace PWR_IMR1
williamr@4: 		{
williamr@4: 		const TUint16	Addr = Register::PWR_IMR1;
williamr@4: 		using namespace _PWR_I_1_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace PWR_ISR1
williamr@4: 		{
williamr@4: 		const TUint16	Addr = Register::PWR_ISR1;
williamr@4: 		using namespace _PWR_I_1_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace _MADC_I_1_
williamr@4: 		{
williamr@4: 		const TUint8 MADC_USB_ISR1		= KBit3;
williamr@4: 		const TUint8 MADC_SW2_ISR1		= KBit2;
williamr@4: 		const TUint8 MADC_SW1_ISR1		= KBit1;
williamr@4: 		const TUint8 MADC_RT_ISR1		= KBit0;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace MADC_IMR1
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::MADC_IMR1;
williamr@4: 		using namespace _MADC_I_1_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace MADC_ISR1
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::MADC_ISR1;
williamr@4: 		using namespace _MADC_I_1_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace _GPIO_I_1A_
williamr@4: 		{
williamr@4: 		const TUint8 GPIO7ISR1 			= KBit7;
williamr@4: 		const TUint8 GPIO6ISR1 			= KBit6;
williamr@4: 		const TUint8 GPIO5ISR1 			= KBit5;
williamr@4: 		const TUint8 GPIO4ISR1 			= KBit4;
williamr@4: 		const TUint8 GPIO3ISR1 			= KBit3;
williamr@4: 		const TUint8 GPIO2ISR1 			= KBit2;
williamr@4: 		const TUint8 GPIO1ISR1 			= KBit1;
williamr@4: 		const TUint8 GPIO0ISR1 			= KBit0;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace _GPIO_I_2A_
williamr@4: 		{
williamr@4: 		const TUint8 GPIO15ISR2 		= KBit7;
williamr@4: 		const TUint8 GPIO14ISR2 		= KBit6;
williamr@4: 		const TUint8 GPIO13ISR2 		= KBit5;
williamr@4: 		const TUint8 GPIO12ISR2 		= KBit4;
williamr@4: 		const TUint8 GPIO11ISR2 		= KBit3;
williamr@4: 		const TUint8 GPIO10ISR2 		= KBit2;
williamr@4: 		const TUint8 GPIO9ISR2 			= KBit1;
williamr@4: 		const TUint8 GPIO8ISR2 			= KBit0;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace _GPIO_I_3A_
williamr@4: 		{
williamr@4: 		const TUint8 GPIO17ISR3 		= KBit1;
williamr@4: 		const TUint8 GPIO16ISR3 		= KBit0;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace GPIO_IMR1A
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::GPIO_IMR1A;
williamr@4: 		using namespace _GPIO_I_1A_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace GPIO_ISR1A
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::GPIO_ISR1A;
williamr@4: 		using namespace _GPIO_I_1A_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace GPIO_IMR2A
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::GPIO_IMR2A;
williamr@4: 		using namespace _GPIO_I_2A_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace GPIO_ISR2A
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::GPIO_ISR2A;
williamr@4: 		using namespace _GPIO_I_2A_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace GPIO_IMR3A
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::GPIO_IMR3A;
williamr@4: 		using namespace _GPIO_I_3A_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace GPIO_ISR3A
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::GPIO_ISR3A;
williamr@4: 		using namespace _GPIO_I_3A_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace _BCI_I_1_
williamr@4: 		{
williamr@4: 		const TUint8 BCI_BATSTS_ISR1 		= KBit7;
williamr@4: 		const TUint8 BCI_TBATOR1_ISR1 		= KBit6;
williamr@4: 		const TUint8 BCI_TBATOR2_ISR1 		= KBit5;
williamr@4: 		const TUint8 BCI_ICHGEOC_ISR1 		= KBit4;
williamr@4: 		const TUint8 BCI_ICHGLOW_ISR1ASTO 	= KBit3;
williamr@4: 		const TUint8 BCI_IICHGHIGH_ISR1 	= KBit2;
williamr@4: 		const TUint8 BCI_TMOVF_ISR1 		= KBit1;
williamr@4: 		const TUint8 BCI_WOVF_ISR1 			= KBit0;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace _BCI_I_2_
williamr@4: 		{
williamr@4: 		const TUint8 BCI_ACCHGOV_ISR1 		= KBit3;
williamr@4: 		const TUint8 BCI_VBUSOV_ISR1 		= KBit2;
williamr@4: 		const TUint8 BCI_VBATOV_ISR1 		= KBit1;
williamr@4: 		const TUint8 BCI_VBATLVL_ISR1 		= KBit0;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace BCIIMR1A
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::BCIIMR1A;
williamr@4: 		using namespace _BCI_I_1_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace BCIISR1A
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::BCIISR1A;
williamr@4: 		using namespace _BCI_I_1_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace BCIIMR2A
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::BCIIMR2A;
williamr@4: 		using namespace _BCI_I_2_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace BCIISR2A
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::BCIISR2A;
williamr@4: 		using namespace _BCI_I_2_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace _KEYP_I_
williamr@4: 		{
williamr@4: 		const TUint8 KEYP_ITMISR1 			= KBit3;
williamr@4: 		const TUint8 KEYP_ITTOISR1 			= KBit2;
williamr@4: 		const TUint8 KEYP_ITLKISR1  		= KBit1;
williamr@4: 		const TUint8 KEYP_ITKPISR1 			= KBit0;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace KEYP_IMR1
williamr@4: 		{
williamr@4: 		const TUint16 Addr   = Register::KEYP_IMR1;
williamr@4: 		using namespace _KEYP_I_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace KEYP_ISR1
williamr@4: 		{
williamr@4: 		const TUint16 Addr   = Register::KEYP_ISR1;
williamr@4: 		using namespace _KEYP_I_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace _USB_INT_EN_
williamr@4: 		{
williamr@4: 		const TUint8 USB_INTSTS_IDGND 				= KBit4;
williamr@4: 		const TUint8 USB_INTSTS_SESSEND				= KBit3;
williamr@4: 		const TUint8 USB_INTSTS_SESSVALID			= KBit2;
williamr@4: 		const TUint8 USB_INTSTS_VBUSVALID			= KBit1;
williamr@4: 		const TUint8 USB_INTSTS_HOSTDISCONNECT		= KBit0;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace USB_INT_EN_RISE_SET
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::USB_INT_EN_RISE_SET;
williamr@4: 		using namespace _USB_INT_EN_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace USB_INT_EN_RISE_CLR
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::USB_INT_EN_RISE_CLR;
williamr@4: 		using namespace _USB_INT_EN_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace USB_INT_STS
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::USB_INT_STS;
williamr@4: 		using namespace _USB_INT_EN_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace _OTHER_INT_
williamr@4: 		{
williamr@4: 		const TUint8 OTHER_INT_VB_SESS_VLD		= KBit7;
williamr@4: 		const TUint8 OTHER_INT_DM_HI			= KBit6;
williamr@4: 		const TUint8 OTHER_INT_DP_HI			= KBit5;
williamr@4: 		const TUint8 OTHER_INT_MANU				= KBit1;
williamr@4: 		const TUint8 OTHER_INT_ABNORMAL_STRESS	= KBit0;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace OTHER_INT_EN_RISE_SET
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::OTHER_INT_EN_RISE_SET;
williamr@4: 		using namespace _OTHER_INT_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace OTHER_INT_EN_RISE_CLR
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::OTHER_INT_EN_RISE_CLR;
williamr@4: 		using namespace _OTHER_INT_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace OTHER_INT_STS
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::OTHER_INT_STS;
williamr@4: 		using namespace _OTHER_INT_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace _CARKIT_INT_
williamr@4: 		{
williamr@4: 		const TUint8 CARKIT_CARDP				= KBit2;
williamr@4: 		const TUint8 CARKIT_CARINTDET			= KBit1;
williamr@4: 		const TUint8 CARKIT_IDFLOAT				= KBit0;
williamr@4: 		}
williamr@4: 	
williamr@4: 	namespace CARKIT_INT_EN_SET
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::CARKIT_INT_EN_SET;
williamr@4: 		using namespace _CARKIT_INT_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace CARKIT_INT_EN_CLR
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::CARKIT_INT_EN_CLR;
williamr@4: 		using namespace _CARKIT_INT_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace CARKIT_INT_STS
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::CARKIT_INT_STS;
williamr@4: 		using namespace _CARKIT_INT_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace _ID_INT_
williamr@4: 		{
williamr@4: 		const TUint8 ID_INTID_RES_FLOAT 		= KBit3;
williamr@4: 		const TUint8 ID_INTID_RES_440K 		= KBit2;
williamr@4: 		const TUint8 ID_INTID_RES_200K 		= KBit1;
williamr@4: 		const TUint8 ID_INTID_RES_102K			= KBit0;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace ID_INT_EN_RISE_SET
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::ID_INT_EN_RISE_SET;
williamr@4: 		using namespace _ID_INT_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace ID_INT_EN_RISE_CLR
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::ID_INT_EN_RISE_CLR;
williamr@4: 		using namespace _ID_INT_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace ID_INT_STS
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::ID_INT_STS;
williamr@4: 		using namespace _ID_INT_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace _CARKIT_SM_1_INT_
williamr@4: 		{
williamr@4: 		const TUint8 CARKIT_SM_1_PSM_ERROR			= KBit6;
williamr@4: 		const TUint8 CARKIT_SM_1_PH_ACC 			= KBit5;
williamr@4: 		const TUint8 CARKIT_SM_1_CHARGER			= KBit4;
williamr@4: 		const TUint8 CARKIT_SM_1_USB_HOST			= KBit3;
williamr@4: 		const TUint8 CARKIT_SM_1_USB_OTG_B			= KBit2;
williamr@4: 		const TUint8 CARKIT_SM_1_CARKIT				= KBit1;
williamr@4: 		const TUint8 CARKIT_SM_1_DISCONNECTED		= KBit0;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace _CARKIT_SM_2_INT_
williamr@4: 		{
williamr@4: 		const TUint8 CARKIT_SM_2_STOP_PLS_MISS		= KBit7;
williamr@4: 		const TUint8 CARKIT_SM_2_STEREO_TO_MONO		= KBit3;
williamr@4: 		const TUint8 CARKIT_SM_2_PHONE_UART			= KBit1;
williamr@4: 		const TUint8 CARKIT_SM_2_PH_NO_ACK 			= KBit0;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace CARKIT_SM_1_INT_EN_SET
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::CARKIT_SM_1_INT_EN_SET;
williamr@4: 		using namespace _CARKIT_SM_1_INT_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace CARKIT_SM_1_INT_EN_CLR
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::CARKIT_SM_1_INT_EN_CLR;
williamr@4: 		using namespace _CARKIT_SM_1_INT_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace CARKIT_SM_1_INT_STS
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::CARKIT_SM_1_INT_STS;
williamr@4: 		using namespace _CARKIT_SM_1_INT_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace CARKIT_SM_2_INT_EN_SET
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::CARKIT_SM_2_INT_EN_SET;
williamr@4: 		using namespace _CARKIT_SM_2_INT_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace CARKIT_SM_2_INT_EN_CLR
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::CARKIT_SM_2_INT_EN_CLR;
williamr@4: 		using namespace _CARKIT_SM_2_INT_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace CARKIT_SM_2_INT_STS
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::CARKIT_SM_2_INT_STS;
williamr@4: 		using namespace _CARKIT_SM_2_INT_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace _PIH_
williamr@4: 		{
williamr@4: 		const TUint8 PIH_PWR_INT	= KBit5;
williamr@4: 		const TUint8 PIH_USB_INT	= KBit4;
williamr@4: 		const TUint8 PIH_MADC_INT	= KBit3;
williamr@4: 		const TUint8 PIH_BCI_INT	= KBit2;
williamr@4: 		const TUint8 PIH_KEYP_INT	= KBit1;
williamr@4: 		const TUint8 PIH_GPIO_INT	= KBit0;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace PIH_ISR_P1
williamr@4: 		{
williamr@4: 		const TUint Addr = Register::PIH_ISR_P1;
williamr@4: 		
williamr@4: 		const TUint8	PIH_ISR7	= KBit7;
williamr@4: 		const TUint8	PIH_ISR6	= KBit6;
williamr@4: 		const TUint8	PIH_ISR5	= KBit5;
williamr@4: 		const TUint8	PIH_ISR4	= KBit4;
williamr@4: 		const TUint8	PIH_ISR3	= KBit3;
williamr@4: 		const TUint8	PIH_ISR2	= KBit2;
williamr@4: 		const TUint8	PIH_ISR1	= KBit1;
williamr@4: 		const TUint8	PIH_ISR0	= KBit0;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace _SIH_CTRL_
williamr@4: 		{
williamr@4: 		const TUint8 SIH_EXCLEN		= KBit0;
williamr@4: 		const TUint8 SIH_PENDDIS	= KBit1;
williamr@4: 		const TUint8 SIH_COR		= KBit2;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace GPIO_SIH_CTRL
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::GPIO_SIH_CTRL;
williamr@4: 		using namespace _SIH_CTRL_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace KEYP_SIH_CTRL
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::KEYP_SIH_CTRL;
williamr@4: 		using namespace _SIH_CTRL_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace BCISIHCTRL
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::BCISIHCTRL;
williamr@4: 		using namespace _SIH_CTRL_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace MADC_SIH_CTRL
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::MADC_SIH_CTRL;
williamr@4: 		using namespace _SIH_CTRL_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace PWR_SIH_CTRL
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::PWR_SIH_CTRL;
williamr@4: 		using namespace _SIH_CTRL_;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace PROTECT_KEY
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::PROTECT_KEY;
williamr@4: 
williamr@4: 		const TUint8 KEY_TEST = KBit0;
williamr@4: 		const TUint8 KEY_CFG = KBit1;
williamr@4: 		}
williamr@4: 
williamr@4: 	namespace RTC_CTRL_REG
williamr@4: 		{
williamr@4: 		const TUint16 Addr = Register::RTC_CTRL_REG;
williamr@4: 
williamr@4: 		const TUint8 STOP_RTC = KBit0;
williamr@4: 		const TUint8 ROUND_30S = KBit1;
williamr@4: 		const TUint8 AUTO_COMP = KBit2;
williamr@4: 		const TUint8 MODE_12_24 = KBit3;
williamr@4: 		const TUint8 TEST_MODE = KBit4;
williamr@4: 		const TUint8 SET_32_COUNTER = KBit5;
williamr@4: 		const TUint8 GET_TIME = KBit6;
williamr@4: 		}
williamr@4: 
williamr@4: } // namespace TPS65950
williamr@4: 
williamr@4: #endif // define TPS65950_REGISTERS_H