williamr@4: // Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies). williamr@4: // All rights reserved. williamr@4: // This component and the accompanying materials are made available williamr@4: // under the terms of the License "Eclipse Public License v1.0" williamr@4: // which accompanies this distribution, and is available williamr@4: // at the URL "http://www.eclipse.org/legal/epl-v10.html". williamr@4: // williamr@4: // Initial Contributors: williamr@4: // Nokia Corporation - initial contribution. williamr@4: // williamr@4: // Contributors: williamr@4: // williamr@4: // Description: williamr@4: // williamr@4: williamr@4: #ifndef TPS65950_H williamr@4: #define TPS65950_H williamr@4: williamr@4: #include williamr@4: #include williamr@4: #include williamr@4: #include williamr@4: williamr@4: // Trace - 191 = 0x00000000 0x00000000 0x00000000 0x00000000 0x0000000 0x0000000 0x80000000 0x00000000 0x00000000 williamr@4: #define KTPS65950 191 williamr@4: williamr@4: williamr@4: williamr@4: namespace TPS65950 williamr@4: { williamr@4: williamr@4: /** Structure used for issuing an asynchronous request williamr@4: * You must set iDfc to point to a TDfc object which will williamr@4: * be queued on completion williamr@4: */ williamr@4: struct TReq williamr@4: { williamr@4: enum TAction williamr@4: { williamr@4: ERead, williamr@4: EWrite, williamr@4: EClearSet, williamr@4: EDisableProtect, williamr@4: ERestoreProtect williamr@4: }; williamr@4: williamr@4: williamr@4: TUint16 iRegister; ///< Register to be accessed williamr@4: TAction iAction : 8; ///< type of request, read, write or clearset williamr@4: TUint8 iReadValue; ///< Returned value from a read, original value for a ClearSet, unused for write williamr@4: union williamr@4: { williamr@4: TUint8 iWriteValue; ///< Value to write into register for a write williamr@4: TUint8 iSetMask; ///< Bits to set in a ClearSet williamr@4: }; williamr@4: TUint8 iClearMask; ///< Bits to clear in a ClearSet williamr@4: TDfc* iCompletionDfc; ///< Pointer to DFC to be called on completion (for multi-phase only the last TReq causes a completion) williamr@4: TInt iResult; ///< KErrNone on success, else error code williamr@4: TReq* iNextPhase; ///< set to NULL if this is a single request, for a multi-phase request set this to point to next TReq williamr@4: SDblQueLink iLink; ///< Used internally to maintain linked list of requests williamr@4: }; williamr@4: williamr@4: struct TRtcTime williamr@4: { williamr@4: TUint8 iSecond; williamr@4: TUint8 iMinute; williamr@4: TUint8 iHour; williamr@4: TUint8 iDay; williamr@4: TUint8 iMonth; williamr@4: TUint8 iYear; williamr@4: }; williamr@4: williamr@4: /** Test whether this driver has been initialized williamr@4: * Use this in code which is expected to run early during boot williamr@4: * to prevent it trying to access this driver before it is ready williamr@4: * williamr@4: * @return ETrue if initialized, EFalse if not williamr@4: */ williamr@4: IMPORT_C TBool Initialized(); williamr@4: williamr@4: /** Execute a request asynchronously williamr@4: * williamr@4: * @param aRequest Request object to executed, must stay valid until request completes williamr@4: */ williamr@4: IMPORT_C void ExecAsync( TReq& aRequest ); williamr@4: williamr@4: /** Execute a write synchronously williamr@4: * @param aRegister Register to write to - this must be one of the williamr@4: * register enumerations from tps65950_register.h williamr@4: * or the value of a register Addr property williamr@4: * williamr@4: * @param aValue Value to write to register williamr@4: * @return KErrNone on success, else standard error code williamr@4: */ williamr@4: IMPORT_C TInt WriteSync( TUint16 aRegister, TUint8 aValue ); williamr@4: williamr@4: /** Execute a read synchronously williamr@4: * @param aRegister Register to write to - this must be one of the williamr@4: * register enumerations from tps65950_register.h williamr@4: * or the value of a register Addr property williamr@4: * williamr@4: * @param aValue Value read will be written to here williamr@4: * @return KErrNone on success, else standard error code williamr@4: */ williamr@4: IMPORT_C TInt ReadSync( TUint16 aRegister, TUint8& aValue ); williamr@4: williamr@4: /** Execute a bit clear/set synchronously williamr@4: * @param aRegister Register to write to - this must be one of the williamr@4: * register enumerations from tps65950_register.h williamr@4: * or the value of a register Addr property williamr@4: * williamr@4: * @param aClearMask Each '1' clear the corresponding bit in the register williamr@4: * @param aSetMask Each '1' sets the corresponding bit in the register williamr@4: * @return KErrNone on success, else standard error code williamr@4: */ williamr@4: IMPORT_C TInt ClearSetSync( TUint16 aRegister, TUint8 aClearMask, TUint8 aSetMask ); williamr@4: williamr@4: /** Disable protection of voltage control registers williamr@4: * Call RestoreProtect() to re-enable protection williamr@4: * williamr@4: * Note - calls to DisableProtect and RestoreProtect() are williamr@4: * reference-counted, so you must call RestoreProtect() the same williamr@4: * number of times you called DisableProtect(). This is to allow williamr@4: * multiple clients to disable and restore protection so that williamr@4: * protection will only be re-enabled when the last client has williamr@4: * restored it. williamr@4: */ williamr@4: IMPORT_C TInt DisableProtect(); williamr@4: williamr@4: /** Restore protection after a DisableProtect(). williamr@4: * If other clients have called DisableProtect(), or this client williamr@4: * has other DisableProtect() calls still not balanced by a williamr@4: * RestoreProtect() then the protection will remain disabled williamr@4: */ williamr@4: IMPORT_C TInt RestoreProtect(); williamr@4: williamr@4: /** Read the current RTC time */ williamr@4: IMPORT_C TInt GetRtcData( TRtcTime& aTime ); williamr@4: williamr@4: /** Set the RTC time */ williamr@4: IMPORT_C TInt SetRtcData( const TRtcTime& aTime ); williamr@4: williamr@4: enum TPanic williamr@4: { williamr@4: EBadAction, ///< illegal value in TReq::iAction williamr@4: ENoDfc, ///< iCompletionDFC is NULL williamr@4: EBadGroup ///< Group component of iRegister is invalid williamr@4: }; williamr@4: williamr@4: williamr@4: enum TInterruptId williamr@4: { williamr@4: KTPS65950IrqFirst= (EIrqRangeBasePsu << KIrqRangeIndexShift), williamr@4: williamr@4: ETPS65950_IRQ_PWR_SC_DETECT = KTPS65950IrqFirst, williamr@4: ETPS65950_IRQ_PWR_MBCHG, williamr@4: ETPS65950_IRQ_PWR_PWROK_TIMEOUT, williamr@4: ETPS65950_IRQ_PWR_HOT_DIE, williamr@4: ETPS65950_IRQ_PWR_RTC_IT, williamr@4: ETPS65950_IRQ_PWR_USB_PRES, williamr@4: ETPS65950_IRQ_PWR_CHG_PRES, williamr@4: ETPS65950_IRQ_PWR_CHG_PWRONS, williamr@4: williamr@4: ETPS65950_IRQ_MADC_USB_ISR1, williamr@4: ETPS65950_IRQ_MADC_SW2_ISR1, williamr@4: ETPS65950_IRQ_MADC_SW1_ISR1, williamr@4: ETPS65950_IRQ_MADC_RT_ISR1, williamr@4: williamr@4: ETPS65950_IRQ_GPIO_0ISR1, williamr@4: ETPS65950_IRQ_GPIO_1ISR1, williamr@4: ETPS65950_IRQ_GPIO_2ISR1, williamr@4: ETPS65950_IRQ_GPIO_3ISR1, williamr@4: ETPS65950_IRQ_GPIO_4ISR1, williamr@4: ETPS65950_IRQ_GPIO_5ISR1, williamr@4: ETPS65950_IRQ_GPIO_6ISR1, williamr@4: ETPS65950_IRQ_GPIO_7ISR2, williamr@4: williamr@4: ETPS65950_IRQ_GPIO_8ISR2, williamr@4: ETPS65950_IRQ_GPIO_9ISR2, williamr@4: ETPS65950_IRQ_GPIO_10ISR2, williamr@4: ETPS65950_IRQ_GPIO_11ISR2, williamr@4: ETPS65950_IRQ_GPIO_12ISR2, williamr@4: ETPS65950_IRQ_GPIO_13ISR2, williamr@4: ETPS65950_IRQ_GPIO_14ISR2, williamr@4: ETPS65950_IRQ_GPIO_15ISR2, williamr@4: williamr@4: ETPS65950_IRQ_GPIO16ISR3, williamr@4: ETPS65950_IRQ_GPIO17ISR3, williamr@4: williamr@4: ETPS65950_IRQ_BCI_BATSTS_ISR1, williamr@4: ETPS65950_IRQ_BCI_TBATOR1_ISR1, williamr@4: ETPS65950_IRQ_BCI_TBATOR2_ISR1, williamr@4: ETPS65950_IRQ_BCI_ICHGEOC_ISR1, williamr@4: ETPS65950_IRQ_BCI_ICHGLOW_ISR1ASTO, williamr@4: ETPS65950_IRQ_BCI_IICHGHIGH_ISR1, williamr@4: ETPS65950_IRQ_BCI_TMOVF_ISR1, williamr@4: ETPS65950_IRQ_BCI_WOVF_ISR1, williamr@4: williamr@4: ETPS65950_IRQ_BCI_ACCHGOV_ISR1, williamr@4: ETPS65950_IRQ_BCI_VBUSOV_ISR1, williamr@4: ETPS65950_IRQ_BCI_VBATOV_ISR1, williamr@4: ETPS65950_IRQ_BCI_VBATLVL_ISR1, williamr@4: williamr@4: ETPS65950_IRQ_KEYP_ITMISR1, williamr@4: ETPS65950_IRQ_KEYP_ITTOISR1, williamr@4: ETPS65950_IRQ_KEYP_ITLKISR1, williamr@4: ETPS65950_IRQ_KEYP_ITKPISR1, williamr@4: williamr@4: ETPS65950_IRQ_USB_INTSTS_IDGND, williamr@4: ETPS65950_IRQ_USB_INTSTS_SESSEND, williamr@4: ETPS65950_IRQ_USB_INTSTS_SESSVALID, williamr@4: ETPS65950_IRQ_USB_INTSTS_VBUSVALID, williamr@4: ETPS65950_IRQ_USB_INTSTS_HOSTDISCONNECT, williamr@4: ETPS65950_IRQ_USB_CARKIT_CARDP, williamr@4: ETPS65950_IRQ_USB_CARKIT_CARINTDET, williamr@4: ETPS65950_IRQ_USB_CARKIT_IDFLOAT, williamr@4: ETPS65950_IRQ_USB_OTHER_INT_VB_SESS_VLD, williamr@4: ETPS65950_IRQ_USB_OTHER_INT_DM_HI, williamr@4: ETPS65950_IRQ_USB_OTHER_INT_DP_HI, williamr@4: ETPS65950_IRQ_USB_OTHER_INT_MANU, williamr@4: ETPS65950_IRQ_USB_OTHER_INT_ABNORMAL_STRESS, williamr@4: ETPS65950_IRQ_USB_ID_INT_ID_RES_FLOAT, williamr@4: ETPS65950_IRQ_USB_ID_INT_ID_RES_440K, williamr@4: ETPS65950_IRQ_USB_ID_INT_ID_RES_200K, williamr@4: ETPS65950_IRQ_USB_ID_INT_ID_RES_102K, williamr@4: ETPS65950_IRQ_USB_CARKIT_SM_1_PSM_ERROR, williamr@4: ETPS65950_IRQ_USB_CARKIT_SM_1_PH_ACC, williamr@4: ETPS65950_IRQ_USB_CARKIT_SM_1_CHARGER, williamr@4: ETPS65950_IRQ_USB_CARKIT_SM_1_USB_HOST, williamr@4: ETPS65950_IRQ_USB_CARKIT_SM_1_USB_OTG_B, williamr@4: ETPS65950_IRQ_USB_CARKIT_SM_1_CARKIT, williamr@4: ETPS65950_IRQ_USB_CARKIT_SM_1_DISCONNECTED, williamr@4: ETPS65950_IRQ_USB_CARKIT_SM_2_STOP_PLS_MISS, williamr@4: ETPS65950_IRQ_USB_CARKIT_SM_2_STEREO_TO_MONO, williamr@4: ETPS65950_IRQ_USB_CARKIT_SM_2_PHONE_UART, williamr@4: ETPS65950_IRQ_USB_CARKIT_SM_2_PH_NO_ACK, williamr@4: williamr@4: KTPS65950IrqLast, williamr@4: }; williamr@4: williamr@4: const TInt KNumTPSInts = (KTPS65950IrqLast - KTPS65950IrqFirst); williamr@4: williamr@4: } // namespace TPS65950 williamr@4: williamr@4: williamr@4: #endif //tps65950