williamr@4: // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
williamr@4: // All rights reserved.
williamr@4: // This component and the accompanying materials are made available
williamr@4: // under the terms of the License "Eclipse Public License v1.0"
williamr@4: // which accompanies this distribution, and is available
williamr@4: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
williamr@4: //
williamr@4: // Initial Contributors:
williamr@4: // Nokia Corporation - initial contribution.
williamr@4: //
williamr@4: // Contributors:
williamr@4: //
williamr@4: // Description:
williamr@4: // omap3530/omap3530_drivers/uart/omap3530_uart.h
williamr@4: // This file is part of the Beagle Base port
williamr@4: //
williamr@4: 
williamr@4: #ifndef __OMAP3530_UART_H__
williamr@4: #define __OMAP3530_UART_H__
williamr@4: 
williamr@4: #include <assp/omap3530_assp/omap3530_hardware_base.h>
williamr@4: #include <assp/omap3530_assp/omap3530_prcm.h>
williamr@4: //#include "assp/omap3530_assp/omap3530_prm.h"
williamr@4: #include <assp/omap3530_assp/omap3530_irqmap.h>
williamr@4: 
williamr@4: //#include "omap3530_prm.h"
williamr@4: 
williamr@4: 
williamr@4: namespace Omap3530Uart
williamr@4: {
williamr@4: using namespace TexasInstruments::Omap3530;
williamr@4: 
williamr@4: enum TUartNumber
williamr@4: 	{
williamr@4: 	EUartNone = -1,
williamr@4: 	EUart0 = 0,
williamr@4: 	EUart1,
williamr@4: 	EUart2
williamr@4: 	};
williamr@4: 
williamr@4: template< const TUartNumber aUartNumber >
williamr@4: struct TUartTraits
williamr@4: 	{
williamr@4: 	};
williamr@4: 
williamr@4: template<>
williamr@4: struct TUartTraits< EUart0 >
williamr@4: 	{
williamr@4: 	static const TUint32 KBaseAddress = Omap3530HwBase::KL4_Core + 0x0006A000;
williamr@4: 	static const TInt KInterruptId = EOmap3530_IRQ72_UART1_IRQ;
williamr@4: 	static const Prcm::TClock	KInterfaceClock = Prcm::EClkUart1_I;
williamr@4: 	static const Prcm::TClock	KFunctionClock = Prcm::EClkUart1_F;
williamr@4: //	static const Omap3530Prm::TPrmId	KPrmInterfaceClock = Omap3530Prm::EPrmClkUart1_I;
williamr@4: //	static const Omap3530Prm::TPrmId	KPrmFunctionClock = Omap3530Prm::EPrmClkUart1_F;
williamr@4: 	};
williamr@4: 
williamr@4: template<>
williamr@4: struct TUartTraits< EUart1 >
williamr@4: 	{
williamr@4: 	static const TUint32 KBaseAddress = Omap3530HwBase::KL4_Core + 0x0006C000;
williamr@4: 	static const TInt KInterruptId = EOmap3530_IRQ73_UART2_IRQ;
williamr@4: 	static const Prcm::TClock	KInterfaceClock = Prcm::EClkUart2_I;
williamr@4: 	static const Prcm::TClock	KFunctionClock = Prcm::EClkUart2_F;
williamr@4: //	static const Omap3530Prm::TPrmId	KPrmInterfaceClock = Omap3530Prm::EPrmClkUart2_I;
williamr@4: //	static const Omap3530Prm::TPrmId	KPrmFunctionClock = Omap3530Prm::EPrmClkUart2_F;
williamr@4: 	};
williamr@4: 
williamr@4: template<>
williamr@4: struct TUartTraits< EUart2 >
williamr@4: 	{
williamr@4: 	static const TUint32 KBaseAddress = Omap3530HwBase::KL4_Per + 0x00020000;
williamr@4: 	static const TInt KInterruptId = EOmap3530_IRQ74_UART3_IRQ;
williamr@4: 	static const Prcm::TClock	KInterfaceClock = Prcm::EClkUart3_I;
williamr@4: 	static const Prcm::TClock	KFunctionClock = Prcm::EClkUart3_F;
williamr@4: //	static const Omap3530Prm::TPrmId	KPrmInterfaceClock = Omap3530Prm::EPrmClkUart3_I;
williamr@4: //	static const Omap3530Prm::TPrmId	KPrmFunctionClock = Omap3530Prm::EPrmClkUart3_F;
williamr@4: 	};
williamr@4: 
williamr@4: // Forward declaration
williamr@4: class TUart;
williamr@4: 
williamr@4: 
williamr@4: /** Representation of general UART register set */
williamr@4: struct DLL
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x00;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<0,8>	CLOCK_LSB;
williamr@4: 	};
williamr@4: 
williamr@4: struct RHR
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x00;
williamr@4: 	static TDynReg8_R< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<0,8>	Value;
williamr@4: 	};
williamr@4: 
williamr@4: struct THR
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x00;
williamr@4: 	static TDynReg8_W< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<0,8>	Value;
williamr@4: 	};
williamr@4: 
williamr@4: struct IER
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x04;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TSingleBitField<7>	CTS_IT;
williamr@4: 	typedef TSingleBitField<6>	RTS_IT;
williamr@4: 	typedef TSingleBitField<5>	XOFF_IT;
williamr@4: 	typedef TSingleBitField<4>	SLEEP_MODE;
williamr@4: 	typedef TSingleBitField<3>	MODEM_STS_IT;
williamr@4: 	typedef TSingleBitField<2>	LINE_STS_IT;
williamr@4: 	typedef TSingleBitField<1>	THR_IT;
williamr@4: 	typedef TSingleBitField<0>	RHR_IT;
williamr@4: 	};
williamr@4: 
williamr@4: struct IER_IRDA
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x04;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TSingleBitField<7>	EOF_IT;
williamr@4: 	typedef TSingleBitField<6>	LINE_STS_IT;
williamr@4: 	typedef TSingleBitField<5>	TX_STATUS_IT;
williamr@4: 	typedef TSingleBitField<4>	STS_FIFO_TRIG_IT;
williamr@4: 	typedef TSingleBitField<3>	RX_OVERRUN_IT;
williamr@4: 	typedef TSingleBitField<2>	LAST_RX_BYTE_IT;
williamr@4: 	typedef TSingleBitField<1>	THR_IT;
williamr@4: 	typedef TSingleBitField<0>	RHR_IT;
williamr@4: 	};
williamr@4: 
williamr@4: struct DLH
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x04;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<0,6>	CLOCK_MSB;
williamr@4: 	};
williamr@4: 
williamr@4: struct FCR
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x08;
williamr@4: 	static TDynReg8_W< TUart, KOffset >	iMem;
williamr@4: 	typedef TSingleBitField<0>	FIFO_EN;
williamr@4: 	typedef TSingleBitField<1>	RX_FIFO_CLEAR;
williamr@4: 	typedef	TSingleBitField<2>	TX_FIFO_CLEAR;
williamr@4: 	typedef TSingleBitField<3>	DMA_MODE;
williamr@4: 	struct TX_FIFO_TRIG : public TBitField<4,2>
williamr@4: 		{
williamr@4: 		enum TConstants
williamr@4: 			{
williamr@4: 			K8Char	= 0 << KShift,
williamr@4: 			K16Char	= 1 << KShift,
williamr@4: 			K32Char	= 2 << KShift,
williamr@4: 			K56Char	= 3 << KShift
williamr@4: 			};
williamr@4: 		};
williamr@4: 	struct RX_FIFO_TRIG : public TBitField<6,2>
williamr@4: 		{
williamr@4: 		static const TUint8	K8Char	= 0 << KShift;
williamr@4: 		static const TUint8	K16Char	= 1 << KShift;
williamr@4: 		static const TUint8	K56Char	= 2 << KShift;
williamr@4: 		static const TUint8	K60Char	= 3 << KShift;
williamr@4: 		};
williamr@4: 	};
williamr@4: 
williamr@4: struct IIR
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x08;
williamr@4: 	static TDynReg8_R< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<6,2>	FCR_MIRROR;
williamr@4: 	struct IT_TYPE : public TBitField<1,5>
williamr@4: 		{
williamr@4: 		enum TConstants
williamr@4: 			{
williamr@4: 			EModem	= 0 << KShift,
williamr@4: 			ETHR	= 1 << KShift,
williamr@4: 			ERHR	= 2 << KShift,
williamr@4: 			ERxLineStatus	= 3 << KShift,
williamr@4: 			ERxTimeout		= 6 << KShift,
williamr@4: 			EXoff			= 8 << KShift,
williamr@4: 			ECtsRts			= 16  << KShift
williamr@4: 			};
williamr@4: 		};
williamr@4: 	typedef TSingleBitField<0>	IT_PENDING;
williamr@4: 	};
williamr@4: 
williamr@4: struct EFR
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x08;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TSingleBitField<7>	AUTO_CTS_EN;
williamr@4: 	typedef TSingleBitField<6>	AUTO_RTS_EN;
williamr@4: 	typedef TSingleBitField<5>	SPEC_CHAR;
williamr@4: 	typedef TSingleBitField<4>	ENHANCED_EN;
williamr@4: 	struct SW_FLOW_CONTROL : public TBitField<0,4>
williamr@4: 		{
williamr@4: 		enum TFlowControl
williamr@4: 			{
williamr@4: 			ENone		= 0,
williamr@4: 			EXonXoff1	= 8,
williamr@4: 			EXonXoff2	= 4,
williamr@4: 			EXonXoffBoth = 8 + 4,
williamr@4: 			};
williamr@4: 		};
williamr@4: 	};
williamr@4: 
williamr@4: struct LCR
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x0c;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TSingleBitField<7>	DIV_EN;
williamr@4: 	typedef TSingleBitField<6>	BREAK_EN;
williamr@4: 	typedef TSingleBitField<5>	PARITY_TYPE2;
williamr@4: 	typedef TSingleBitField<4>	PARITY_TYPE1;
williamr@4: 	typedef TSingleBitField<3>	PARITY_EN;
williamr@4: 	struct NB_STOP : public TSingleBitField<2>
williamr@4: 		{
williamr@4: 		enum TConstants
williamr@4: 			{
williamr@4: 			E1Stop		= 0 << KShift,
williamr@4: 			E1_5Stop	= 1 << KShift,
williamr@4: 			E2Stop		= 1 << KShift
williamr@4: 			};
williamr@4: 		};
williamr@4: 	struct CHAR_LENGTH : public TBitField<0,2>
williamr@4: 		{
williamr@4: 		enum TConstants
williamr@4: 			{
williamr@4: 			E5Bits		= 0,
williamr@4: 			E6Bits		= 1,
williamr@4: 			E7Bits		= 2,
williamr@4: 			E8Bits		= 3
williamr@4: 			};
williamr@4: 		};
williamr@4: 
williamr@4: 	/** Special magic number to enter MODEA */
williamr@4: 	static const TUint8 KConfigModeA = 0x80;
williamr@4: 
williamr@4: 	/** Special magic number to enter MODEB */
williamr@4: 	static const TUint8 KConfigModeB = 0xBF;
williamr@4: 
williamr@4: 	/** Special magic number to enter operational mode */
williamr@4: 	static const TUint8 KConfigModeOperational = 0x00;
williamr@4: 	};
williamr@4: 
williamr@4: struct MCR
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x10;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TSingleBitField<6>	TCR_TLR;
williamr@4: 	typedef TSingleBitField<5>	XON_EN;
williamr@4: 	typedef TSingleBitField<4>	LOOPBACK_EN;
williamr@4: 	typedef TSingleBitField<3>	CD_STS_CH;
williamr@4: 	typedef TSingleBitField<2>	RI_STS_CH;
williamr@4: 	typedef TSingleBitField<1>	RTS;
williamr@4: 	typedef TSingleBitField<0>	DTR;
williamr@4: 	};
williamr@4: 
williamr@4: struct XON1_ADDR1
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x10;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<0,8>	Value;
williamr@4: 	};
williamr@4: 
williamr@4: struct LSR
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x14;
williamr@4: 	static TDynReg8_R< TUart, KOffset >	iMem;
williamr@4: 	typedef TSingleBitField<7>	RX_FIFO_STS;
williamr@4: 	typedef TSingleBitField<6>	TX_SR_E;
williamr@4: 	typedef TSingleBitField<5>	TX_FIFO_E;
williamr@4: 	typedef TSingleBitField<4>	RX_BI;
williamr@4: 	typedef TSingleBitField<3>	RX_FE;
williamr@4: 	typedef TSingleBitField<2>	RX_PE;
williamr@4: 	typedef TSingleBitField<1>	RX_OE;
williamr@4: 	typedef TSingleBitField<0>	RX_FIFO_E;
williamr@4: 	};
williamr@4: 
williamr@4: struct XON2_ADDR2
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x14;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<0,8>	Value;
williamr@4: 	};
williamr@4: 
williamr@4: struct XOFF1
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x18;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<0,8>	Value;
williamr@4: 	};
williamr@4: 
williamr@4: struct TCR
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x18;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<4,4>	RX_FIFO_TRIG_START;
williamr@4: 	typedef TBitField<0,4>	RX_FIFO_TRIG_HALT;
williamr@4: 	};
williamr@4: 
williamr@4: struct MSR
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x18;
williamr@4: 	static TDynReg8_R< TUart, KOffset >	iMem;
williamr@4: 	typedef TSingleBitField<7>	NCD_STS;
williamr@4: 	typedef TSingleBitField<6>	NRI_STS;
williamr@4: 	typedef TSingleBitField<5>	NDSR_STS;
williamr@4: 	typedef TSingleBitField<4>	NCTS_STS;
williamr@4: 	typedef TSingleBitField<3>	DCD_STS;
williamr@4: 	typedef TSingleBitField<2>	RI_STS;
williamr@4: 	typedef TSingleBitField<1>	DSR_STS;
williamr@4: 	typedef TSingleBitField<0>	CTS_STS;
williamr@4: 	};
williamr@4: 
williamr@4: struct SPR
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x1c;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<0,8>	SPR_WORD;
williamr@4: 	};
williamr@4: 
williamr@4: struct XOFF2
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x1c;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<0,8>	Value;
williamr@4: 	};
williamr@4: 
williamr@4: struct TLR
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x1c;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<4,4>	RX_FIFO_TRIG_DMA;
williamr@4: 	typedef TBitField<0,4>	TX_FIFO_TRIG_DMA;
williamr@4: 	};
williamr@4: 
williamr@4: struct MDR1
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x20;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TSingleBitField<7>	FRAME_END_MODE;
williamr@4: 	typedef TSingleBitField<6>	SIP_MODE;
williamr@4: 	typedef TSingleBitField<5>	SCT;
williamr@4: 	typedef TSingleBitField<4>	SET_TXIR;
williamr@4: 	typedef TSingleBitField<3>	IR_SLEEP;
williamr@4: 	struct MODE_SELECT : public TBitField<0,3>
williamr@4: 		{
williamr@4: 		enum TMode
williamr@4: 			{
williamr@4: 			EUart16x		= 0,
williamr@4: 			ESIR			= 1,
williamr@4: 			EUart16xAutoBaud = 2,
williamr@4: 			EUart13x		= 3,
williamr@4: 			EMIR			= 4,
williamr@4: 			EFIR			= 5,
williamr@4: 			ECIR			= 6,
williamr@4: 			EDisable		= 7
williamr@4: 			};
williamr@4: 		};
williamr@4: 	};
williamr@4: 
williamr@4: struct MDR2
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x24;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TSingleBitField<6>	IRRXINVERT;
williamr@4: 	struct CIR_PULSE_MODE : public TBitField<4,2>
williamr@4: 		{
williamr@4: 		enum TConstants
williamr@4: 			{
williamr@4: 			EPw3	= 0 << KShift,
williamr@4: 			EPw4	= 1 << KShift,
williamr@4: 			EPw5	= 2 << KShift,
williamr@4: 			EPw6	= 3 << KShift
williamr@4: 			};
williamr@4: 		};
williamr@4: 	typedef TSingleBitField<3>	UART_PULSE;
williamr@4: 	struct STS_FIFO_TRIG : public TBitField<1,2>
williamr@4: 		{
williamr@4: 		enum TConstants
williamr@4: 			{
williamr@4: 			E1Entry		= 0 << KShift,
williamr@4: 			E4Entry		= 1 << KShift,
williamr@4: 			E7Entry		= 2 << KShift,
williamr@4: 			E8Entry		= 3 << KShift
williamr@4: 			};
williamr@4: 		};
williamr@4: 	typedef TSingleBitField<0>	IRTX_UNDERRUN;
williamr@4: 	};
williamr@4: 
williamr@4: struct TXFLL
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x28;
williamr@4: 	static TDynReg8_W< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<0,8>	TX_FLL;
williamr@4: 	};
williamr@4: 
williamr@4: struct SFLSR
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x28;
williamr@4: 	static TDynReg8_R< TUart, KOffset >	iMem;
williamr@4: 	typedef TSingleBitField<4>	OE_ERROR;
williamr@4: 	typedef TSingleBitField<3>	FTL_ERROR;
williamr@4: 	typedef TSingleBitField<2>	ABORT_DETECT;
williamr@4: 	typedef TSingleBitField<1>	CRC_ERROR;
williamr@4: 	};
williamr@4: 
williamr@4: struct RESUME
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x2c;
williamr@4: 	static TDynReg8_R< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<0,8>	Value;
williamr@4: 	};
williamr@4: 
williamr@4: struct TXFLH
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x2c;
williamr@4: 	static TDynReg8_W< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<0,5>	TX_FLH;
williamr@4: 	};
williamr@4: 
williamr@4: struct RXFLL
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x30;
williamr@4: 	static TDynReg8_W< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<0,8>	RX_FLL;
williamr@4: 	};
williamr@4: 
williamr@4: struct SFREGL
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x30;
williamr@4: 	static TDynReg8_R< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<0,8>	Value;
williamr@4: 	};
williamr@4: 
williamr@4: struct SFREGH
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x34;
williamr@4: 	static TDynReg8_R< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<0,4>	Value;
williamr@4: 	};
williamr@4: 
williamr@4: struct RXFLH
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x34;
williamr@4: 	static TDynReg8_W< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<0,4>	RX_FLH;
williamr@4: 	};
williamr@4: 
williamr@4: struct BLR
williamr@4: 	{
williamr@4: 	typedef TSingleBitField<7>	STS_FIFO_RESET;
williamr@4: 	typedef TSingleBitField<6>	XBOF_TYPE;
williamr@4: 	};
williamr@4: 
williamr@4: struct UASR
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x38;
williamr@4: 	static TDynReg8_R< TUart, KOffset >	iMem;
williamr@4: 	struct PARITY_TYPE : public TBitField<6,2>
williamr@4: 		{
williamr@4: 		enum TConstants
williamr@4: 			{
williamr@4: 			ENone	= 0 << KShift,
williamr@4: 			ESpace	= 1 << KShift,
williamr@4: 			EEven	= 2 << KShift,
williamr@4: 			EOdd	= 3 << KShift
williamr@4: 			};
williamr@4: 		};
williamr@4: 	struct BIT_BY_CHAR : public TSingleBitField<5>
williamr@4: 		{
williamr@4: 		enum TConstants
williamr@4: 			{
williamr@4: 			E7Bit	= 0 << KShift,
williamr@4: 			E8Bit	= 1 << KShift
williamr@4: 			};
williamr@4: 		};
williamr@4: 	struct SPEED : public TBitField<0,5>
williamr@4: 		{
williamr@4: 		enum TBaud
williamr@4: 			{
williamr@4: 			EUnknown	= 0,
williamr@4: 			E115200		= 1,
williamr@4: 			E57600		= 2,
williamr@4: 			E38400		= 3,
williamr@4: 			E28800		= 4,
williamr@4: 			E19200		= 5,
williamr@4: 			E14400		= 6,
williamr@4: 			E9600		= 7,
williamr@4: 			E4800		= 8,
williamr@4: 			E4800_2		= 9,
williamr@4: 			E1200		= 10
williamr@4: 			};
williamr@4: 		};
williamr@4: 	};
williamr@4: 
williamr@4: struct ACREG
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x3c;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TSingleBitField<7>	PULSE_TYPE;
williamr@4: 	typedef TSingleBitField<6>	SID_MOD;
williamr@4: 	typedef TSingleBitField<5>	DIS_IR_RX;
williamr@4: 	typedef TSingleBitField<4>	DIS_TX_UNDERRUN;
williamr@4: 	typedef TSingleBitField<3>	SEND_SIP;
williamr@4: 	typedef TSingleBitField<2>	SCTX_EN;
williamr@4: 	typedef TSingleBitField<1>	ABORT_EN;
williamr@4: 	typedef TSingleBitField<0>	EOT_EN;
williamr@4: 	};
williamr@4: 
williamr@4: struct SCR
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x40;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TSingleBitField<7>	RX_TRIG_GRANU1;
williamr@4: 	typedef TSingleBitField<6>	TX_TRIG_GRANU1;
williamr@4: 	typedef TSingleBitField<4>	RX_CTS_WU_EN;
williamr@4: 	typedef TSingleBitField<3>	TX_EMPTY_CTL_IT;
williamr@4: 	typedef TBitField<1,2>		DMA_MODE2;
williamr@4: 	typedef TSingleBitField<0>	DMA_MODE_CTL;
williamr@4: 	};
williamr@4: 
williamr@4: struct SSR
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x44;
williamr@4: 	static TDynReg8_R< TUart, KOffset >	iMem;
williamr@4: 	typedef TSingleBitField<1>	RX_CTS_WU_STS;
williamr@4: 	typedef TSingleBitField<0>	TX_FIFO_FULL;
williamr@4: 	};
williamr@4: 
williamr@4: struct EBLR
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x48;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<0,8>	Value;
williamr@4: 	};
williamr@4: 
williamr@4: struct SYSC
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x54;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	struct IDLE_MODE : public TBitField<3,2>
williamr@4: 		{
williamr@4: 		enum TMode
williamr@4: 			{
williamr@4: 			EForceIdle	= 0 << KShift,
williamr@4: 			ENoIdle		= 1 << KShift,
williamr@4: 			ESmartIdle	= 2 << KShift
williamr@4: 			};
williamr@4: 		};
williamr@4: 	typedef TSingleBitField<2>	ENAWAKEUP;
williamr@4: 	typedef TSingleBitField<1>	SOFTRESET;
williamr@4: 	typedef TSingleBitField<0>	AUTOIDLE;
williamr@4: 	};
williamr@4: 
williamr@4: struct SYSS
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x58;
williamr@4: 	static TDynReg8_R< TUart, KOffset >	iMem;
williamr@4: 	typedef TSingleBitField<0>	RESETDONE;
williamr@4: 	};
williamr@4: 
williamr@4: struct WER
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x5c;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TSingleBitField<6>	EVENT_6_RLS_INTERRUPT;
williamr@4: 	typedef TSingleBitField<5>	EVENT_5_RHR_INTERRUPT;
williamr@4: 	typedef TSingleBitField<4>	EVENT_4_RX_ACTIVITY;
williamr@4: 	typedef TSingleBitField<2>	EVENT_2_RI_ACTIVITY;
williamr@4: 	typedef TSingleBitField<0>	EVENT_0_CTS_ACTIVITY;
williamr@4: 	};
williamr@4: 
williamr@4: struct CFPS
williamr@4: 	{
williamr@4: 	static const TInt KOffset	= 0x60;
williamr@4: 	static TDynReg8_RW< TUart, KOffset >	iMem;
williamr@4: 	typedef TBitField<0,8>	Value;
williamr@4: 	};
williamr@4: 
williamr@4: 
williamr@4: class TUart
williamr@4: 	{
williamr@4: 	public:
williamr@4: 		enum TBaud
williamr@4: 			{
williamr@4: 			E1200,
williamr@4: 			E2400,
williamr@4: 			E4800,
williamr@4: 			E9600,
williamr@4: 			E14400,
williamr@4: 			E19200,
williamr@4: 			E28800,
williamr@4: 			E38400,
williamr@4: 			E57600,
williamr@4: 			E115200,
williamr@4: 			E230400,
williamr@4: 			E460800,
williamr@4: 			E921600,
williamr@4: 			E1843000,
williamr@4: 			E3688400,
williamr@4: 			E4000000,		// FIR
williamr@4: 
williamr@4: 			KSupportedBaudCount
williamr@4: 			};
williamr@4: 
williamr@4: 		enum TParity
williamr@4: 			{
williamr@4: 			ENone,
williamr@4: 			EOdd,
williamr@4: 			EEven,
williamr@4: 			EMark,
williamr@4: 			ESpace
williamr@4: 			};
williamr@4: 
williamr@4: 		enum TDataBits
williamr@4: 			{
williamr@4: 			E5Data = ::Omap3530Uart::LCR::CHAR_LENGTH::E5Bits,
williamr@4: 			E6Data = ::Omap3530Uart::LCR::CHAR_LENGTH::E6Bits,
williamr@4: 			E7Data = ::Omap3530Uart::LCR::CHAR_LENGTH::E7Bits,
williamr@4: 			E8Data = ::Omap3530Uart::LCR::CHAR_LENGTH::E8Bits,
williamr@4: 			};
williamr@4: 
williamr@4: 		enum TStopBits
williamr@4: 			{
williamr@4: 			E1Stop = ::Omap3530Uart::LCR::NB_STOP::E1Stop,
williamr@4: 			E1_5Stop = ::Omap3530Uart::LCR::NB_STOP::E1_5Stop,
williamr@4: 			E2Stop = ::Omap3530Uart::LCR::NB_STOP::E2Stop,
williamr@4: 			};
williamr@4: 
williamr@4: 		enum TUartMode
williamr@4: 			{
williamr@4: 			EUart,
williamr@4: 			EUartAutoBaud,
williamr@4: 			ESIR,
williamr@4: 			EMIR,
williamr@4: 			EFIR,
williamr@4: 			ECIR,
williamr@4: 
williamr@4: 			KSupportedUartModes
williamr@4: 			};
williamr@4: 
williamr@4: 		enum TFifoTrigger
williamr@4: 			{
williamr@4: 			ETrigger8,
williamr@4: 			ETrigger16,
williamr@4: 			ETrigger32,
williamr@4: 			ETrigger56,
williamr@4: 			ETrigger60,
williamr@4: 			ETriggerUnchanged
williamr@4: 			};
williamr@4: 
williamr@4: 		enum TEnableState
williamr@4: 			{
williamr@4: 			EDisabled,
williamr@4: 			EEnabled
williamr@4: 			};
williamr@4: 
williamr@4: 		enum TInterrupt
williamr@4: 			{
williamr@4: 			EIntRhr = 0,
williamr@4: 			EIntThr = 1,
williamr@4: 			EIntLineStatus = 2,
williamr@4: 			EIntModemStatus = 3,
williamr@4: 			EIntXoff = 5,
williamr@4: 			EIntRts = 6,
williamr@4: 			EIntCts = 7
williamr@4: 			};
williamr@4: 
williamr@4: 	public:
williamr@4: 		inline TUart( const TUartNumber aUartNumber )
williamr@4: 			: iBase(	(aUartNumber == EUart0 )	?	TUartTraits<EUart0>::KBaseAddress
williamr@4: 							:	(aUartNumber == EUart1 )	?	TUartTraits<EUart1>::KBaseAddress
williamr@4: 							:	(aUartNumber == EUart2 )	?	TUartTraits<EUart2>::KBaseAddress
williamr@4: 							:	0 ),
williamr@4: 				iUartNumber( aUartNumber )
williamr@4: 			{}
williamr@4: 
williamr@4: 		FORCE_INLINE TLinAddr Base() const
williamr@4: 			{ return iBase; }
williamr@4: 
williamr@4: 		IMPORT_C TInt InterruptId() const;
williamr@4: 
williamr@4: 		IMPORT_C Prcm::TClock PrcmInterfaceClk() const;
williamr@4: 		
williamr@4: 		IMPORT_C Prcm::TClock PrcmFunctionClk() const;
williamr@4: 
williamr@4: //		IMPORT_C TInt PrmInterfaceClk() const;
williamr@4: 		
williamr@4: //		IMPORT_C TInt PrmFunctionClk() const;
williamr@4: 
williamr@4: 		/** Reset and initialize the UART 
williamr@4: 		 * On return the UART will be in disable mode */
williamr@4: 		IMPORT_C void Init();
williamr@4: 
williamr@4: 		/** Defines which mode the UART will run in when enabled, but does not configure that mode
williamr@4: 		 * You must call this before calling SetBaud to ensure that correct baud rate multiplier is used */
williamr@4: 		IMPORT_C void DefineMode( const TUartMode aMode );
williamr@4: 
williamr@4: 		/** Enabled the UART in the defined mode
williamr@4: 		 * You must call DefineMode() and SetBaud() before calling Enable()
williamr@4: 		 */
williamr@4: 		IMPORT_C void Enable();
williamr@4: 
williamr@4: 		/** Disables the UART */
williamr@4: 		IMPORT_C void Disable();
williamr@4: 
williamr@4: 		/** Set the baud rate 
williamr@4: 		 * Do not call this while the UART is enabled
williamr@4: 		 * You must have previously called DefineMode()
williamr@4: 		 */
williamr@4: 		IMPORT_C void SetBaud( const TBaud aBaud );
williamr@4: 
williamr@4: 		/** Set the data length, parity and stop bits */
williamr@4: 		IMPORT_C void SetDataFormat( const TDataBits aDataBits, const TStopBits aStopBits, const TParity aParity );
williamr@4: 
williamr@4: 		/** Setup the FIFO configuration */
williamr@4: 		IMPORT_C void EnableFifo( const TEnableState aState, const TFifoTrigger aRxTrigger = ETriggerUnchanged, const TFifoTrigger aTxTrigger = ETriggerUnchanged );
williamr@4: 
williamr@4: 		/** Enable a particular interrupt source */
williamr@4: 		IMPORT_C void EnableInterrupt( const TInterrupt aWhich );
williamr@4: 
williamr@4: 		/** Disable a particular interrupt source */
williamr@4: 		IMPORT_C void DisableInterrupt( const TInterrupt aWhich );
williamr@4: 
williamr@4: 		/** Disable all interrupts */
williamr@4: 		IMPORT_C void DisableAllInterrupts();
williamr@4: 
williamr@4: 		inline TBool TxFifoFull()
williamr@4: 			{ return SSR::iMem.Read(*this) bitand SSR::TX_FIFO_FULL::KMask; }
williamr@4: 
williamr@4: 		inline TBool TxFifoEmpty()
williamr@4: 			{ return LSR::iMem.Read(*this) bitand LSR::TX_FIFO_E::KMask; }
williamr@4: 
williamr@4: 		inline TBool RxFifoEmpty()
williamr@4: 			{ return !(LSR::iMem.Read(*this) bitand LSR::RX_FIFO_E::KMask); }
williamr@4: 
williamr@4: 		inline void Write( TUint8 aByte )
williamr@4: 			{ THR::iMem.Write( *this, aByte ); }
williamr@4: 
williamr@4: 		inline TUint8 Read()
williamr@4: 			{ return RHR::iMem.Read( *this ); }
williamr@4: 
williamr@4: 	private:
williamr@4: 		TUart();
williamr@4: 
williamr@4: 	public:
williamr@4: 		const TLinAddr	iBase;
williamr@4: 		const TUartNumber	iUartNumber : 8;
williamr@4: 		TUartMode		iMode : 8;
williamr@4: 		::Omap3530Uart::MDR1::MODE_SELECT::TMode	iTargetMode : 8;
williamr@4: 	};
williamr@4: 
williamr@4: 
williamr@4: } // Omap3530Uart
williamr@4: 
williamr@4: #endif // ndef __OMAP3530_UART_H__
williamr@4: