williamr@4: // Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies).
williamr@4: // All rights reserved.
williamr@4: // This component and the accompanying materials are made available
williamr@4: // under the terms of the License "Eclipse Public License v1.0"
williamr@4: // which accompanies this distribution, and is available
williamr@4: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
williamr@4: //
williamr@4: // Initial Contributors:
williamr@4: // Nokia Corporation - initial contribution.
williamr@4: //
williamr@4: // Contributors:
williamr@4: //
williamr@4: // Description:
williamr@4: // /omap3530/assp/inc/omap3530_timer.h
williamr@4: //
williamr@4: 
williamr@4: #ifndef HEADER_OMAP3530_TIMER_H_INCLUDED
williamr@4: #	define HEADER_OMAP3530_TIMER_H_INCLUDED
williamr@4: 
williamr@4: /**
williamr@4: @file
williamr@4: 	omap3530_timer.h header file
williamr@4: This file provides timer handling for the omap3530 timers
williamr@4: @publishedAll
williamr@4: @released
williamr@4: */
williamr@4: 
williamr@4: #include <assp/omap3530_assp/omap3530_hardware_base.h>
williamr@4: #include <assp/omap3530_assp/omap3530_irqmap.h>
williamr@4: 
williamr@4: namespace TexasInstruments
williamr@4: 	{
williamr@4: 
williamr@4: 	namespace Omap3530
williamr@4: 		{
williamr@4: 
williamr@4: 
williamr@4: 		namespace GPTimer
williamr@4: 			{
williamr@4: 
williamr@4: 			namespace TIOCP_CFG
williamr@4: 				{
williamr@4: 				/**
williamr@4: 					0 AUTOIDLE Internal L4 interface clock gating strategy 0
williamr@4: 					0x0: L4 interface clock is free-running.
williamr@4: 					0x1: Automatic L4 interface clock gating strategy isapplied, based on the L4 interface activity.
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<0>	T_AUTOIDLE ;
williamr@4: 
williamr@4: 				/**
williamr@4: 					1 SOFTRESET Software reset. This bit is automatically reset by the RW 0 hardware. During reads, it always returns 0.
williamr@4: 					0x0: Normal mode
williamr@4: 					0x1: The module is reset.
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<1>	T_SOFTRESET ;
williamr@4: 
williamr@4: 				/**
williamr@4: 					2 ENAWAKEUP Wake-up feature global control RW 0
williamr@4: 					0x0: No wake-up line assertion in idle mode
williamr@4: 					0x1: Wake-up line assertion enabled in smart-idle mode
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<2>	T_ENAWAKEUP ;
williamr@4: 
williamr@4: 				/**
williamr@4: 					4:3 IDLEMODE Power management, req/ack control RW 0x0
williamr@4: 					0x0: Force-idle. An idle request is acknowledged unconditionally.
williamr@4: 					0x1: No-idle. An idle request is never acknowledged.
williamr@4: 					0x2: Smart-idle. Acknowledgement to an idle request is given based on the internal activity of the module.
williamr@4: 					0x3: Reserved. Do not use.
williamr@4: 				*/
williamr@4: 				class T_IDLEMODE : public TBitField<3, 2>
williamr@4: 					{
williamr@4: 				  public :
williamr@4: 					enum TConstants
williamr@4: 						{
williamr@4: 						KForceIdle		= TConstVal<0>::KValue,
williamr@4: 						KNoIdle			= TConstVal<1>::KValue,
williamr@4: 						KSmartIdle		= TConstVal<2>::KValue
williamr@4: 						} ;
williamr@4: 					} ;
williamr@4: 
williamr@4: 				/**
williamr@4: 					5 EMUFREE Emulation mode RW 0
williamr@4: 					0x0: Timer counter frozen in emulation
williamr@4: 					0x1: Timer counter free-running in emulation
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<5>	T_EMUFREE ;
williamr@4: 
williamr@4: 				/**
williamr@4: 					9:8 CLOCKACTIVITY Clock activity during wakeup mode period: RW 0x0
williamr@4: 					0x0: L4 interface and Functional clocks can be switched off.
williamr@4: 					0x1: L4 interface clock is maintained during wake-up period; Functional clock can be switched off.
williamr@4: 					0x2: L4 interface clock can be switched off; Functional clock is maintained during wake-up period.
williamr@4: 					0x3: L4 interface and Functional clocks are maintained during wake-up period.
williamr@4: 				*/
williamr@4: 				class T_CLOCKACTIVITY : public TBitField<8, 2>
williamr@4: 					{
williamr@4: 				  public :
williamr@4: 					enum TConstants
williamr@4: 						{
williamr@4: 						KMaintainNeither	= TConstVal<0>::KValue,
williamr@4: 						KMaintainIfClock	= TConstVal<1>::KValue,
williamr@4: 						KMaintainFuncClock	= TConstVal<2>::KValue,
williamr@4: 						KMaintainBoth		= TConstVal<3>::KValue
williamr@4: 						} ;
williamr@4: 					} ;
williamr@4: 
williamr@4: 				} ;	// namespace TIOCP_CFG
williamr@4: 
williamr@4: 			namespace TISTAT
williamr@4: 				{
williamr@4: 				/**
williamr@4: 				0 RESETDONE Internal reset monitoring R 0
williamr@4: 				0x0: Internal module reset is ongoing.
williamr@4: 				0x1: Reset completed
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<0>	T_RESETDONE ;
williamr@4: 
williamr@4: 				} ;	// namespace TISTAT
williamr@4: 
williamr@4: 			namespace TISR
williamr@4: 				{
williamr@4: 				/**
williamr@4: 				0 MAT_IT_FLAG Pending match interrupt status RW 0
williamr@4: 				Read 0x0: No match interrupt pending
williamr@4: 				Write 0x0: Status unchanged
williamr@4: 				Read 0x1: Match interrupt pending
williamr@4: 				Write 0x1: Status bit cleared
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<0>	T_MAT_IT_FLAG ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				1 OVF_IT_FLAG Pending overflow interrupt status RW 0
williamr@4: 				Read 0x0: No overflow interrupt pending
williamr@4: 				Write 0x0: Status unchanged
williamr@4: 				Read 0x1: Overflow interrupt pending
williamr@4: 				Write 0x1: Status bit cleared
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<1>	T_OVF_IT_FLAG ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				2 TCAR_IT_FLAG Pending capture interrupt status RW 0
williamr@4: 				Read 0x0: No capture interrupt event pending
williamr@4: 				Write 0x0: Status unchanged
williamr@4: 				Read 0x1: Capture interrupt event pending
williamr@4: 				Write 0x1: Status bit cleared
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<2>	T_TCAR_IT_FLAG ;
williamr@4: 
williamr@4: 				} ;	// namespace TISR
williamr@4: 
williamr@4: 			namespace TIER
williamr@4: 				{
williamr@4: 				/**
williamr@4: 				0 MAT_IT_ENA Enable match interrupt RW 0
williamr@4: 				0x0: Disable match interrupt.
williamr@4: 				0x1: Enable match interrupt.
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<0>	T_MAT_IT_ENA ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				1 OVF_IT_ENA Enable overflow interrupt RW 0
williamr@4: 				0x0: Disable overflow interrupt.
williamr@4: 				0x1: Enable overflow interrupt.
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<1>	T_OVF_IT_ENA ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				2 TCAR_IT_ENA Enable capture interrupt RW 0
williamr@4: 				0x0: Disable capture interrupt.
williamr@4: 				0x1: Enable capture interrupt.
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<2>	T_TCAR_IT_ENA ;
williamr@4: 
williamr@4: 				} ;	// namespace TIER
williamr@4: 
williamr@4: 			namespace TWER
williamr@4: 				{
williamr@4: 				/**
williamr@4: 				0 MAT_WUP_ENA Enable match wake-up RW 0
williamr@4: 				0x0: Disable match wake-up.
williamr@4: 				0x1: Enable match wake-up.
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<0>	T_MAT_WUP_ENA ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				1 OVF_WUP_ENA Enable overflow wake-up RW 0
williamr@4: 				0x0: Disable overflow wake-up.
williamr@4: 				0x1: Enable overflow wake-up.
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<1>	T_OVF_WUP_ENA ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				2 TCAR_WUP_ENA Enable capture wake-up RW 0
williamr@4: 				0x0: Disable capture wake-up.
williamr@4: 				0x1: Enable capture wake-up.
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<2>	T_TCAR_WUP_ENA ;
williamr@4: 
williamr@4: 				} ;	// namespace TWER
williamr@4: 
williamr@4: 			namespace TCLR
williamr@4: 				{
williamr@4: 				/**
williamr@4: 				0 ST Start/stop timer control RW 0
williamr@4: 				0x0: Stop the timer
williamr@4: 				0x1: Start the timer
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<0>	T_ST ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				1 AR Autoreload mode RW 0
williamr@4: 				0x0: One-shot mode overflow
williamr@4: 				0x1: Autoreload mode overflow
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<1>	T_AR ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				4:2 PTV Trigger output mode
williamr@4: 				0x0: The timer counter is prescaled with the value: RW 0x0
williamr@4: 				2(PTV+1). Example: PTV = 3, counter increases value (if started) after 16 functional clock periods.
williamr@4: 				*/
williamr@4: 				class T_PTV : public TBitField<2, 3>
williamr@4: 					{
williamr@4: 				  public :
williamr@4: 					enum TConstants
williamr@4: 						{
williamr@4: 						KPS_2		= TConstVal<0>::KValue,
williamr@4: 						KPS_4		= TConstVal<1>::KValue,
williamr@4: 						KPS_8		= TConstVal<2>::KValue,
williamr@4: 						KPS_16		= TConstVal<3>::KValue,
williamr@4: 						KPS_32		= TConstVal<4>::KValue,
williamr@4: 						KPS_64		= TConstVal<5>::KValue,
williamr@4: 						KPS_128		= TConstVal<6>::KValue,
williamr@4: 						KPS_256		= TConstVal<7>::KValue
williamr@4: 						} ;
williamr@4: 					} ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				5 PRE Prescaler enable RW 0
williamr@4: 				0x0: Prescaler disabled
williamr@4: 				0x1: Prescaler enabled
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<5>	T_PRE ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				6 CE Compare enable RW 0
williamr@4: 				0x0: Compare disabled
williamr@4: 				0x1: Compare enabled
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<6>	T_CE ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				7 SCPWM Pulse-width-modulation output pin default setting when RW 0
williamr@4: 				counter is stopped or trigger output mode is set to no trigger.
williamr@4: 				0x0: Default value of PWM_out output: 0
williamr@4: 				0x1: Default value of PWM_out output: 1
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<7>	T_SCPWM ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				9:8 TCM Transition capture mode RW 0x0
williamr@4: 				0x0: No capture
williamr@4: 				0x1: Capture on rising edges of EVENT_CAPTURE pin.
williamr@4: 				0x2: Capture on falling edges of EVENT_CAPTURE pin.
williamr@4: 				0x3: Capture on both edges of EVENT_CAPTURE pin.
williamr@4: 				*/
williamr@4: 				class T_TCM : public TBitField<8, 2>
williamr@4: 					{
williamr@4: 				  public :
williamr@4: 					enum TConstants
williamr@4: 						{
williamr@4: 						KNoCapture			= TConstVal<0>::KValue,
williamr@4: 						KRisingEdge			= TConstVal<1>::KValue,
williamr@4: 						KFallingEdge		= TConstVal<2>::KValue,
williamr@4: 						KBothEdges			= TConstVal<3>::KValue
williamr@4: 						} ;
williamr@4: 					} ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				11:10 TRG Trigger output mode RW 0x0
williamr@4: 				0x0: No trigger
williamr@4: 				0x1: Overflow trigger
williamr@4: 				0x2: Overflow and match trigger
williamr@4: 				0x3: Reserved
williamr@4: 				*/
williamr@4: 				class T_IDLEMODE : public TBitField<10, 2>
williamr@4: 					{
williamr@4: 				  public :
williamr@4: 					enum TConstants
williamr@4: 						{
williamr@4: 						KNoTrigger				= TConstVal<0>::KValue,
williamr@4: 						KOverflow				= TConstVal<1>::KValue,
williamr@4: 						KOverflowAndMatch		= TConstVal<2>::KValue
williamr@4: 						} ;
williamr@4: 					} ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				12 PT Pulse or toggle select bit RW 0
williamr@4: 				0x0: Pulse modulation
williamr@4: 				0x1: Toggle modulation
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<12>	T_PT ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				13 CAPT_MODE Capture mode select bit (first/second) RW 0
williamr@4: 				0x0: Capture the first enabled capture event in TCAR1.
williamr@4: 				0x1: Capture the second enabled capture event in TCAR2.
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<13>	T_CAPT_MODE ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				14 GPO_CFG PWM output/event detection input pin direction control: RW 0
williamr@4: 				0x0: Configures the pin as an output (needed when PWM mode is required)
williamr@4: 				0x1: Configures the pin as an input (needed when capture mode is required)
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<14>	T_GPO_CFG ;
williamr@4: 
williamr@4: 				} ;	// namespace TCLR
williamr@4: 
williamr@4: 			namespace TWPS
williamr@4: 				{
williamr@4: 				/**
williamr@4: 				0 W_PEND_TCLR Write pending for register GPT_TCLR R 0
williamr@4: 				0x0: Control register write not pending
williamr@4: 				0x1: Control register write pending
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<0>	T_W_PEND_TCLR ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				1 W_PEND_TCRR Write pending for register GPT_TCRR R 0
williamr@4: 				0x0: Counter register write not pending
williamr@4: 				0x1: Counter register write pending
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<1>	T_W_PEND_TCRR ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				2 W_PEND_TLDR Write pending for register GPT_TLDR R 0
williamr@4: 				0x0: Load register write not pending
williamr@4: 				0x1: Load register write pending
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<2>	T_W_PEND_TLDR ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				3 W_PEND_TTGR Write pending for register GPT_TTGR R 0
williamr@4: 				0x0: Trigger register write not pending
williamr@4: 				0x1: Trigger register write pending
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<3>	T_W_PEND_TTGR ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				4 W_PEND_TMAR Write pending for register GPT_TMAR R 0
williamr@4: 				0x0: Match register write not pending
williamr@4: 				0x1: Match register write pending
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<4>	T_W_PEND_TMAR;
williamr@4: 
williamr@4: 				/**
williamr@4: 				5 W_PEND_TPIR Write pending for register GPT_TPIR R 0
williamr@4: 				Reserved for instances 3, 4, 5, 6, 7, 8, 9, 11, 12 Read returns reset value. R 0
williamr@4: 				0x0: Positive increment register write not pending
williamr@4: 				0x1: Positive increment register write pending
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<5>	T_W_PEND_TPIR ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				6 W_PEND_TNIR Write pending for register GPT_TNIR R 0
williamr@4: 				0x0: Negative increment register write not pending
williamr@4: 				0x1: Negative increment register write pending
williamr@4: 				Reserved for instances 3, 4, 5, 6, 7, 8, 9, 11, 12 Read returns reset value. R 0
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<6>	T_W_PEND_TNIR ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				7 W_PEND_TCVR Write pending for register GPT_TCVR R 0
williamr@4: 				0x0: Counter value register write not pending
williamr@4: 				0x1: Counter value register write pending
williamr@4: 				Reserved for instances 3, 4, 5, 6, 7, 8, 9, 11, 12 Read returns reset value. R 0
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<7>	T_W_PEND_TCVR ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				8 W_PEND_TOCR Write pending for register GPT_TOCR R 0
williamr@4: 				0x0: Overflow counter register write not pending
williamr@4: 				0x1: Overflow counter register write pending
williamr@4: 				Reserved for instances 3, 4, 5, 6, 7, 8, 9, 11, 12 Read returns reset value. R 0
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<8>	T_W_PEND_TOCR ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				9 W_PEND_TOWR Write pending for register GPT_TOWR R 0
williamr@4: 				0x0: Overflow wrapping register write not pending
williamr@4: 				0x1: Overflow wrapping register write pending
williamr@4: 				Reserved for instances 3, 4, 5, 6, 7, 8, 9, 11, 12 Read returns reset value. R 0
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<9>	T_W_PEND_TOWR ;
williamr@4: 
williamr@4: 				} ;	// namespace TWPS
williamr@4: 
williamr@4: 			namespace TSICR
williamr@4: 				{
williamr@4: 				/**
williamr@4: 				1 SFT Reset software functional registers. This bit is automatically reset RW 0
williamr@4: 				by the hardware. During reads, it always returns 0.
williamr@4: 				0x0: Normal functional mode
williamr@4: 				0x1: The functional registers are reset.
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<1>	T_SFT ;
williamr@4: 
williamr@4: 				/**
williamr@4: 				2 POSTED Posted mode selection RW 1
williamr@4: 				0x0: Non-posted mode selected
williamr@4: 				0x1: Posted mode selected
williamr@4: 				*/
williamr@4: 				typedef TSingleBitField<2>	T_POSTED ;
williamr@4: 
williamr@4: 				} ;	// namespace TSICR
williamr@4: 
williamr@4: 			namespace TOCR
williamr@4: 				{
williamr@4: 				/**
williamr@4: 				23:0 OVF_COUNTER_VALUE The number of overflow events. RW 0x00000000
williamr@4: 				*/
williamr@4: 				class T_OVF_COUNTER_VALUE : public TBitField<0, 24>
williamr@4: 					{
williamr@4: 				  public :
williamr@4: 					enum TConstants
williamr@4: 						{
williamr@4: 						} ;
williamr@4: 					} ;
williamr@4: 
williamr@4: 				} ;	// namespace TOCR
williamr@4: 
williamr@4: 			namespace TOWR
williamr@4: 				{
williamr@4: 				/**
williamr@4: 				23:0 OVF_WRAPPING_VALUE The number of masked interrupts. RW 0x00000000
williamr@4: 				*/
williamr@4: 				class T_OVF_WRAPPING_VALUE : public TBitField<0, 24>
williamr@4: 					{
williamr@4: 				  public :
williamr@4: 					enum TConstants
williamr@4: 						{
williamr@4: 						} ;
williamr@4: 					} ;
williamr@4: 
williamr@4: 				} ;	// namespace TOWR
williamr@4: 
williamr@4: 			enum TBaseAddress
williamr@4: 				{
williamr@4: 				KGPTIMER1_Base			= TVirtual<0x48318000>::Value,
williamr@4: 				KGPTIMER2_Base			= TVirtual<0x49032000>::Value,
williamr@4: 				KGPTIMER3_Base			= TVirtual<0x49034000>::Value,
williamr@4: 				KGPTIMER4_Base			= TVirtual<0x49036000>::Value,
williamr@4: 				KGPTIMER5_Base			= TVirtual<0x49038000>::Value,
williamr@4: 				KGPTIMER6_Base			= TVirtual<0x4903A000>::Value,
williamr@4: 				KGPTIMER7_Base			= TVirtual<0x4903C000>::Value,
williamr@4: 				KGPTIMER8_Base			= TVirtual<0x4903E000>::Value,
williamr@4: 				KGPTIMER9_Base			= TVirtual<0x49040000>::Value,
williamr@4: 				KGPTIMER10_Base			= TVirtual<0x48086000>::Value,
williamr@4: 				KGPTIMER11_Base			= TVirtual<0x48088000>::Value,
williamr@4: 				KGPTIMER12_Base			= TVirtual<0x48304000>::Value,
williamr@4: 				} ;
williamr@4: 
williamr@4: 			enum TTimerNumber
williamr@4: 				{
williamr@4: 				EGpTimer1,
williamr@4: 				EGpTimer2,
williamr@4: 				EGpTimer3,
williamr@4: 				EGpTimer4,
williamr@4: 				EGpTimer5,
williamr@4: 				EGpTimer6,
williamr@4: 				EGpTimer7,
williamr@4: 				EGpTimer8,
williamr@4: 				EGpTimer9,
williamr@4: 				EGpTimer10,
williamr@4: 				EGpTimer11,
williamr@4: 				EGpTimer12
williamr@4: 				};
williamr@4: 
williamr@4: 			typedef void (*TTimerIsr)(TAny*) ;
williamr@4: 
williamr@4: 			template<const TTimerNumber tImEr>
williamr@4: 			struct TTimerTraits
williamr@4: 				{
williamr@4: 				} ;
williamr@4: 
williamr@4: 			template<>
williamr@4: 			struct TTimerTraits<EGpTimer1>
williamr@4: 				{
williamr@4: 				enum	TraitValues
williamr@4: 					{
williamr@4: 					KBaseAddress	= KGPTIMER1_Base,
williamr@4: 					KIrq			= EOmap3530_IRQ37_GPT1_IRQ,
williamr@4: 					KClockSelMask	= TSingleBitField<7>::KMask,
williamr@4: 					KClockSelValue	= TSingleBitField<7>::KOn,
williamr@4: 					} ;
williamr@4: 				} ;
williamr@4: 
williamr@4: 			template<>
williamr@4: 			struct TTimerTraits<EGpTimer2>
williamr@4: 				{
williamr@4: 				enum	TraitValues
williamr@4: 					{
williamr@4: 					KBaseAddress	= KGPTIMER2_Base,
williamr@4: 					KIrq	= EOmap3530_IRQ38_GPT2_IRQ,
williamr@4: 					} ;
williamr@4: 				} ;
williamr@4: 
williamr@4: 			template<>
williamr@4: 			struct TTimerTraits<EGpTimer3>
williamr@4: 				{
williamr@4: 				enum	TraitValues
williamr@4: 					{
williamr@4: 					KBaseAddress	= KGPTIMER3_Base,
williamr@4: 					KIrq	= EOmap3530_IRQ39_GPT3_IRQ,
williamr@4: 					} ;
williamr@4: 				} ;
williamr@4: 
williamr@4: 			template<>
williamr@4: 			struct TTimerTraits<EGpTimer4>
williamr@4: 				{
williamr@4: 				enum	TraitValues
williamr@4: 					{
williamr@4: 					KBaseAddress	= KGPTIMER4_Base,
williamr@4: 					KIrq	= EOmap3530_IRQ40_GPT4_IRQ,
williamr@4: 					} ;
williamr@4: 				} ;
williamr@4: 
williamr@4: 			template<>
williamr@4: 			struct TTimerTraits<EGpTimer5>
williamr@4: 				{
williamr@4: 				enum	TraitValues
williamr@4: 					{
williamr@4: 					KBaseAddress	= KGPTIMER5_Base,
williamr@4: 					KIrq	= EOmap3530_IRQ41_GPT5_IRQ,
williamr@4: 					} ;
williamr@4: 				} ;
williamr@4: 
williamr@4: 			template<>
williamr@4: 			struct TTimerTraits<EGpTimer6>
williamr@4: 				{
williamr@4: 				enum	TraitValues
williamr@4: 					{
williamr@4: 					KBaseAddress	= KGPTIMER6_Base,
williamr@4: 					KIrq	= EOmap3530_IRQ42_GPT6_IRQ,
williamr@4: 					} ;
williamr@4: 				} ;
williamr@4: 
williamr@4: 			template<>
williamr@4: 			struct TTimerTraits<EGpTimer7>
williamr@4: 				{
williamr@4: 				enum	TraitValues
williamr@4: 					{
williamr@4: 					KBaseAddress	= KGPTIMER7_Base,
williamr@4: 					KIrq	= EOmap3530_IRQ43_GPT7_IRQ,
williamr@4: 					} ;
williamr@4: 				} ;
williamr@4: 
williamr@4: 			template<>
williamr@4: 			struct TTimerTraits<EGpTimer8>
williamr@4: 				{
williamr@4: 				enum	TraitValues
williamr@4: 					{
williamr@4: 					KBaseAddress	= KGPTIMER8_Base,
williamr@4: 					KIrq	= EOmap3530_IRQ44_GPT8_IRQ,
williamr@4: 					} ;
williamr@4: 				} ;
williamr@4: 
williamr@4: 			template<>
williamr@4: 			struct TTimerTraits<EGpTimer9>
williamr@4: 				{
williamr@4: 				enum	TraitValues
williamr@4: 					{
williamr@4: 					KBaseAddress	= KGPTIMER9_Base,
williamr@4: 					KIrq			= EOmap3530_IRQ45_GPT9_IRQ,
williamr@4: 					} ;
williamr@4: 				} ;
williamr@4: 
williamr@4: 			template<>
williamr@4: 			struct TTimerTraits<EGpTimer10>
williamr@4: 				{
williamr@4: 				enum	TraitValues
williamr@4: 					{
williamr@4: 					KBaseAddress	= KGPTIMER10_Base,
williamr@4: 					KIrq	= EOmap3530_IRQ46_GPT10_IRQ,
williamr@4: 					} ;
williamr@4: 				} ;
williamr@4: 
williamr@4: 			template<>
williamr@4: 			struct TTimerTraits<EGpTimer11>
williamr@4: 				{
williamr@4: 				enum	TraitValues
williamr@4: 					{
williamr@4: 					KBaseAddress	= KGPTIMER11_Base,
williamr@4: 					KIrq			= EOmap3530_IRQ47_GPT11_IRQ,
williamr@4: 					} ;
williamr@4: 				} ;
williamr@4: 
williamr@4: 			template<>
williamr@4: 			struct TTimerTraits<EGpTimer12>
williamr@4: 				{
williamr@4: 				enum	TraitValues
williamr@4: 					{
williamr@4: 					KBaseAddress	= KGPTIMER12_Base,
williamr@4: 					KIrq			= EOmap3530_IRQ95_GPT12_IRQ,
williamr@4: 					KClockSelReg	= 0,
williamr@4: 					KClockSelMask	= 0,
williamr@4: 					KClockSel32K	= 0,
williamr@4: 					KClockSelSys	= 0,
williamr@4: 					KClockSelValue	= KClockSel32K
williamr@4: 					} ;
williamr@4: 				} ;
williamr@4: 
williamr@4: 			/**
williamr@4: 			An interface template for OMAP3530 General Purpose timer functionality.
williamr@4: 			*/
williamr@4: 			template <const TTimerNumber tImEr>
williamr@4: 			class TGPT
williamr@4: 				{
williamr@4: 			  protected :
williamr@4: 				enum TRegisterOffsets
williamr@4: 					{
williamr@4: 					KTIOCP_CFG_Offset	= 0x010,
williamr@4: 					KTISTAT_Offset		= 0x014,
williamr@4: 					KTISR_Offset		= 0x018,
williamr@4: 					KTIER_Offset		= 0x01C,
williamr@4: 					KTWER_Offset		= 0x020,
williamr@4: 					KTCLR_Offset		= 0x024,
williamr@4: 					KTCRR_Offset		= 0x028,
williamr@4: 					KTLDR_Offset		= 0x02C,
williamr@4: 					KTTGR_Offset		= 0x030,
williamr@4: 					KTWPS_Offset		= 0x034,
williamr@4: 					KTMAR_Offset		= 0x038,
williamr@4: 					KTCAR1_Offset		= 0x03C,
williamr@4: 					KTSICR_Offset		= 0x040,
williamr@4: 					KTCAR2_Offset		= 0x044
williamr@4: 					} ;
williamr@4: 				enum TConstants
williamr@4: 					{
williamr@4: 					KHz						= 1000,
williamr@4: 					KClockInputFrequency	= 32768,
williamr@4: 					} ;
williamr@4: 
williamr@4: 			  public :
williamr@4: 				static inline TOmap3530_IRQ Irq()
williamr@4: 					{
williamr@4: 					return TOmap3530_IRQ(TTimerTraits<tImEr>::KIrq) ;
williamr@4: 					}
williamr@4: 				static inline TBool CanWriteTCLR()
williamr@4: 					{
williamr@4: 					return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TCLR::KOn)) ;
williamr@4: 					}
williamr@4: 				static inline TBool CanWriteTCRR()
williamr@4: 					{
williamr@4: 					return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TCRR::KOn)) ;
williamr@4: 					}
williamr@4: 				static inline TBool CanWriteTLDR()
williamr@4: 					{
williamr@4: 					return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TLDR::KOn)) ;
williamr@4: 					}
williamr@4: 				static inline TBool CanWriteTTGR()
williamr@4: 					{
williamr@4: 					return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TTGR::KOn)) ;
williamr@4: 					}
williamr@4: 				static inline TBool CanWriteTMAR()
williamr@4: 					{
williamr@4: 					return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TMAR::KOn)) ;
williamr@4: 					}
williamr@4: 				static inline void Reset()
williamr@4: 					{
williamr@4: 					iTIOCP_CFG.Write(TIOCP_CFG::T_SOFTRESET::KOn) ;
williamr@4: 					}
williamr@4: 				static inline TBool ResetComplete()
williamr@4: 					{
williamr@4: 					return (TISTAT::T_RESETDONE::KOn & iTISTAT.Read()) ;
williamr@4: 					}
williamr@4: 				static inline TBool WriteOutstanding()
williamr@4: 					{
williamr@4: 					return (iTWPS.Read()) ;
williamr@4: 					}
williamr@4: 
williamr@4: 			  public :
williamr@4: 				static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTIOCP_CFG_Offset)>	iTIOCP_CFG ;
williamr@4: 				static TReg32_R<(TTimerTraits<tImEr>::KBaseAddress  + KTISTAT_Offset)>		iTISTAT ;
williamr@4: 				static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTISR_Offset)>		iTISR ;
williamr@4: 				static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTIER_Offset)>		iTIER ;
williamr@4: 				static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTWER_Offset)>		iTWER ;
williamr@4: 				static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTCLR_Offset)>		iTCLR ;
williamr@4: 				static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTCRR_Offset)>		iTCRR ;
williamr@4: 				static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTLDR_Offset)>		iTLDR ;
williamr@4: 				static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTTGR_Offset)>		iTTGR ;
williamr@4: 				static TReg32_R<(TTimerTraits<tImEr>::KBaseAddress  + KTWPS_Offset)>		iTWPS ;
williamr@4: 				static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTMAR_Offset)>		iTMAR ;
williamr@4: 				static TReg32_R<(TTimerTraits<tImEr>::KBaseAddress  + KTCAR1_Offset)>		iTCAR1 ;
williamr@4: 				static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTSICR_Offset)>		iTSICR ;
williamr@4: 				static TReg32_R<(TTimerTraits<tImEr>::KBaseAddress  + KTCAR2_Offset)>		iTCAR2 ;
williamr@4: 				} ;	// class TGPTi
williamr@4: 
williamr@4: 			/**
williamr@4: 
williamr@4: 			An interface template for OMAP3530 Microsecond aligned timer functionality.
williamr@4: 			Encapsulates the extra registers provided for timers 1, 2 and 10.
williamr@4: 			*/
williamr@4: 			template <const TTimerNumber tImEr>
williamr@4: 			class TMsSyncTimer : public TGPT<tImEr>
williamr@4: 				{
williamr@4: 				using TGPT<tImEr>::iTWPS ;
williamr@4: 				using TGPT<tImEr>::iTLDR ;
williamr@4: 			  
williamr@4: 			protected :
williamr@4: 				enum TRegisterOffsets
williamr@4: 					{
williamr@4: 					KTPIR_Offset		= 0x048,
williamr@4: 					KTNIR_Offset		= 0x04C,
williamr@4: 					KTCVR_Offset		= 0x050,
williamr@4: 					KTOCR_Offset		= 0x054,
williamr@4: 					KTOWR_Offset		= 0x058
williamr@4: 					} ;
williamr@4: 
williamr@4: 			  public :
williamr@4: 				enum TRegisterValues
williamr@4: 					{
williamr@4: 					KInitialLoad	= 0xFFFFFFE0,
williamr@4: 					KInitialPIR		= 0x38A40,
williamr@4: 					KInitialNIR		= 0xFFF44800
williamr@4: 					} ;
williamr@4: 
williamr@4: 				static inline TBool CanWriteTPIR()
williamr@4: 					{
williamr@4: 					return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TPIR::KOn)) ;
williamr@4: 					}
williamr@4: 				static inline TBool CanWriteTNIR()
williamr@4: 					{
williamr@4: 					return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TNIR::KOn)) ;
williamr@4: 					}
williamr@4: 				static inline TBool CanWriteTCVR()
williamr@4: 					{
williamr@4: 					return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TCVR::KOn)) ;
williamr@4: 					}
williamr@4: 				static inline TBool CanWriteTOCR()
williamr@4: 					{
williamr@4: 					return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TOCR::KOn)) ;
williamr@4: 					}
williamr@4: 				static inline TBool CanWriteTOWR()
williamr@4: 					{
williamr@4: 					return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TOWR::KOn)) ;
williamr@4: 					}
williamr@4: 
williamr@4: 				static inline void ConfigureFor1Ms()
williamr@4: 					{
williamr@4: 					iTLDR.Write( KInitialLoad );
williamr@4: 					iTPIR.Write( KInitialPIR );
williamr@4: 					iTNIR.Write( KInitialNIR );
williamr@4: 					}
williamr@4: 
williamr@4: 			  public :
williamr@4: 				static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTPIR_Offset)>		iTPIR ;
williamr@4: 				static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTNIR_Offset)>		iTNIR ;
williamr@4: 				static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTCVR_Offset)>		iTCVR ;
williamr@4: 				static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTOCR_Offset)>		iTOCR ;
williamr@4: 				static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTOWR_Offset)>		iTOWR ;
williamr@4: 				} ;	// class TMsSyncTimer
williamr@4: 
williamr@4: 
williamr@4: 			}	// namespage GPTimer
williamr@4: 
williamr@4: 		typedef GPTimer::TMsSyncTimer<GPTimer::EGpTimer1>		TGpTimer1 ;
williamr@4: 		typedef GPTimer::TMsSyncTimer<GPTimer::EGpTimer2>		TGpTimer2 ;
williamr@4: 		typedef GPTimer::TGPT<GPTimer::EGpTimer3>				TGpTimer3 ;
williamr@4: 		typedef GPTimer::TGPT<GPTimer::EGpTimer4>				TGpTimer4 ;
williamr@4: 		typedef GPTimer::TGPT<GPTimer::EGpTimer5>				TGpTimer5 ;
williamr@4: 		typedef GPTimer::TGPT<GPTimer::EGpTimer6>				TGpTimer6 ;
williamr@4: 		typedef GPTimer::TGPT<GPTimer::EGpTimer7>				TGpTimer7 ;
williamr@4: 		typedef GPTimer::TGPT<GPTimer::EGpTimer8>				TGpTimer8 ;
williamr@4: 		typedef GPTimer::TGPT<GPTimer::EGpTimer9>				TGpTimer9 ;
williamr@4: 		typedef GPTimer::TMsSyncTimer<GPTimer::EGpTimer10>		TGpTimer10 ;
williamr@4: 		typedef GPTimer::TGPT<GPTimer::EGpTimer11>				TGpTimer11 ;
williamr@4: 		typedef GPTimer::TGPT<GPTimer::EGpTimer12>				TGpTimer12 ;
williamr@4: 
williamr@4: 
williamr@4: 		/**
williamr@4: 		An interface template for OMAP3530 32-KHz aligned timer functionality.
williamr@4: 		*/
williamr@4: 		class T32KhzSyncTimer
williamr@4: 			{
williamr@4: 		  protected :
williamr@4: 			enum TRegisterAddress
williamr@4: 				{
williamr@4: 				KREG_32KSYNCNT_SYSCONFIG	= TVirtual<0x48320004>::Value,
williamr@4: 				KREG_32KSYNCNT_CR			= TVirtual<0x48320010>::Value
williamr@4: 				} ;
williamr@4: 
williamr@4: 		  public :
williamr@4: 			static TReg32_RW<KREG_32KSYNCNT_SYSCONFIG>		iSysConfig ;
williamr@4: 			static TReg32_R<KREG_32KSYNCNT_CR>				iCR ;
williamr@4: 
williamr@4: 		  private :
williamr@4: 			} ;	// class TMsSyncTimer
williamr@4: 
williamr@4: 		}	// namespace Omap3530
williamr@4: 
williamr@4: 	}	// namespace TexasInstruments
williamr@4: 
williamr@4: 
williamr@4: // **** TEST CODE ****
williamr@4: //#	define HEADER_OMAP3530_TIMER_H_DO_COMPILE_TIME_CHECK_TESTS 1
williamr@4: #	ifdef HEADER_OMAP3530_TIMER_H_DO_COMPILE_TIME_CHECK_TESTS
williamr@4: 		inline void CompileTimeChecks(void)
williamr@4: 			{
williamr@4: 			__ASSERT_COMPILE((TI::Omap3530::GPTimer::TIOCP_CFG::T_IDLEMODE::KSmartIdle == (2 << 3))) ;
williamr@4: 			__ASSERT_COMPILE((TI::Omap3530::GPTimer::TIOCP_CFG::T_CLOCKACTIVITY::KMaintainIfClock == (1 << 8))) ;
williamr@4: 			__ASSERT_COMPILE((TI::Omap3530::GPTimer::KGPTIMER1_Base == (0xC6318000))) ;
williamr@4: 			__ASSERT_COMPILE((0)) ;		// Prove that testing is happening
williamr@4: 			}
williamr@4: #	endif
williamr@4: #endif	/* ndef HEADER_OMAP3530_TIMER_H_INCLUDED */