williamr@4: // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
williamr@4: // All rights reserved.
williamr@4: // This component and the accompanying materials are made available
williamr@4: // under the terms of the License "Eclipse Public License v1.0"
williamr@4: // which accompanies this distribution, and is available
williamr@4: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
williamr@4: //
williamr@4: // Initial Contributors:
williamr@4: // Nokia Corporation - initial contribution.
williamr@4: //
williamr@4: // Contributors:
williamr@4: //
williamr@4: // Description:
williamr@4: // \omap3530\omap3530_assp\prcm.h
williamr@4: // Access to PRCM.
williamr@4: // This file is part of the Beagle Base port
williamr@4: //
williamr@4: 
williamr@4: #ifndef PRCM_H__
williamr@4: #define PRCM_H__
williamr@4: 
williamr@4: #include <e32cmn.h>
williamr@4: #include <assp/omap3530_assp/omap3530_irqmap.h>
williamr@4: 
williamr@4: namespace Prcm
williamr@4: {
williamr@4: enum TPanic
williamr@4: 	{
williamr@4: 	ESetPllConfigBadPll,	///< bad PLL ID in SetPllConfiguration()
williamr@4: 	EGetPllConfigBadPll,	///< bad PLL ID in PllConfiguration()
williamr@4: 	ESetPllConfigBadFreqRange,	///< bad PLL frequency range in SetPllConfiguration()
williamr@4: 	ESetPllConfigBadRamp,		///< bad PLL ramp setting in SetPllConfiguration()
williamr@4: 	ESetPllConfigBadDrift,		///< bad PLL drift setting in SetPllConfiguration()
williamr@4: 	ESetPllConfigBadDivider,	///< bad divider setting in SetPllConfiguration()
williamr@4: 	ESetPllConfigBadMultiplier,	///< bad divider setting in SetPllConfiguration()
williamr@4: 	ESetPllLpBadPll,		///< bad PLL ID in SetPllLp()
williamr@4: 	EGetPllLpBadPll,		///< bad PLL ID in PllLp()
williamr@4: 	ESetPllLpBadMode,		///< bad PLL LP mode in SetPllLp()
williamr@4: 	ESetDividerBadClock,	///< bad clock ID in SetDivider()
williamr@4: 	EGetDividerBadClock,	///< bad clock ID in Divider()
williamr@4: 	ESetStateBadClock,		///< bad clock ID in SetClockState()
williamr@4: 	ESetWakeupBadClock,		///< bad clock ID in SetWakeupMode()
williamr@4: 	ESetPllModeBadClock,
williamr@4: 	ESetPllModeBadMode,
williamr@4: 	EGetStateBadClock,		///< bad clock ID in ClockState()
williamr@4: 	EGetWakeupBadClock,		///< bad clock ID in WakeupMode()
williamr@4: 	ESetGptClockBadGpt,		///< bad GPT ID in SetGptClockSource()
williamr@4: 	EGetWakeupGroupBadClock,
williamr@4: 	EGetWakeupGroupBadGroup,
williamr@4: 	EAddWakeupGroupBadClock,
williamr@4: 	EAddWakeupGroupBadGroup,
williamr@4: 	ERemoveWakeupGroupBadClock,
williamr@4: 	ERemoveWakeupGroupBadGroup,
williamr@4: 	EAddDomainBadClock,		///< bad clock in call to AddToWakeupDomain()
williamr@4: 	ERemoveDomainBadClock,	///< bad clock in call to RemoveFromWakeupDomain()
williamr@4: 	ECheckDomainBadClock,	///< bad clock in call to IsInWakeupDomain()
williamr@4: 	EAddDomainBadDomain,	///< bad domain in call to AddToWakeupDomain()
williamr@4: 	ERemoveDomainBadDomain,	///< bad domain in call to RemoveFromWakeupDomain()
williamr@4: 	ECheckDomainBadDomain,	///< bad domain in call to IsInWakeupDomain()
williamr@4: 	ESetDividerUnsupportedClock,	///< attempt to set divider on clock that does not have divider
williamr@4: 	ESetDividerBadDivider,	///< bad divider value in SetDivider()
williamr@4: 	EGetNameBadClock,		///< bad clock ID in PrmName()
williamr@4: 	EClockFrequencyBadClock,	///< bad clock ID in ClockFrequency()
williamr@4: 	ESetClockMuxBadClock,	///< bad clock ID in SetClockMux()
williamr@4: 	ESetClockMuxBadSource,	///< bad source clock ID in SetClockMux()
williamr@4: 	EGetClockMuxBadClock,	///< bad clock ID in ClockMux()
williamr@4: 	ESetDomainModeBadDomain,	///< bad domain in SetPowerDomainMode()
williamr@4: 	ESetDomainModeBadMode,		///< bad mode in SetPowerDomainMode()
williamr@4: 	EGetDomainModeBadDomain,	///< bad domain in PowerDomainMode()
williamr@4: 	ESetDomainModeUnsupportedMode,	///< mode requested in SetPowerDomainMode() not supported by that domain
williamr@4: 	EPllIsLockedBadPll,			///< bad PLL ID in PllIsLocked()
williamr@4: 	EWaitForPllLockBadPll,		///< bad PLL ID in WaitForPllLocked()
williamr@4: 	ESetPllBypassDividerBadPll,	///< bad PLL ID in SetPllBypassDivider()
williamr@4: 	EPllBypassDividerBadPll,		///< bad PLL ID in PllBypassDivider()
williamr@4: 	ESetPllBypassDividerBadDivider,	///< bad dividier value in SetPllBypassDivider()
williamr@4: 	EPllInternalFrequencyOutOfRange	///< PLL internal frequency out of range in AutoSetPllFrequencyRange()
williamr@4: 	};
williamr@4: 
williamr@4: enum TClock
williamr@4: 	{
williamr@4: 	EClkMpu,		///< DPLL1
williamr@4: 	EClkIva2Pll,	///< DPLL2
williamr@4: 	EClkCore,		///< DPLL3
williamr@4: 	EClkPeriph,		///< DPLL4
williamr@4: 	EClkPeriph2,	///< DPLL5
williamr@4: 
williamr@4: 	EClkPrcmInterface,
williamr@4: 
williamr@4: 	EClkEmu,		///< Emulation clock
williamr@4: 	EClkNeon,
williamr@4: 
williamr@4: 	EClkL3Domain,
williamr@4: 	EClkL4Domain,
williamr@4: 
williamr@4: 	EClkMpuPll_Bypass,	///< DPLL1 bypass frequency
williamr@4: 	EClkIva2Pll_Bypass,	///< DPLL2 bypass frequency
williamr@4: 	EClkRM_F,			///< Reset manager functional clock	
williamr@4: 	EClk96M,			///< 96MHz clock
williamr@4: 	EClk120M,			///< 120MHz clock
williamr@4: 	EClkSysOut,
williamr@4: 
williamr@4: 	// Functional clocks
williamr@4: 	EClkTv_F,			///< TV functional clock, same as 54MHz FCLK
williamr@4: 	EClkDss1_F,
williamr@4: 	EClkDss2_F,
williamr@4: 	EClkCsi2_F,
williamr@4: 	EClkCam_F,
williamr@4: 	EClkIva2_F,
williamr@4: 	EClkMmc1_F,
williamr@4: 	EClkMmc2_F,
williamr@4: 	EClkMmc3_F,
williamr@4: 	EClkMsPro_F,
williamr@4: 	EClkHdq_F,
williamr@4: 	EClkMcBsp1_F,
williamr@4: 	EClkMcBsp2_F,
williamr@4: 	EClkMcBsp3_F,
williamr@4: 	EClkMcBsp4_F,
williamr@4: 	EClkMcBsp5_F,
williamr@4: 	EClkMcSpi1_F,
williamr@4: 	EClkMcSpi2_F,
williamr@4: 	EClkMcSpi3_F,
williamr@4: 	EClkMcSpi4_F,
williamr@4: 	EClkI2c1_F,
williamr@4: 	EClkI2c2_F,
williamr@4: 	EClkI2c3_F,
williamr@4: 	EClkUart1_F,
williamr@4: 	EClkUart2_F,
williamr@4: 	EClkUart3_F,
williamr@4: 	EClkGpt1_F,
williamr@4: 	EClkGpt2_F,
williamr@4: 	EClkGpt3_F,
williamr@4: 	EClkGpt4_F,
williamr@4: 	EClkGpt5_F,
williamr@4: 	EClkGpt6_F,
williamr@4: 	EClkGpt7_F,
williamr@4: 	EClkGpt8_F,
williamr@4: 	EClkGpt9_F,
williamr@4: 	EClkGpt10_F,
williamr@4: 	EClkGpt11_F,
williamr@4: 	EClkUsbTll_F,
williamr@4: 	EClkTs_F,
williamr@4: 	EClkCpeFuse_F,
williamr@4: 
williamr@4: 	EClkSgx_F,
williamr@4: 
williamr@4: 	EClkUsim_F,
williamr@4: 	EClkSmartReflex2_F,
williamr@4: 	EClkSmartReflex1_F,
williamr@4: 	EClkWdt2_F,
williamr@4: 	EClkWdt3_F,
williamr@4: 	EClkGpio1_F,
williamr@4: 	EClkGpio2_F,
williamr@4: 	EClkGpio3_F,
williamr@4: 	EClkGpio4_F,
williamr@4: 	EClkGpio5_F,
williamr@4: 	EClkGpio6_F,
williamr@4: 
williamr@4: 	EClkUsb120_F,		///< USB host 120MHz functional clock
williamr@4: 	EClkUsb48_F,		///< USB host 48MHz functional clock
williamr@4: 
williamr@4: 
williamr@4: 	// Interface clocks
williamr@4: 	EClkDss_I,
williamr@4: 	EClkCam_I,
williamr@4: 	EClkIcr_I,
williamr@4: 	EClkMmc1_I,
williamr@4: 	EClkMmc2_I,
williamr@4: 	EClkMmc3_I,
williamr@4: 	EClkMsPro_I,
williamr@4: 	EClkHdq_I,
williamr@4: 	EClkAes1_I,
williamr@4: 	EClkAes2_I,
williamr@4: 	EClkSha11_I,
williamr@4: 	EClkSha12_I,
williamr@4: 	EClkDes1_I,
williamr@4: 	EClkDes2_I,
williamr@4: 	EClkMcBsp1_I,
williamr@4: 	EClkMcBsp2_I,
williamr@4: 	EClkMcBsp3_I,
williamr@4: 	EClkMcBsp4_I,
williamr@4: 	EClkMcBsp5_I,
williamr@4: 	EClkI2c1_I,
williamr@4: 	EClkI2c2_I,
williamr@4: 	EClkI2c3_I,
williamr@4: 	EClkUart1_I,
williamr@4: 	EClkUart2_I,
williamr@4: 	EClkUart3_I,
williamr@4: 	EClkMcSpi1_I,
williamr@4: 	EClkMcSpi2_I,
williamr@4: 	EClkMcSpi3_I,
williamr@4: 	EClkMcSpi4_I,
williamr@4: 	EClkGpt1_I,
williamr@4: 	EClkGpt2_I,
williamr@4: 	EClkGpt3_I,
williamr@4: 	EClkGpt4_I,
williamr@4: 	EClkGpt5_I,
williamr@4: 	EClkGpt6_I,
williamr@4: 	EClkGpt7_I,
williamr@4: 	EClkGpt8_I,
williamr@4: 	EClkGpt9_I,
williamr@4: 	EClkGpt10_I,
williamr@4: 	EClkGpt11_I,
williamr@4: 	EClkGpt12_I,
williamr@4: 	EClkMailboxes_I,
williamr@4: 	EClkOmapSCM_I,
williamr@4: 	EClkHsUsbOtg_I,
williamr@4: 	EClkSdrc_I,
williamr@4: 	EClkPka_I,
williamr@4: 	EClkRng_I,
williamr@4: 	EClkUsbTll_I,
williamr@4: 
williamr@4: 	EClkSgx_I,
williamr@4: 
williamr@4: 	EClkUsim_I,
williamr@4: 	EClkWdt1_I,
williamr@4: 	EClkWdt2_I,
williamr@4: 	EClkWdt3_I,
williamr@4: 	EClkGpio1_I,
williamr@4: 	EClkGpio2_I,
williamr@4: 	EClkGpio3_I,
williamr@4: 	EClkGpio4_I,
williamr@4: 	EClkGpio5_I,
williamr@4: 	EClkGpio6_I,
williamr@4: 	EClk32Sync_I,
williamr@4: 
williamr@4: 	EClkUsb_I,			///< USB host interface clock
williamr@4: 
williamr@4: 	EClk48M,			///< 48MHz clock
williamr@4: 	EClk12M,			///< 12MHz clock
williamr@4: 
williamr@4: 	// These cannot be modified, they just represent the input clocks
williamr@4: 	// They must remain last in the table
williamr@4: 	EClkSysClk,			///< SYSCLK input clock
williamr@4: 	EClkAltClk,			///< SYSCLK32k input clock
williamr@4: 	EClkSysClk32k,		///< ALTCLK input clock
williamr@4: 
williamr@4: 	KSupportedClockCount
williamr@4: 	};
williamr@4: 
williamr@4: enum TInterruptIds
williamr@4: 	{
williamr@4: 	EIntWkUp	= (EIrqRangeBasePrcm << KIrqRangeIndexShift),
williamr@4: 	EIntUnused1,
williamr@4: 	EIntEvGenOn,
williamr@4: 	EIntEvGenOff,
williamr@4: 	EIntTransition,
williamr@4: 	EIntCoreDpll,
williamr@4: 	EIntPeriphDpll,
williamr@4: 	EIntMpuDpll,
williamr@4: 	EIntIvaDpll,
williamr@4: 	EIntIo,
williamr@4: 	EIntVp1OpChangeDone,
williamr@4: 	EIntVp1MinVdd,
williamr@4: 	EIntVp1MaxVdd,
williamr@4: 	EIntVp1NoSmpsAck,
williamr@4: 	EIntVp1EqValue,
williamr@4: 	EIntVp1TranDone,
williamr@4: 	EIntVp2OpChangeDone,
williamr@4: 	EIntVp2MinVdd,
williamr@4: 	EIntVp2MaxVdd,
williamr@4: 	EIntVp2NoSmpsAck,
williamr@4: 	EIntVp2EqValue,
williamr@4: 	EIntVp2TranDone,
williamr@4: 	EIntVcSaErr,
williamr@4: 	EIntVcRaErr,
williamr@4: 	EIntVcTimeoutErr,
williamr@4: 	EIntSndPeriphDpll,
williamr@4: 
williamr@4: 	KPrcmLastInterruptPlusOne
williamr@4: 	};
williamr@4: const TInt KInterruptCount = KPrcmLastInterruptPlusOne - EIrqRangeBasePrcm;
williamr@4: 
williamr@4: 
williamr@4: /** GPT reference enumeration */
williamr@4: enum TGpt
williamr@4: 	{
williamr@4: 	EGpt1,
williamr@4: 	EGpt2,
williamr@4: 	EGpt3,
williamr@4: 	EGpt4,
williamr@4: 	EGpt5,
williamr@4: 	EGpt6,
williamr@4: 	EGpt7,
williamr@4: 	EGpt8,
williamr@4: 	EGpt9, 
williamr@4: 	EGpt10,
williamr@4: 	EGpt11,
williamr@4: 	EGpt12,
williamr@4: 
williamr@4: 	KSupportedGptCount
williamr@4: 	};
williamr@4: 
williamr@4: /** Enumeration of supported PLLs */
williamr@4: enum TPll
williamr@4: 	{
williamr@4: 	EDpll1,
williamr@4: 	EDpll2,
williamr@4: 	EDpll3,
williamr@4: 	EDpll4,
williamr@4: 	EDpll5,
williamr@4: 
williamr@4: 	KSupportedPllCount
williamr@4: 	};
williamr@4: 
williamr@4: enum TGptClockSource
williamr@4: 	{
williamr@4: 	EGptClockSysClk,
williamr@4: 	EGptClock32k
williamr@4: 	};
williamr@4: 
williamr@4: enum TClockState
williamr@4: 	{
williamr@4: 	EClkOff,		///< clock is disabled
williamr@4: 	EClkOn,		///< clock is enabled
williamr@4: 	EClkAuto		///< clock is in auto mode (enabled when required)
williamr@4: 	};
williamr@4: 
williamr@4: enum TWakeupMode
williamr@4: 	{
williamr@4: 	EWakeupDisabled,
williamr@4: 	EWakeupEnabled,
williamr@4: 	};
williamr@4: 
williamr@4: enum TLpMode
williamr@4: 	{
williamr@4: 	ENormalMode,
williamr@4: 	ELpMode
williamr@4: 	};
williamr@4: 
williamr@4: enum TPowerSaveMode
williamr@4: 	{
williamr@4: 	EPowerSaveOff,
williamr@4: 	EPowerSaveIdle,
williamr@4: 	EPowerSaveStandby
williamr@4: 	};
williamr@4: 
williamr@4: enum TPllMode
williamr@4: 	{
williamr@4: 	EPllStop,
williamr@4: 	EPllBypass,
williamr@4: 	EPllRun,
williamr@4: 	EPllFastRelock,
williamr@4: 	EPllAuto
williamr@4: 	};
williamr@4: 
williamr@4: enum TBypassDivider
williamr@4: 	{
williamr@4: 	EBypassDiv1,
williamr@4: 	EBypassDiv2,
williamr@4: 	EBypassDiv4
williamr@4: 	};
williamr@4: 
williamr@4: enum TPowerDomainMode
williamr@4: 	{
williamr@4: 	EPowerOff,
williamr@4: 	EPowerRetention,
williamr@4: 	EPowerReserved,
williamr@4: 	EPowerOn,
williamr@4: 	};
williamr@4: 
williamr@4: enum TPowerDomain
williamr@4: 	{
williamr@4: 	EPowerDomainMpu,
williamr@4: 	EPowerDomainIva2,
williamr@4: 	EPowerDomainNeon,
williamr@4: 	EPowerDomainCore,
williamr@4: 	EPowerDomainSgx,
williamr@4: 	EPowerDomainDss,
williamr@4: 	EPowerDomainCamera,
williamr@4: 	EPowerDomainUsb,
williamr@4: 	EPowerDomainPer,
williamr@4: 
williamr@4: 	KSupportedPowerDomainCount
williamr@4: 	};
williamr@4: 
williamr@4: enum TWakeupDomain
williamr@4: 	{
williamr@4: 	EWakeDomainMpu,
williamr@4: 	EWakeDomainCore,
williamr@4: 	EWakeDomainIva2,
williamr@4: 	EWakeDomainPeripheral,
williamr@4: 	EWakeDomainDss,
williamr@4: 	EWakeDomainWakeup,
williamr@4: 
williamr@4: 	KSupportedWakeupDomainCount
williamr@4: 	};
williamr@4: 
williamr@4: enum TWakeupGroup
williamr@4: 	{
williamr@4: 	EWakeGroupMpu,
williamr@4: 	EWakeGroupIva2,
williamr@4: 
williamr@4: 	KSupportedWakeupGroupCount
williamr@4: 	};
williamr@4: 
williamr@4: /** Indicates how to handle a request to set a clock frequency */
williamr@4: enum TClockRoundMode
williamr@4: 	{
williamr@4: 	EExactOnly,		///< only set clock if requested frequency can be set exactly
williamr@4: 	ENearest,		///< always set clock to nearest possible frequency higher or lower than requested
williamr@4: 	ENearestLower,	///< set to nearest frequency <=requested, fail if no frequency <= requested is possible
williamr@4: 	ENearestHigher,	///< set to nearest frequency >=requested, fail if no frequency >= requested is possible
williamr@4: 	};
williamr@4: 
williamr@4: /** Enumeration of valid Pll frequency ranges */
williamr@4: enum TPllFrequencyRange
williamr@4: 	{
williamr@4: 	EPllRange_075_100		= 0x3,	///<	0.75 - 1.0 MHz
williamr@4: 	EPllRange_100_125		= 0x4,	///<	<1.0 MHz - 1.25 MHz
williamr@4: 	EPllRange_125_150		= 0x5,	///<	<1.25 MHz - 1.5 MHz
williamr@4: 	EPllRange_150_175		= 0x6,	///<	<1.5 MHz - 1.75 MHz
williamr@4: 	EPllRange_175_210		= 0x7,	///<	<1.75 MHz - 2.1 MHz
williamr@4: 	EPllRange_750_1000		= 0xB,	///<	<7.5 MHz - 10 MHz
williamr@4: 	EPllRange_1000_1250		= 0xC,	///<	<10 MHz - 12.5 MHz
williamr@4: 	EPllRange_1250_1500		= 0xD,	///<	<12.5 MHz - 15 MHz
williamr@4: 	EPllRange_1500_1750		= 0xE,	///<	<15 MHz - 17.5 MHz
williamr@4: 	EPllRange_1750_2100		= 0xF	///<	<17.5 MHz - 21 MHz
williamr@4: 	};
williamr@4: 
williamr@4: /** Enumeration of valid PLL ramp settings */
williamr@4: enum TPllRamp
williamr@4: 	{
williamr@4: 	EPllRampDisabled = 0x0,
williamr@4: 	EPllRamp4us		= 0x1,
williamr@4: 	EPllRam20us		= 0x2,
williamr@4: 	EPllRamp40us	= 0x3
williamr@4: 	};
williamr@4: 
williamr@4: /** Enumeration of vali PLL driftguard settings */
williamr@4: enum TPllDrift
williamr@4: 	{
williamr@4: 	EPllDriftGuardDisabled,
williamr@4: 	EPllDriftGuardEnabled
williamr@4: 	};
williamr@4: 
williamr@4: /** Structure containing configuration for a PLL */
williamr@4: struct TPllConfiguration
williamr@4: 	{
williamr@4: 	TUint		iMultiplier;		///< Multiple value
williamr@4: 	TUint		iDivider;			///< Divider value (this is actual divider, hardware is programmed with iDivider-1)
williamr@4: 	TPllFrequencyRange	iFreqRange : 8;
williamr@4: 	TPllRamp	iRamp : 8;
williamr@4: 	TPllDrift	iDrift : 8;
williamr@4: 	TUint8		__spare;
williamr@4: 	};
williamr@4: 
williamr@4: /** Enumeration of supported SysClk frequency configurations */
williamr@4: enum TSysClkFrequency
williamr@4: 	{
williamr@4: 	ESysClk12MHz,
williamr@4: 	ESysClk13MHz,
williamr@4: 	ESysClk16_8MHz,
williamr@4: 	ESysClk19_2MHz,
williamr@4: 	ESysClk26MHz,
williamr@4: 	ESysClk38_4MHz
williamr@4: 	};
williamr@4: 
williamr@4: // called during start-up
williamr@4: IMPORT_C void Init3(); // PRCM (disable every peripheral leaving DSS (and UART3 in debug) running)
williamr@4: 
williamr@4: IMPORT_C void SetPllConfig( TPll aPll, const TPllConfiguration& aConfig  );
williamr@4: IMPORT_C void PllConfig( TPll aPll, TPllConfiguration& aConfigResult );
williamr@4: 
williamr@4: 
williamr@4: /** Configure PLL frequency */
williamr@4: IMPORT_C void SetPllMode( TPll aPll, TPllMode aPllMode );
williamr@4: 
williamr@4: /** Return PLL frequency configuration */
williamr@4: IMPORT_C TPllMode PllMode( TPll aPll );
williamr@4: 
williamr@4: /** Test whether a PLL is locked */
williamr@4: IMPORT_C TBool PllIsLocked( TPll aPll );
williamr@4: 
williamr@4: /** Wait for a PLL to lock */
williamr@4: IMPORT_C void WaitForPllLock( TPll aPll );
williamr@4: 
williamr@4: /** Calculate the correct FreqRange setting for the given pll
williamr@4:  * Updates the iFreqRange parameter of the given TPllConfiguration
williamr@4:  */
williamr@4: IMPORT_C void CalcPllFrequencyRange( TPll aPll, TPllConfiguration& aConfig );
williamr@4: 
williamr@4: /** Enable LP mode on a DLL if it is within LP frequency range */
williamr@4: IMPORT_C void AutoSetPllLpMode( TPll aPll );
williamr@4: 
williamr@4: /** Enable or disable PLL LP mode */
williamr@4: IMPORT_C void SetPllLp( TPll aPll, TLpMode aLpMode );
williamr@4: 
williamr@4: /** Get LP mode setting for a PLL */
williamr@4: IMPORT_C TLpMode PllLp( TPll aPll );
williamr@4: 
williamr@4: /** Set the bypass divider for a PLL */
williamr@4: IMPORT_C void SetPllBypassDivider( TPll aPll, TBypassDivider aDivider );
williamr@4: 
williamr@4: /** Get the current bypass divider for a PLL */
williamr@4: IMPORT_C TBypassDivider PllBypassDivider( TPll aPll );
williamr@4: 
williamr@4: /** Set the divider value for the given clock 
williamr@4:  * aDivider is the required divide value - e.g. to divide by 4
williamr@4:  * aDivider=4.
williamr@4:  *
williamr@4:  * Note that not all clocks support division by any number, and
williamr@4:  * only some clocks have a divider. Attempting to set a divider
williamr@4:  * on a clock without a divider will have no effect in UREL and
williamr@4:  * will panic in UDEB with ESetDividerUnsupportedClock.
williamr@4:  * Attempting to set a divider value not supported by the clock
williamr@4:  * will have no effect in UREL and will panic in UDEB with
williamr@4:  * ESetDividerBadDivider.
williamr@4:  *
williamr@4:  * Note 1: for EClkSgx_F the value valued of aDivide are 0, 3, 4, 6.
williamr@4:  * 0 sets the clock to be the 96MHz clock
williamr@4:  * 3, 4, 6 set it to be CORE_CLK divided by 3, 4, or 6
williamr@4:  *
williamr@4:  * Note 2: you cannot use this function to set EClkUsim_F, use
williamr@4:  * SetUsimClockDivider().
williamr@4:  */
williamr@4: IMPORT_C void SetDivider( TClock aClock, TUint aDivide );
williamr@4: 
williamr@4: /** Get the current divider value of the given clock */
williamr@4: IMPORT_C TUint Divider( TClock aClock );
williamr@4: 
williamr@4: //IMPORT_C void SetUsimClockDivider( TUint TUsimDivideMode aMode );
williamr@4: //IMPORT_C TUsimDivideMode UsimClockDivider();
williamr@4: 
williamr@4: /** Controls power to a power domain */
williamr@4: IMPORT_C void SetPowerDomainMode( TPowerDomain aDomain, TPowerDomainMode aMode );
williamr@4: 
williamr@4: /** Gets the current mode of a power domain power control */
williamr@4: IMPORT_C TPowerDomainMode PowerDomainMode( TPowerDomain aDomain );
williamr@4: 
williamr@4: //IMPORT_C void SetPowerSaveMode( TClock aClock, TPowerSaveMode aMode );
williamr@4: //IMPORT_C TPowerSaveMode PowerSaveMode( TClock aClock );
williamr@4: 
williamr@4: //IMPORT_C TBool DomainClockActive( TClock aClock );
williamr@4: 
williamr@4: // Set clock enable/disable
williamr@4: /** Set the clock state of a given clock */
williamr@4: IMPORT_C void SetClockState( TClock aClock, TClockState aState );
williamr@4: 
williamr@4: /** Get the configured clock state of a given clock */
williamr@4: IMPORT_C TClockState ClockState( TClock aClock );
williamr@4: 
williamr@4: // Configure wakeup mode for clocks
williamr@4: /** Configure wakeup mode for a clock
williamr@4:  * Note - for peripheral blocks with an interface and functional clock, it is
williamr@4:  * the interface clock which is configured for wakeup. Attempting to configure
williamr@4:  * wakeup on the functional clock has no effect
williamr@4:  */
williamr@4: IMPORT_C void SetWakeupMode( TClock aClock, TWakeupMode aMode );
williamr@4: 
williamr@4: /** Get configured wakeup mode for a clock */
williamr@4: IMPORT_C TWakeupMode WakeupMode( TClock aClock );
williamr@4: 
williamr@4: /** Add a peripheral interface clock to the specified wakeup group */
williamr@4: IMPORT_C void AddToWakeupGroup( TClock aClock, TWakeupGroup aGroup );
williamr@4: 
williamr@4: /** Remove a peripheral interface clock from the specified wakeup group */
williamr@4: IMPORT_C void RemoveFromWakeupGroup( TClock aClock, TWakeupGroup aGroup );
williamr@4: 
williamr@4: /** Test whether a peripheral interface clock is in the specified wakeup group */
williamr@4: IMPORT_C TBool IsInWakeupGroup( TClock aClock, TWakeupGroup aGroup );
williamr@4: 
williamr@4: /** Add a clock to the given wakeup domain */
williamr@4: IMPORT_C void AddToWakeupDomain( TClock aClock, TWakeupDomain aDomain );
williamr@4: 
williamr@4: /** Remove a clock from the given wakeup domain */
williamr@4: IMPORT_C void RemoveFromWakeupDomain( TClock aClock, TWakeupDomain aDomain );
williamr@4: 
williamr@4: /** Test whether a clock is in the specified wakeup domain */
williamr@4: IMPORT_C TBool IsInWakeupDomain( TClock aClock, TWakeupDomain aDomain );
williamr@4: 
williamr@4: 
williamr@4: // Functions for configuring clock sources
williamr@4: 
williamr@4: /** Set the clock source for a GPT timer */
williamr@4: IMPORT_C void SetGptClockSource( TGpt aGpt, TGptClockSource aSource );
williamr@4: 
williamr@4: /** Get the current clock source of a GPT */
williamr@4: IMPORT_C TGptClockSource GptClockSource( TGpt aGpt );
williamr@4: 
williamr@4: /** Get the USIM divider factor */
williamr@4: IMPORT_C TUint UsimDivider();
williamr@4: 
williamr@4: /** Get the USIM source clock */
williamr@4: IMPORT_C TClock UsimClockSource();
williamr@4: 
williamr@4: /** Sets the current input clock into the clock mux for the specified clock
williamr@4:  * aClock must refer to a clock that has a mux for selecting input clock
williamr@4:  * and aSource must be a possible input clock for aClock
williamr@4:  */
williamr@4: IMPORT_C void SetClockMux( TClock aClock, TClock aSource );
williamr@4: 
williamr@4: 
williamr@4: /** Gets the current input clock into the clock mux for the specified clock
williamr@4:  * aClock must refer to a clock that has a mux for selecting input clock
williamr@4:  */
williamr@4: IMPORT_C TClock ClockMux( TClock aClock );
williamr@4: 
williamr@4: /** Get the currently configured frequency of the specified clock
williamr@4:  * Note that this is regardless of whether the clock is currently running.
williamr@4:  * That is, if a clock is configured to run at 8MHz, then this function
williamr@4:  * will return 8000000 whether the clock is currently enabled or disabled.
williamr@4:  *
williamr@4:  * @param	aClock	clock required
williamr@4:  * @return	Frequency in Hz
williamr@4:  */
williamr@4: IMPORT_C TUint ClockFrequency( TClock aClock );
williamr@4: 
williamr@4: /** Set the correct SysClock frequency */
williamr@4: IMPORT_C void SetSysClkFrequency( TSysClkFrequency aFrequency );
williamr@4: 
williamr@4: /** Get the currently configured SysClk frequency */
williamr@4: IMPORT_C TSysClkFrequency SysClkFrequency();
williamr@4: 
williamr@4: /** Function to get the name to be passed to the Power Resource Manager
williamr@4:  * to refer to the given clock source
williamr@4:  */
williamr@4: IMPORT_C const TDesC& PrmName( TClock aClock );
williamr@4: 
williamr@4: }
williamr@4: 
williamr@4: #endif // !defined PRCM_H__