williamr@4: // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
williamr@4: // All rights reserved.
williamr@4: // This component and the accompanying materials are made available
williamr@4: // under the terms of the License "Eclipse Public License v1.0"
williamr@4: // which accompanies this distribution, and is available
williamr@4: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
williamr@4: //
williamr@4: // Initial Contributors:
williamr@4: // Nokia Corporation - initial contribution.
williamr@4: //
williamr@4: // Contributors:
williamr@4: //
williamr@4: // Description:
williamr@4: // omap3530/assp/inc/omap3530_irqmap.h
williamr@4: //
williamr@4: 
williamr@4: #ifndef OMAP3530_IRQMAP_H
williamr@4: #define OMAP3530_IRQMAP_H
williamr@4: 
williamr@4: #include <assp/omap3530_assp/omap3530_hardware_base.h>
williamr@4: 
williamr@4: 										   
williamr@4: #define INTCPS_BASE 			Omap3530HwBase::KL4_Core +   0x200000 
williamr@4: #define INTCPS_SYSCONFIG  		INTCPS_BASE + 0x10 
williamr@4: #define INTCPS_SYSSTATUS  		INTCPS_BASE + 0x14
williamr@4: #define INTCPS_PROTECTION		INTCPS_BASE + 0x4c
williamr@4: #define INTCPS_IRQ_PRIORITY		INTCPS_BASE + 0x60
williamr@4: #define INTCPS_FIQ_PRIORITY		INTCPS_BASE + 0x64
williamr@4: 
williamr@4: 
williamr@4: #define INTCPS_ITR(n)			(INTCPS_BASE +  0x80  +( 0x20 *n))
williamr@4: #define INTCPS_THRESHOLD		INTCPS_BASE + 0x64
williamr@4: #define INTCPS_IDLE 			INTCPS_BASE + 0x50
williamr@4: //#define INTC_INIT_REGISTER1 	0x470C8010
williamr@4: //#define INTC_INIT_REGISTER2 	0x470C8050 
williamr@4: #define INTCPS_ILRM(n)			(INTCPS_BASE + 0x100 +(0x04 *n))
williamr@4: 
williamr@4: //current interrupt vector & clear regs
williamr@4: #define INTCPS_SIR_IRQ			INTCPS_BASE + 0x40
williamr@4: #define INTCPS_SIR_FIQ			INTCPS_BASE + 0x44
williamr@4: #define INTCPS_CONTROL			INTCPS_BASE + 0x48
williamr@4: 
williamr@4: 
williamr@4: #define INTCPS_PENDING_IRQ(n)	(INTCPS_BASE + 0x98 + (0x20 * n))
williamr@4: #define INTCPS_PENDING_FIQ(n)	(INTCPS_BASE + 0x9c + (0x20 * n))
williamr@4: //masks on /off 
williamr@4: #define INTCPS_MIRn(n)			(INTCPS_BASE + 0x084 + (n *0x20))
williamr@4: #define INTCPS_MIR_SETn(n)		(INTCPS_BASE + 0x08c + (n * 0x20))
williamr@4: #define INTCPS_MIR_CLEARn(n)	(INTCPS_BASE + 0x088 + (n *0x20))
williamr@4: 
williamr@4: 
williamr@4: #define INTCPS_ISRSET(n) 		(INTCPS_BASE + 0x090 + (n *0x20))
williamr@4: #define INTCPS_ISR_CLEAR(n)		(INTCPS_BASE + 0x094 + (n *0x20))
williamr@4: 
williamr@4: //regvals
williamr@4: #define INTCPS_SYSCONFIG_AUTOIDLE 	0x1
williamr@4: #define INTCPS_IDLE_FUNCIDLE		0x0
williamr@4: #define INTCPS_IDLE_TURBO			0x1
williamr@4: #define INTCPS_ILRM_DEF_PRI			(0x1 <<2)
williamr@4: #define INTCPS_ILRM_ROUTE_FIQ		0x1
williamr@4: #define INTCPS_ILRM_ROUTE_IRQ       0x00
williamr@4: #define INTCPS_MIR_ALL_UNSET		0x00000000
williamr@4: #define INTCPS_MIR_ALL_SET			0xffffffff
williamr@4: 
williamr@4: #define INTCPS_CONTROL_IRQ_CLEAR	0x1
williamr@4: #define INTCPS_CONTROL_FIQ_CLEAR    (0x1 << 1)
williamr@4: #define INTCPS_INIT_RG_LOW_PWR		0x1			
williamr@4: #define INTCPS_PENDING_MASK			0x7f
williamr@4: 
williamr@4: 
williamr@4: 
williamr@4: // Base of each interrupt range supported within the ASSP layer
williamr@4: // Used to index the correct interrupt handler object
williamr@4: enum TIrqRangeIndex
williamr@4: 	{
williamr@4: 	EIrqRangeBaseCore,	// main interrupt controller
williamr@4: 	EIrqRangeBasePrcm,	// PRCM sub-controller interrupt sources
williamr@4: 	EIrqRangeBaseGpio,	// GPIO sub-controller interrupt sources
williamr@4: 	EIrqRangeBasePsu,	// Place-holder for off-board PSU device, reserved here because
williamr@4: 						// we know there will always be one  (probably a TPD65950 or similar)
williamr@4: 
williamr@4: 	KIrqRangeCount
williamr@4: 	};
williamr@4: 
williamr@4: const TInt	KIrqRangeIndexShift		= 16;
williamr@4: const TInt	KIrqNumberMask			= 0xFFFF;
williamr@4: 
williamr@4: /** Class defining an interrupt dispatcher */
williamr@4: class MInterruptDispatcher
williamr@4: 	{
williamr@4: 	public:
williamr@4: 		IMPORT_C void Register( TIrqRangeIndex aIndex );
williamr@4: 		
williamr@4: 		virtual TInt Bind(TInt aId, TIsr aIsr, TAny* aPtr) = 0;
williamr@4: 		virtual TInt Unbind(TInt aId) = 0;
williamr@4: 		virtual TInt Enable(TInt aId) = 0;
williamr@4: 		virtual TInt Disable(TInt aId) = 0;
williamr@4: 		virtual TInt Clear(TInt aId) = 0;
williamr@4: 		virtual TInt SetPriority(TInt aId, TInt aPriority) = 0;
williamr@4: 	};
williamr@4: 
williamr@4: /*
williamr@4: (1) All the IRQ signals are active at low level.
williamr@4: (2) These interrupts are internally generated within the MPU subsystem.
williamr@4: 
williamr@4: Table 10-4. Interrupt Mapping to the MPU Subsystem (continued)
williamr@4: */
williamr@4: enum TOmap3530_IRQ {
williamr@4: 
williamr@4: 	EOmap3530_IRQ0_EMUINT = (EIrqRangeBaseCore << KIrqRangeIndexShift),  				//MPU emulation(2)
williamr@4: 	EOmap3530_IRQ1_COMMTX, 					//MPU emulation(2)
williamr@4: 	EOmap3530_IRQ2_COMMRX, 					//MPU emulation(2)
williamr@4: 	EOmap3530_IRQ3_BENCH, 					//MPU emulation(2)
williamr@4: 	EOmap3530_IRQ4_MCBSP2_ST_IRQ, 			//Sidetone MCBSP2 overflow
williamr@4: 	EOmap3530_IRQ5_MCBSP3_ST_IRQ, 			//Sidetone MCBSP3 overflow
williamr@4: 	EOmap3530_IRQ6_SSM_ABORT_IRQ, 			//MPU subsystem secure state-machine abort (2)
williamr@4: 	EOmap3530_IRQ7_SYS_NIRQ, 				//External source (active low)
williamr@4: 	EOmap3530_IRQ8_RESERVED, 				//RESERVED
williamr@4: 	EOmap3530_IRQ9_SMX_DBG_IRQ, 			//SMX error for debug
williamr@4: 	EOmap3530_IRQ10_SMX_APP_IRQ, 			//SMX error for application
williamr@4: 	EOmap3530_IRQ11_PRCM_MPU_IRQ, 			//PRCM module IRQ
williamr@4: 	EOmap3530_IRQ12_SDMA_IRQ0, 				//System DMA request 0(3)
williamr@4: 	EOmap3530_IRQ13_SDMA_IRQ1, 				//System DMA request 1(3)
williamr@4: 	EOmap3530_IRQ14_SDMA_IRQ2, 				//System DMA request 2
williamr@4: 	EOmap3530_IRQ15_SDMA_IRQ3, 				//System DMA request 3
williamr@4: 	EOmap3530_IRQ16_MCBSP1_IRQ, 			//McBSP module 1 IRQ (3)
williamr@4: 	EOmap3530_IRQ17_MCBSP2_IRQ, 			//McBSP module 2 IRQ (3)
williamr@4: 	EOmap3530_IRQ18_SR1_IRQ, 				//SmartReflex™ 1
williamr@4: 	EOmap3530_IRQ19_SR2_IRQ, 				//SmartReflex™ 2
williamr@4: 	EOmap3530_IRQ20_GPMC_IRQ, 				//General-purpose memory controller module
williamr@4: 	EOmap3530_IRQ21_SGX_IRQ, 				//2D/3D graphics module
williamr@4: 	EOmap3530_IRQ22_MCBSP3_IRQ, 			//McBSP module 3(3)
williamr@4: 	EOmap3530_IRQ23_MCBSP4_IRQ, 			//McBSP module 4(3)
williamr@4: 	EOmap3530_IRQ24_CAEM_IRQ0, 				//Camera interface request 0
williamr@4: 	EOmap3530_IRQ25_DSS_IRQ, 				//Display subsystem module(3)
williamr@4: 	EOmap3530_IRQ26_MAIL_U0_MPU_IRQ, 		//Mailbox user 0 request
williamr@4: 	EOmap3530_IRQ27_MCBSP5_IRQ, 			//McBSP module 5 (3)
williamr@4: 	EOmap3530_IRQ28_IVA2_MMU_IRQ, 			//IVA2 MMU
williamr@4: 	EOmap3530_IRQ29_GPIO1_MPU_IRQ, 			//GPIO module 1(3)
williamr@4: 	EOmap3530_IRQ30_GPIO2_MPU_IRQ, 			//GPIO module 2(3)
williamr@4: 	EOmap3530_IRQ31_GPIO3_MPU_IRQ, 			//GPIO module 3(3)
williamr@4: 	EOmap3530_IRQ32_GPIO4_MPU_IRQ, 			//GPIO module 4(3)
williamr@4: 	EOmap3530_IRQ33_GPIO5_MPU_IRQ, 			//GPIO module 5(3)
williamr@4: 	EOmap3530_IRQ34_GPIO6_MPU_IRQ, 			//GPIO module 6(3)
williamr@4: 	EOmap3530_IRQ35_USIEM_IRQ,		 		//USIM interrupt (HS devices only) (4)
williamr@4: 	EOmap3530_IRQ36_WDT3_IRQ, 				//Watchdog timer module 3 overflow
williamr@4: 	EOmap3530_IRQ37_GPT1_IRQ, 				//General-purpose timer module 1
williamr@4: 	EOmap3530_IRQ38_GPT2_IRQ, 				//General-purpose timer module 2
williamr@4: 	EOmap3530_IRQ39_GPT3_IRQ, 				//General-purpose timer module 3
williamr@4: 	EOmap3530_IRQ40_GPT4_IRQ, 				//General-purpose timer module 4
williamr@4: 	EOmap3530_IRQ41_GPT5_IRQ, 				//General-purpose timer module 5(3)
williamr@4: 	EOmap3530_IRQ42_GPT6_IRQ, 				//General-purpose timer module 6(3)
williamr@4: 	EOmap3530_IRQ43_GPT7_IRQ, 				//General-purpose timer module 7(3)
williamr@4: 	EOmap3530_IRQ44_GPT8_IRQ, 				//General-purpose timer module 8(3)
williamr@4: 	EOmap3530_IRQ45_GPT9_IRQ, 				//General-purpose timer module 9
williamr@4: 	EOmap3530_IRQ46_GPT10_IRQ, 				//General-purpose timer module 10
williamr@4: 	EOmap3530_IRQ47_GPT11_IRQ, 				//General-purpose timer module 11
williamr@4: 	EOmap3530_IRQ48_SPI4_IRQ, 				//McSPI module 4
williamr@4: 	EOmap3530_IRQ49_SHA1MD5_IRQ2, 			//SHA-1/MD5 crypto-accelerator 2 (HS devices only)(4)
williamr@4: 	EOmap3530_IRQ50_FPKA_IRQREADY_N, 		//PKA crypto-accelerator (HS devices only) (4)
williamr@4: 	EOmap3530_IRQ51_SHA2MD5_IRQ, 			//SHA-2/MD5 crypto-accelerator 1 (HS devices only) (4)
williamr@4: 	EOmap3530_IRQ52_RNG_IRQ, 				//RNG module (HS devices only) (4)
williamr@4: 	EOmap3530_IRQ53_MG_IRQ, 				//MG function (3)
williamr@4: 	EOmap3530_IRQ54_MCBSP4_IRQTX, 			//McBSP module 4 transmit(3)
williamr@4: 	EOmap3530_IRQ55_MCBSP4_IRQRX, 			//McBSP module 4 receive(3)
williamr@4: 	EOmap3530_IRQ56_I2C1_IRQ, 				//I2C module 1
williamr@4: 	EOmap3530_IRQ57_I2C2_IRQ, 				//I2C module 2
williamr@4: 	EOmap3530_IRQ58_HDQ_IRQ, 				//HDQ/One-wire
williamr@4: 	EOmap3530_IRQ59_McBSP1_IRQTX, 			//McBSP module 1 transmit(3)
williamr@4: 	EOmap3530_IRQ60_McBSP1_IRQRX, 			//McBSP module 1 receive(3)
williamr@4: 	EOmap3530_IRQ61_I2C3_IRQ, 				//I2C module 3
williamr@4: 	EOmap3530_IRQ62_McBSP2_IRQTX, 			//McBSP module 2 transmit(3)
williamr@4: 	EOmap3530_IRQ63_McBSP2_IRQRX, 			//McBSP module 2 receive(3)
williamr@4: 	EOmap3530_IRQ64_FPKA_IRQRERROR_N, 		//PKA crypto-accelerator (HS devices only) (4)
williamr@4: 	EOmap3530_IRQ65_SPI1_IRQ, 				//McSPI module 1
williamr@4: 	EOmap3530_IRQ66_SPI2_IRQ, 				//McSPI module 2
williamr@4: 	EOmap3530_IRQ67_RESERVED, 				//RESERVED
williamr@4: 	EOmap3530_IRQ68_RESERVED, 				//RESERVED
williamr@4: 	EOmap3530_IRQ69_RESERVED, 				//RESERVED
williamr@4: 	EOmap3530_IRQ70_RESERVED, 				//RESERVED
williamr@4: 	EOmap3530_IRQ71_RESERVED, 				//RESERVED
williamr@4: 	EOmap3530_IRQ72_UART1_IRQ, 				//UART module 1
williamr@4: 	EOmap3530_IRQ73_UART2_IRQ, 				//UART module 2
williamr@4: 	EOmap3530_IRQ74_UART3_IRQ, 				//UART module 3 (also infrared)(3)
williamr@4: 	EOmap3530_IRQ75_PBIAS_IRQ, 				//Merged interrupt for PBIASlite1 and 2
williamr@4: 	EOmap3530_IRQ76_OHCI_IRQ, 				//OHCI controller HSUSB MP Host Interrupt
williamr@4: 	EOmap3530_IRQ77_EHCI_IRQ, 				//EHCI controller HSUSB MP Host Interrupt
williamr@4: 	EOmap3530_IRQ78_TLL_IRQ, 				//HSUSB MP TLL Interrupt
williamr@4: 	EOmap3530_IRQ79_PARTHASH_IRQ, 			//SHA2/MD5 crypto-accelerator 1 (HS devices only) (4)
williamr@4: 	EOmap3530_IRQ80_RESERVED, 				//Reserved
williamr@4: 	EOmap3530_IRQ81_MCBSP5_IRQTX, 			//McBSP module 5 transmit(3)
williamr@4: 	EOmap3530_IRQ82_MCBSP5_IRQRX, 			//McBSP module 5 receive(3)
williamr@4: 	EOmap3530_IRQ83_MMC1_IRQ, 				//MMC/SD module 1
williamr@4: 	EOmap3530_IRQ84_MS_IRQ, 				//MS-PRO module
williamr@4: 	EOmap3530_IRQ85_RESERVED, 				//Reserved
williamr@4: 	EOmap3530_IRQ86_MMC2_IRQ, 				//MMC/SD module 2
williamr@4: 	EOmap3530_IRQ87_MPU_ICR_IRQ, 			//MPU ICR
williamr@4: 	EOmap3530_IRQ88_RESERVED, 				//RESERVED
williamr@4: 	EOmap3530_IRQ89_MCBSP3_IRQTX, 			//McBSP module 3 transmit(3)
williamr@4: 	EOmap3530_IRQ90_MCBSP3_IRQRX, 			//McBSP module 3 receive(3)
williamr@4: 	EOmap3530_IRQ91_SPI3_IRQ, 				//McSPI module 3
williamr@4: 	EOmap3530_IRQ92_HSUSB_MC_NINT, 			//High-Speed USB OTG controller
williamr@4: 	EOmap3530_IRQ93_HSUSB_DMA_NINT, 		//High-Speed USB OTG DMA controller
williamr@4: 	EOmap3530_IRQ94_MMC3_IRQ, 				//MMC/SD module 3
williamr@4: 	EOmap3530_IRQ95_GPT12_IRQ, 				//General-purpose timer module 12
williamr@4: 
williamr@4: // IRQ virtual IDs
williamr@4: 	EOmap3530_GPIOIRQ_FIRST,
williamr@4: 
williamr@4: 	EOmap3530_GPIOIRQ_PIN_0,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_1,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_2,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_3,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_4,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_5,	
williamr@4: 	EOmap3530_GPIOIRQ_PIN_6,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_7,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_8,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_9,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_10,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_11,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_12,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_13,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_14,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_15,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_16,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_17,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_18,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_19,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_20,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_21,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_22,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_23,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_24,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_25,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_26,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_27,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_28,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_29,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_30,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_31,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_32,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_33,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_34,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_35,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_36,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_37,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_38,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_39,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_40,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_41,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_42,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_43,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_44,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_45,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_46,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_47,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_48,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_49,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_50,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_51,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_52,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_53,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_54,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_55,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_56,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_57,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_58,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_59,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_60,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_61,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_62,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_63,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_64,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_65,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_66,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_67,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_68,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_69,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_70,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_71,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_72,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_73,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_74,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_75,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_76,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_77,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_78,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_79,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_80,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_81,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_82,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_83,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_84,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_85,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_86,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_87,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_88,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_89,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_90,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_91,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_92,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_93,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_94,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_95,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_96,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_97,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_98,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_99,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_100,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_101,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_102,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_103,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_104,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_105,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_106,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_107,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_108,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_109,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_110,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_111,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_112,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_113,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_114,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_115,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_116,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_117,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_118,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_119,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_120,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_121,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_122,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_123,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_124,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_125,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_126,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_127,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_128,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_129,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_130,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_131,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_132,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_133,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_134,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_135,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_136,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_137,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_138,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_139,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_140,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_141,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_142,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_143,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_144,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_145,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_146,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_147,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_148,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_149,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_150,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_151,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_152,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_153,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_154,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_155,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_156,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_157,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_158,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_159,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_160,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_161,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_162,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_163,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_164,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_165,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_166,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_167,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_168,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_169,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_170,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_171,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_172,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_173,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_174,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_175,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_176,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_177,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_178,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_179,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_180,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_181,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_182,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_183,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_184,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_185,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_186,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_187,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_188,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_189,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_190,
williamr@4: 	EOmap3530_GPIOIRQ_PIN_191,
williamr@4: 	
williamr@4: 	EOmap3530_GPIOIRQ_TOTAL,
williamr@4: 
williamr@4: 	EOmap3530_TOTAL_IRQS
williamr@4: };
williamr@4: 
williamr@4: 
williamr@4: 
williamr@4: const TInt KNumOmap3530Ints = (EOmap3530_GPIOIRQ_FIRST -1);
williamr@4: 
williamr@4: const TInt KOmap3530MaxIntPriority =0;
williamr@4: const TInt KOmap3530MinIntPriority =63;
williamr@4: const TInt KOmap3530DefIntPriority =KOmap3530MinIntPriority /2;
williamr@4: IMPORT_C void ClearAndDisableTestInterrupt(TInt anId);
williamr@4: IMPORT_C void TestInterrupts(TInt id,TIsr func);
williamr@4: 
williamr@4: 
williamr@4: #endif /*Omap3530_IRQMAP_H*/