williamr@4: // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). williamr@4: // All rights reserved. williamr@4: // This component and the accompanying materials are made available williamr@4: // under the terms of the License "Eclipse Public License v1.0" williamr@4: // which accompanies this distribution, and is available williamr@4: // at the URL "http://www.eclipse.org/legal/epl-v10.html". williamr@4: // williamr@4: // Initial Contributors: williamr@4: // Nokia Corporation - initial contribution. williamr@4: // williamr@4: // Contributors: williamr@4: // williamr@4: // Description: williamr@4: // omap3530/omap3530_drivers/gpio/omap3530_gpio.h williamr@4: // This file is part of the Beagle Base port williamr@4: // williamr@4: williamr@4: #ifndef __OMAP3530_GPIO_H__ williamr@4: #define __OMAP3530_GPIO_H__ williamr@4: williamr@4: #include williamr@4: #include williamr@4: //#include williamr@4: williamr@4: #include williamr@4: #include williamr@4: williamr@4: const TUint KGPIO1 = Omap3530HwBase::TVirtual<0x48310000>::Value; williamr@4: const TUint KGPIO2 = Omap3530HwBase::TVirtual<0x49050000>::Value; williamr@4: const TUint KGPIO3 = Omap3530HwBase::TVirtual<0x49052000>::Value; williamr@4: const TUint KGPIO4 = Omap3530HwBase::TVirtual<0x49054000>::Value; williamr@4: const TUint KGPIO5 = Omap3530HwBase::TVirtual<0x49056000>::Value; williamr@4: const TUint KGPIO6 = Omap3530HwBase::TVirtual<0x49058000>::Value; williamr@4: williamr@4: williamr@4: const TUint KGPIO_REVISION = 0x000; williamr@4: const TUint KGPIO_SYSCONFIG = 0x010; williamr@4: const TUint KGPIO_SYSSTATUS = 0x014; williamr@4: const TUint KGPIO_IRQSTATUS1 = 0x018; williamr@4: const TUint KGPIO_IRQENABLE1 = 0x01C; williamr@4: const TUint KGPIO_WAKEUPENABLE = 0x020; williamr@4: const TUint KGPIO_IRQSTATUS2 = 0x028; williamr@4: const TUint KGPIO_IRQENABLE2 = 0x02C; williamr@4: const TUint KGPIO_CTRL = 0x030; williamr@4: const TUint KGPIO_OE = 0x034; williamr@4: const TUint KGPIO_DATAIN = 0x038; williamr@4: const TUint KGPIO_DATAOUT = 0x03C; williamr@4: const TUint KGPIO_LEVELDETECT0 = 0x040; williamr@4: const TUint KGPIO_LEVELDETECT1 = 0x044; williamr@4: const TUint KGPIO_RISINGDETECT = 0x048; williamr@4: const TUint KGPIO_FALLINGDETECT = 0x04C; williamr@4: const TUint KGPIO_DEBOUNCENABLE = 0x050; williamr@4: const TUint KGPIO_DEBOUNCINGTIME = 0x054; williamr@4: const TUint KGPIO_CLEARIRQENABLE1 = 0x060; williamr@4: const TUint KGPIO_SETIRQENABLE1 = 0x064; williamr@4: const TUint KGPIO_CLEARIRQENABLE2 = 0x070; williamr@4: const TUint KGPIO_SETIRQENABLE2 = 0x074; williamr@4: const TUint KGPIO_CLEARWKUENA = 0x080; williamr@4: const TUint KGPIO_SETWKUENA = 0x084; williamr@4: const TUint KGPIO_CLEARDATAOUT = 0x090; williamr@4: const TUint KGPIO_SETDATAOUT = 0x094; williamr@4: williamr@4: const TUint KGPIO_DEBOUNCE_TIME_MASK = 0xF; williamr@4: williamr@4: williamr@4: enum TGPIO_InterruptId williamr@4: { williamr@4: EGPIOIRQ_FIRST = (EIrqRangeBaseGpio << KIrqRangeIndexShift), williamr@4: EGPIOIRQ_PIN_0 = EGPIOIRQ_FIRST, williamr@4: EGPIOIRQ_PIN_1, williamr@4: EGPIOIRQ_PIN_2, williamr@4: EGPIOIRQ_PIN_3, williamr@4: EGPIOIRQ_PIN_4, williamr@4: EGPIOIRQ_PIN_5, williamr@4: EGPIOIRQ_PIN_6, williamr@4: EGPIOIRQ_PIN_7, williamr@4: EGPIOIRQ_PIN_8, williamr@4: EGPIOIRQ_PIN_9, williamr@4: EGPIOIRQ_PIN_10, williamr@4: EGPIOIRQ_PIN_11, williamr@4: EGPIOIRQ_PIN_12, williamr@4: EGPIOIRQ_PIN_13, williamr@4: EGPIOIRQ_PIN_14, williamr@4: EGPIOIRQ_PIN_15, williamr@4: EGPIOIRQ_PIN_16, williamr@4: EGPIOIRQ_PIN_17, williamr@4: EGPIOIRQ_PIN_18, williamr@4: EGPIOIRQ_PIN_19, williamr@4: EGPIOIRQ_PIN_20, williamr@4: EGPIOIRQ_PIN_21, williamr@4: EGPIOIRQ_PIN_22, williamr@4: EGPIOIRQ_PIN_23, williamr@4: EGPIOIRQ_PIN_24, williamr@4: EGPIOIRQ_PIN_25, williamr@4: EGPIOIRQ_PIN_26, williamr@4: EGPIOIRQ_PIN_27, williamr@4: EGPIOIRQ_PIN_28, williamr@4: EGPIOIRQ_PIN_29, williamr@4: EGPIOIRQ_PIN_30, williamr@4: EGPIOIRQ_PIN_31, williamr@4: EGPIOIRQ_PIN_32, williamr@4: EGPIOIRQ_PIN_33, williamr@4: EGPIOIRQ_PIN_34, williamr@4: EGPIOIRQ_PIN_35, williamr@4: EGPIOIRQ_PIN_36, williamr@4: EGPIOIRQ_PIN_37, williamr@4: EGPIOIRQ_PIN_38, williamr@4: EGPIOIRQ_PIN_39, williamr@4: EGPIOIRQ_PIN_40, williamr@4: EGPIOIRQ_PIN_41, williamr@4: EGPIOIRQ_PIN_42, williamr@4: EGPIOIRQ_PIN_43, williamr@4: EGPIOIRQ_PIN_44, williamr@4: EGPIOIRQ_PIN_45, williamr@4: EGPIOIRQ_PIN_46, williamr@4: EGPIOIRQ_PIN_47, williamr@4: EGPIOIRQ_PIN_48, williamr@4: EGPIOIRQ_PIN_49, williamr@4: EGPIOIRQ_PIN_50, williamr@4: EGPIOIRQ_PIN_51, williamr@4: EGPIOIRQ_PIN_52, williamr@4: EGPIOIRQ_PIN_53, williamr@4: EGPIOIRQ_PIN_54, williamr@4: EGPIOIRQ_PIN_55, williamr@4: EGPIOIRQ_PIN_56, williamr@4: EGPIOIRQ_PIN_57, williamr@4: EGPIOIRQ_PIN_58, williamr@4: EGPIOIRQ_PIN_59, williamr@4: EGPIOIRQ_PIN_60, williamr@4: EGPIOIRQ_PIN_61, williamr@4: EGPIOIRQ_PIN_62, williamr@4: EGPIOIRQ_PIN_63, williamr@4: EGPIOIRQ_PIN_64, williamr@4: EGPIOIRQ_PIN_65, williamr@4: EGPIOIRQ_PIN_66, williamr@4: EGPIOIRQ_PIN_67, williamr@4: EGPIOIRQ_PIN_68, williamr@4: EGPIOIRQ_PIN_69, williamr@4: EGPIOIRQ_PIN_70, williamr@4: EGPIOIRQ_PIN_71, williamr@4: EGPIOIRQ_PIN_72, williamr@4: EGPIOIRQ_PIN_73, williamr@4: EGPIOIRQ_PIN_74, williamr@4: EGPIOIRQ_PIN_75, williamr@4: EGPIOIRQ_PIN_76, williamr@4: EGPIOIRQ_PIN_77, williamr@4: EGPIOIRQ_PIN_78, williamr@4: EGPIOIRQ_PIN_79, williamr@4: EGPIOIRQ_PIN_80, williamr@4: EGPIOIRQ_PIN_81, williamr@4: EGPIOIRQ_PIN_82, williamr@4: EGPIOIRQ_PIN_83, williamr@4: EGPIOIRQ_PIN_84, williamr@4: EGPIOIRQ_PIN_85, williamr@4: EGPIOIRQ_PIN_86, williamr@4: EGPIOIRQ_PIN_87, williamr@4: EGPIOIRQ_PIN_88, williamr@4: EGPIOIRQ_PIN_89, williamr@4: EGPIOIRQ_PIN_90, williamr@4: EGPIOIRQ_PIN_91, williamr@4: EGPIOIRQ_PIN_92, williamr@4: EGPIOIRQ_PIN_93, williamr@4: EGPIOIRQ_PIN_94, williamr@4: EGPIOIRQ_PIN_95, williamr@4: EGPIOIRQ_PIN_96, williamr@4: EGPIOIRQ_PIN_97, williamr@4: EGPIOIRQ_PIN_98, williamr@4: EGPIOIRQ_PIN_99, williamr@4: EGPIOIRQ_PIN_100, williamr@4: EGPIOIRQ_PIN_101, williamr@4: EGPIOIRQ_PIN_102, williamr@4: EGPIOIRQ_PIN_103, williamr@4: EGPIOIRQ_PIN_104, williamr@4: EGPIOIRQ_PIN_105, williamr@4: EGPIOIRQ_PIN_106, williamr@4: EGPIOIRQ_PIN_107, williamr@4: EGPIOIRQ_PIN_108, williamr@4: EGPIOIRQ_PIN_109, williamr@4: EGPIOIRQ_PIN_110, williamr@4: EGPIOIRQ_PIN_111, williamr@4: EGPIOIRQ_PIN_112, williamr@4: EGPIOIRQ_PIN_113, williamr@4: EGPIOIRQ_PIN_114, williamr@4: EGPIOIRQ_PIN_115, williamr@4: EGPIOIRQ_PIN_116, williamr@4: EGPIOIRQ_PIN_117, williamr@4: EGPIOIRQ_PIN_118, williamr@4: EGPIOIRQ_PIN_119, williamr@4: EGPIOIRQ_PIN_120, williamr@4: EGPIOIRQ_PIN_121, williamr@4: EGPIOIRQ_PIN_122, williamr@4: EGPIOIRQ_PIN_123, williamr@4: EGPIOIRQ_PIN_124, williamr@4: EGPIOIRQ_PIN_125, williamr@4: EGPIOIRQ_PIN_126, williamr@4: EGPIOIRQ_PIN_127, williamr@4: EGPIOIRQ_PIN_128, williamr@4: EGPIOIRQ_PIN_129, williamr@4: EGPIOIRQ_PIN_130, williamr@4: EGPIOIRQ_PIN_131, williamr@4: EGPIOIRQ_PIN_132, williamr@4: EGPIOIRQ_PIN_133, williamr@4: EGPIOIRQ_PIN_134, williamr@4: EGPIOIRQ_PIN_135, williamr@4: EGPIOIRQ_PIN_136, williamr@4: EGPIOIRQ_PIN_137, williamr@4: EGPIOIRQ_PIN_138, williamr@4: EGPIOIRQ_PIN_139, williamr@4: EGPIOIRQ_PIN_140, williamr@4: EGPIOIRQ_PIN_141, williamr@4: EGPIOIRQ_PIN_142, williamr@4: EGPIOIRQ_PIN_143, williamr@4: EGPIOIRQ_PIN_144, williamr@4: EGPIOIRQ_PIN_145, williamr@4: EGPIOIRQ_PIN_146, williamr@4: EGPIOIRQ_PIN_147, williamr@4: EGPIOIRQ_PIN_148, williamr@4: EGPIOIRQ_PIN_149, williamr@4: EGPIOIRQ_PIN_150, williamr@4: EGPIOIRQ_PIN_151, williamr@4: EGPIOIRQ_PIN_152, williamr@4: EGPIOIRQ_PIN_153, williamr@4: EGPIOIRQ_PIN_154, williamr@4: EGPIOIRQ_PIN_155, williamr@4: EGPIOIRQ_PIN_156, williamr@4: EGPIOIRQ_PIN_157, williamr@4: EGPIOIRQ_PIN_158, williamr@4: EGPIOIRQ_PIN_159, williamr@4: EGPIOIRQ_PIN_160, williamr@4: EGPIOIRQ_PIN_161, williamr@4: EGPIOIRQ_PIN_162, williamr@4: EGPIOIRQ_PIN_163, williamr@4: EGPIOIRQ_PIN_164, williamr@4: EGPIOIRQ_PIN_165, williamr@4: EGPIOIRQ_PIN_166, williamr@4: EGPIOIRQ_PIN_167, williamr@4: EGPIOIRQ_PIN_168, williamr@4: EGPIOIRQ_PIN_169, williamr@4: EGPIOIRQ_PIN_170, williamr@4: EGPIOIRQ_PIN_171, williamr@4: EGPIOIRQ_PIN_172, williamr@4: EGPIOIRQ_PIN_173, williamr@4: EGPIOIRQ_PIN_174, williamr@4: EGPIOIRQ_PIN_175, williamr@4: EGPIOIRQ_PIN_176, williamr@4: EGPIOIRQ_PIN_177, williamr@4: EGPIOIRQ_PIN_178, williamr@4: EGPIOIRQ_PIN_179, williamr@4: EGPIOIRQ_PIN_180, williamr@4: EGPIOIRQ_PIN_181, williamr@4: EGPIOIRQ_PIN_182, williamr@4: EGPIOIRQ_PIN_183, williamr@4: EGPIOIRQ_PIN_184, williamr@4: EGPIOIRQ_PIN_185, williamr@4: EGPIOIRQ_PIN_186, williamr@4: EGPIOIRQ_PIN_187, williamr@4: EGPIOIRQ_PIN_188, williamr@4: EGPIOIRQ_PIN_189, williamr@4: EGPIOIRQ_PIN_190, williamr@4: EGPIOIRQ_PIN_191, williamr@4: williamr@4: EGPIOIRQ_END williamr@4: }; williamr@4: williamr@4: williamr@4: williamr@4: const TInt32 KHwGpioPinMax = 192; // 32*6 pins williamr@4: const TInt32 KHwGpioPinsPerBank = 32; williamr@4: const TInt32 KHwGpioBanks = KHwGpioPinMax / KHwGpioPinsPerBank ; williamr@4: williamr@4: // Utility code to convert a pin number to a GPIO bank williamr@4: const TUint KGPIO_BASE_ADDRESSES[] = { KGPIO1, KGPIO2, KGPIO3, KGPIO4, KGPIO5, KGPIO6 }; williamr@4: williamr@4: williamr@4: williamr@4: williamr@4: williamr@4: inline TUint GPIO_BASE_ADDRESS(TInt aPin) {return KGPIO_BASE_ADDRESSES[(TInt)(aPin/KHwGpioPinsPerBank)];}; williamr@4: #define GPIO_PIN_BANK(aId) ((aId)/KHwGpioPinsPerBank) williamr@4: #define GPIO_PIN_OFFSET(aId) (1 << (aId%KHwGpioPinsPerBank)) williamr@4: #define GPIO_PIN_BOUNDS(aId)((aId > 0) && (aId