williamr@4: // Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies). williamr@4: // All rights reserved. williamr@4: // This component and the accompanying materials are made available williamr@4: // under the terms of the License "Eclipse Public License v1.0" williamr@4: // which accompanies this distribution, and is available williamr@4: // at the URL "http://www.eclipse.org/legal/epl-v10.html". williamr@4: // williamr@4: // Initial Contributors: williamr@4: // Nokia Corporation - initial contribution. williamr@4: // williamr@4: // Contributors: williamr@4: // williamr@4: // Description: williamr@4: // omap3530/omap3530_assp/assp.mmh williamr@4: // TO DO: (mandatory) williamr@4: // Add here a definition for your CPU (list in CONFIG.INC) williamr@4: // macro __CPU_CORTEX_A8__ williamr@4: // williamr@4: williamr@4: macro __CPU_CORTEX_A8N__ williamr@4: williamr@4: // TO DO: (mandatory) williamr@4: // williamr@4: // Add here a definition for your Memory Model williamr@4: // williamr@4: #define MM_MULTIPLE williamr@4: williamr@4: // TO DO: (mandatory) williamr@4: // williamr@4: // Macro which generates the names for the binaries for this platform williamr@4: // williamr@4: #define AsspTarget(name,ext) _omap3530_##name##.##ext williamr@4: williamr@4: //Include debug support. Some e32 tests require debug support williamr@4: macro __DEBUGGER_SUPPORT__ williamr@4: williamr@4: // williamr@4: // TO DO: williamr@4: // williamr@4: // If euser is built from the variant, uncomment the following line to build it williamr@4: // as ARM rather than Thumb williamr@4: // williamr@4: // #define __BUILD_VARIANT_EUSER_AS_ARM__ williamr@4: williamr@4: // TO DO: (optional) williamr@4: // williamr@4: // To replace some of the generic utility functions with variant specific williamr@4: // versions (eg to replace memcpy with a version optimised for the hardware), williamr@4: // uncomment the two lines below and edit the files in the replacementUtils williamr@4: // directory. williamr@4: // williamr@4: // #define REPLACE_GENERIC_UTILS williamr@4: // #define VariantReplacementUtilsPath beagle/beagle_variant/replacement_utils williamr@4: williamr@4: // TO DO: (optional) williamr@4: // williamr@4: // Enable BTrace support in release versions of the kernel by adding williamr@4: // the following BTRACE macro declarations williamr@4: // williamr@4: // macro BTRACE_KERNEL_ALL williamr@4: williamr@4: // TO DO: williamr@4: // williamr@4: // Uncomment the following line if using the r1p0 release or later of the ARM1136 processor. williamr@4: // williamr@4: // macro __CPU_ARM1136_IS_R1__ williamr@4: williamr@4: // TO DO: williamr@4: // williamr@4: // Include the following line if default memory mapping should use shared memory. williamr@4: // Should be on for multicore (SMP) devices. williamr@4: // williamr@4: // macro __CPU_USE_SHARED_MEMORY williamr@4: // williamr@4: williamr@4: // TO DO: williamr@4: // williamr@4: // Uncomment the next line if using the ARM1136 processor and ARM1136 Erratum 406973 williamr@4: // "CLREX instruction might be ignored during data cache line fill" williamr@4: // is fixed on this hardware. williamr@4: // williamr@4: // macro __CPU_ARM1136_ERRATUM_406973_FIXED williamr@4: williamr@4: // Uncomment next line if: williamr@4: // 1) using the ARM1136 processor and ARM1136 Erratum 408022 "Cancelled write to CONTEXTID register might update ASID" williamr@4: // is fixed on this hardware, or williamr@4: // 2) using the ARM1176 processor and ARM1176 Erratum 415047 "Cancelled write to CONTEXTID register might update ASID" williamr@4: // is fixed on this hardware. williamr@4: // williamr@4: // macro __CPU_ARM1136_ERRATUM_408022_FIXED williamr@4: williamr@4: // Uncomment if: williamr@4: // 1) using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache williamr@4: // operation might fail to invalidate some lines if coincident with linefill" williamr@4: // is fixed on this hardware, or williamr@4: // 2) using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache williamr@4: // operation might fail to invalidate some lines if coincident with linefill williamr@4: // is fixed on this hardware. williamr@4: // Workaround: williamr@4: // 1) Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg. williamr@4: // 2) Replaces Invalidate ICache operation with the sequence defined in the errata document. williamr@4: // If this macro is enabled, it should be accompanied by: williamr@4: // "GBLL CFG_CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh williamr@4: // williamr@4: // macro __CPU_ARM1136_ERRATUM_411920_FIXED williamr@4: williamr@4: // Uncomment the following line if Page Tables/Dirs have to be updated in main memory. williamr@4: // Standard platforms shouldn't have this feature switched on. williamr@4: // This must be accompanied by __ARM_L210_CACHE__ or __ARM_L220_CACHE__ macro. williamr@4: // Omission:: The solution doesn't update temporary mappings williamr@4: // of inter-process communication (IPC) - aka aliasing. williamr@4: // williamr@4: // macro __FLUSH_PT_INTO_RAM__ williamr@4: williamr@4: // Uncomment the following line if Symbian OS is running in TrustZone non-secure state and the williamr@4: // secure state has prevented code executing in non-secure state from being able to mask FIQs by williamr@4: // setting the SCR.FW bit in the secure configuration register. williamr@4: // williamr@4: // macro __FIQ_RESERVED_FOR_SECURE_STATE__ williamr@4: williamr@4: // Various PlatSec configuration options cannot be disabled even by clearing the appropriate williamr@4: // bits in the kernel configuration flags - they are enforced at compile time. Uncomment the williamr@4: // following to allow the clearing of bits in the kernel config flags to disable the relevant williamr@4: // options at run time. williamr@4: // williamr@4: //macro __PLATSEC_UNLOCKED__ williamr@4: williamr@4: // If this macro is enabled then EMapAttrBufferedNC memory will be remapped as EMapAttrFullyBlocking williamr@4: //macro FAULTY_NONSHARED_DEVICE_MEMORY williamr@4: williamr@4: // Uncomment the following line if L210/20 cache is running in forced-WT mode. williamr@4: // (Forced_WT bit set in Debug Control Register of L210/20 cache controller.) williamr@4: // macro __ARM_L2_CACHE_WT_MODE williamr@4: williamr@4: // For the status of errata of L210 & L220 cache, see the header of source file: williamr@4: // e32\kernel\arm\cachel2.cpp williamr@4: williamr@4: #if defined(__USING_USING_ASSP_REGISTER_API__) || defined(__USING_INTERRUPT_API__) || defined(__USING_ASSP_REGISTER_API__) williamr@4: library AsspTarget(kaomap3530,lib) williamr@4: #endif williamr@4: