williamr@2: // Copyright (c) 1997-2009 Nokia Corporation and/or its subsidiary(-ies). williamr@2: // All rights reserved. williamr@2: // This component and the accompanying materials are made available williamr@2: // under the terms of the License "Symbian Foundation License v1.0" to Symbian Foundation members and "Symbian Foundation End User License Agreement v1.0" to non-members williamr@2: // which accompanies this distribution, and is available williamr@2: // at the URL "http://www.symbianfoundation.org/legal/licencesv10.html". williamr@2: // williamr@2: // Initial Contributors: williamr@2: // Nokia Corporation - initial contribution. williamr@2: // williamr@2: // Contributors: williamr@2: // williamr@2: // Description: williamr@2: // template\template_assp\template_assp.h williamr@2: // Definitions for Template ASSP williamr@2: // williamr@2: // williamr@2: williamr@2: williamr@2: williamr@2: #ifndef __A32TEMPLATEV1_H__ williamr@2: #define __A32TEMPLATEV1_H__ williamr@2: #include williamr@2: #include williamr@2: #include williamr@2: #include williamr@2: #include williamr@2: williamr@2: //---------------------------------------------------------------------------- williamr@2: // Constant conventions: williamr@2: //---------------------------------------------------------------------------- williamr@2: williamr@2: // KH Hardware definition williamr@2: // KHw 4-byte word definition prefix williamr@2: // KHb Byte definition prefix williamr@2: // KHt Bit definition prefix williamr@2: // KHm Mask definition prefix williamr@2: // KHs Shift definition prefix williamr@2: // KHo Offset definition prefix williamr@2: // KHwRo Read-only register williamr@2: // KHwWo Write-only register williamr@2: // KHwRw Read/write register williamr@2: // KHwBase Base address within memory map williamr@2: // _i Input suffix williamr@2: // _o Output suffix williamr@2: // _b Input/output suffix williamr@2: williamr@2: //---------------------------------------------------------------------------- williamr@2: // Memory map: physical addresses williamr@2: //---------------------------------------------------------------------------- williamr@2: // NB: these are just examples williamr@2: williamr@2: const TUint KHwBaseCs0 = 0x00000000; williamr@2: const TUint KHwBaseCs1 = KHwBaseCs0 + 128*KMega; williamr@2: const TUint KHwBaseCs2 = KHwBaseCs1 + 128*KMega; williamr@2: const TUint KHwBaseCs3 = KHwBaseCs2 + 128*KMega; williamr@2: williamr@2: const TUint KHwBaseMemBank0 = 0x20000000; williamr@2: const TUint KHwBaseMemBank1 = KHwBaseMemBank0 + 256*KMega; williamr@2: williamr@2: const TUint KHwBaseRegisters = 0x80000000; williamr@2: const TUint KHwBasePeripherals = KHwBaseRegisters; // 8000.0000 williamr@2: const TUint KHwBasePeripheralsA = KHwBasePeripherals + 256*KMega; // 9000.0000 williamr@2: const TUint KHwBasePeripheralsB = KHwBasePeripheralsA + 256*KMega; // A000.0000 williamr@2: const TUint KHwBasePeripheralsC = KHwBasePeripheralsB + 256*KMega; // B000.0000 williamr@2: williamr@2: // etc... williamr@2: williamr@2: //---------------------------------------------------------------------------- williamr@2: // Memory map: linear addresses williamr@2: //---------------------------------------------------------------------------- williamr@2: williamr@2: #if defined (__MEMMODEL_MULTIPLE__) williamr@2: const TUint KHwLinBaseRegisters = 0xc6000000; // as mapped by bootstrap williamr@2: const TUint KHwLinSeparation = 0x1000; williamr@2: #elif defined(__MEMMODEL_DIRECT__) williamr@2: const TUint KHwLinBaseRegisters = 0x10000000; // physical address (example only) williamr@2: const TUint KHwLinSeparation = 0x01000000; // physical offsets (example only) williamr@2: #else williamr@2: const TUint KHwLinBaseRegisters = 0x63000000; // as mapped by bootstrap williamr@2: const TUint KHwLinSeparation = 0x1000; williamr@2: #endif williamr@2: williamr@2: // EXAMPLE ONLY: williamr@2: const TUint KHwLinBasePeriphGroupA = KHwLinBaseRegisters; williamr@2: const TUint KHwLinBasePeripheral1 = KHwLinBasePeriphGroupA + 0x00*KHwLinSeparation; williamr@2: const TUint KHwLinBasePeripheral2 = KHwLinBasePeriphGroupA + 0x01*KHwLinSeparation; williamr@2: const TUint KHwLinBasePeripheral3 = KHwLinBasePeriphGroupA + 0x02*KHwLinSeparation; williamr@2: const TUint KHwLinBasePeripheral4 = KHwLinBasePeriphGroupA + 0x03*KHwLinSeparation; williamr@2: williamr@2: const TUint KHwLinBasePeriphGroupB = KHwLinBaseRegisters + 0x20*KHwLinSeparation; williamr@2: williamr@2: const TUint KHwBaseSerial1 = KHwLinBasePeriphGroupB + 0x00*KHwLinSeparation; williamr@2: const TUint KHwBaseSerial2 = KHwLinBasePeriphGroupB + 0x01*KHwLinSeparation; williamr@2: const TUint KHwBaseSerial3 = KHwLinBasePeriphGroupB + 0x02*KHwLinSeparation; williamr@2: williamr@2: const TUint KHwLinBasePeriphGroupC = KHwLinBaseRegisters + 0x30*KHwLinSeparation; williamr@2: williamr@2: const TUint KHwBaseInterrupts = KHwLinBasePeriphGroupC + 0x00*KHwLinSeparation; williamr@2: const TUint KHwInterruptsMaskRo = KHwBaseInterrupts + 0x00; williamr@2: const TUint KHwInterruptsMaskSet = KHwBaseInterrupts + 0x04; williamr@2: const TUint KHwInterruptsMaskClear = KHwBaseInterrupts + 0x08; williamr@2: const TUint KHoInterruptsIrqPending = 0x0C; williamr@2: const TUint KHwInterruptsIrqPending = KHwBaseInterrupts + KHoInterruptsIrqPending; williamr@2: const TUint KHoInterruptsFiqPending = 0x10; williamr@2: const TUint KHwInterruptsFiqending = KHwBaseInterrupts + KHoInterruptsFiqPending; williamr@2: williamr@2: williamr@2: // Other device specifc constants, register offsets, bit masks, general-purpose I/O allocations, williamr@2: // interrupt sources, Memory settings and geometries, etc williamr@2: williamr@2: williamr@2: class TTemplate williamr@2: { williamr@2: /** williamr@2: * Accessor functions to hardware resources managed by ASSP (ASIC). Auxiliary and information functions which williamr@2: * are commonly used by Device Drivers or ASSP/Variant code. williamr@2: * Some examples below. These examples assume that the hardware blocks they access (e.g. Interrupt controller williamr@2: * RTC, Clock Control Module, UART, etc) are part of the ASSP. williamr@2: */ williamr@2: public: williamr@2: /** williamr@2: * initialisation williamr@2: */ williamr@2: static void Init3(); williamr@2: /** williamr@2: * Active waiting loop (not to be used after System Tick timer has been set up - Init3() williamr@2: * @param aDuration A wait time in milliseconds williamr@2: */ williamr@2: IMPORT_C static void BootWaitMilliSeconds(TInt aDuration); williamr@2: /** williamr@2: * Read and return the Startup reason of the Hardware williamr@2: * @return A TMachineStartupType enumerated value williamr@2: */ williamr@2: IMPORT_C static TMachineStartupType StartupReason(); williamr@2: /** williamr@2: * Read and return the the CPU ID williamr@2: * @return An integer containing the CPU ID string read off the hardware williamr@2: */ williamr@2: IMPORT_C static TInt CpuVersionId(); williamr@2: /** williamr@2: * Read Linear base address of debug UART (as selected in obey file or with eshell debugport command). williamr@2: * @return An integer containing the Linear address of debug Serial Port williamr@2: */ williamr@2: IMPORT_C static TUint DebugPortAddr(); williamr@2: /** williamr@2: * Read CPU clock period in picoseconds williamr@2: * @return An integer containing the CPU clock period in picoseconds williamr@2: */ williamr@2: IMPORT_C static TUint ProcessorPeriodInPs(); williamr@2: /** williamr@2: * Set the Hardware Interrupt masks williamr@2: * @param aValue A new interrupt mask value williamr@2: */ williamr@2: IMPORT_C static void SetIntMask(TUint aValue); williamr@2: /** williamr@2: * Modify the Hardware Interrupt masks williamr@2: * @param aClearMask A mask with interrupt source bits to clear (disable) williamr@2: * @param aSetMask A mask with interrupt source bits to set (enable) williamr@2: */ williamr@2: IMPORT_C static void ModifyIntMask(TUint aClearMask,TUint aSetMask); williamr@2: /** williamr@2: * Read the state of pending interrupts williamr@2: * @return A mask containing bits set for all pending interrupts williamr@2: */ williamr@2: IMPORT_C static TUint IntsPending(); williamr@2: /** williamr@2: * Read the current time of the RTC williamr@2: * @return A value that is the real time as given by a RTC williamr@2: */ williamr@2: IMPORT_C static TUint RtcData(); williamr@2: /** williamr@2: * Set the RTC time williamr@2: * @param aValue The real time to set the RTC williamr@2: */ williamr@2: IMPORT_C static void SetRtcData(TUint aValue); williamr@2: /** williamr@2: * Obtain the physical start address of Video Buffer williamr@2: * @return the physical start address of Video Buffer williamr@2: */ williamr@2: IMPORT_C static TPhysAddr VideoRamPhys(); williamr@2: private: williamr@2: /** williamr@2: * Auxiliary accessor functions for Hardware registers (used by functions above) williamr@2: */ williamr@2: static inline TUint Register32(TUint aAddr); williamr@2: static inline void SetRegister32(TUint aValue, TUint aAddr); williamr@2: static void ModifyRegister32(TUint aClearMask, TUint aSetMask, TUint aAddr); williamr@2: /** williamr@2: * Assp-specific implementation for Kern::NanoWait function williamr@2: */ williamr@2: static void NanoWait(TUint32 aInterval); williamr@2: }; williamr@2: williamr@2: // TO DO: (optional) williamr@2: // williamr@2: // Enumerate here all ASSP interrupt souces. It could be a good idea to enumerate them in a way that facilitates williamr@2: // operating on the corresponding interrupt controller registers (e.g using their value as a shift count) williamr@2: // williamr@2: // EXAMPLE ONLY williamr@2: enum TTemplateAsspInterruptId williamr@2: { williamr@2: // ASSP or first-level Interrupt IDs williamr@2: EAsspIntIdA=0, williamr@2: EAsspIntIdB=1, williamr@2: EAsspIntIdC=2, williamr@2: EAsspIntIdD=3, williamr@2: EAsspIntIdE=4, williamr@2: // ... williamr@2: EAsspIntIdUsb=11, williamr@2: EAsspIntIdDma=12, williamr@2: // ... williamr@2: EAsspIntIdZ=25 williamr@2: }; williamr@2: williamr@2: // williamr@2: // TO DO: (optional) williamr@2: // williamr@2: // Define here some commonly used ASSP interrupts williamr@2: // williamr@2: // EXAMPLE ONLY williamr@2: const TInt KIntIdExpansion=EAsspIntIdA; // this is the ASSP interrupt which connects to second-level (Variant) williamr@2: // Interrupt controller: all 2nd level interrupts come through this interrupt williamr@2: const TInt KIntIdOstMatchMsTimer=EAsspIntIdB; williamr@2: const TInt KIntIdDigitiser=EAsspIntIdC; williamr@2: const TInt KIntIdSound=EAsspIntIdD; williamr@2: const TInt KIntIdTimer1=EAsspIntIdE; williamr@2: williamr@2: williamr@2: #endif