1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/epoc32/include/assp/omap3530_shared/tps65950_registers.h Wed Mar 31 12:33:34 2010 +0100
1.3 @@ -0,0 +1,1320 @@
1.4 +// Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +//
1.18 +
1.19 +#ifndef TPS65950_REGISTERS_H
1.20 +#define TPS65950_REGISTERS_H
1.21 +
1.22 +#include <e32cmn.h>
1.23 +
1.24 +namespace TPS65950
1.25 +{
1.26 +
1.27 +namespace Register
1.28 + {
1.29 + const TUint KGroupShift = 8;
1.30 + const TUint KRegisterMask = 0xFF;
1.31 + const TUint KGroupMask = 0xFF00;
1.32 +
1.33 + enum TGroup
1.34 + {
1.35 + EGroup12 = (0 << KGroupShift),
1.36 + EGroup48 = (1 << KGroupShift),
1.37 + EGroup49 = (2 << KGroupShift),
1.38 + EGroup4a = (3 << KGroupShift),
1.39 + EGroup4b = (4 << KGroupShift)
1.40 + };
1.41 +
1.42 + enum TGroup12Registers
1.43 + {
1.44 + VDD1_SR_CONTROL = EGroup12,
1.45 + VDD2_SR_CONTROL
1.46 + };
1.47 +
1.48 +
1.49 + enum TGroup48Registers
1.50 + {
1.51 + VENDOR_ID_LO = EGroup48,
1.52 + VENDOR_ID_HI,
1.53 + PRODUCT_ID_LO,
1.54 + PRODUCT_ID_HI,
1.55 + FUNC_CTRL,
1.56 + FUNC_CTRL_SET,
1.57 + FUNC_CTRL_CLR,
1.58 + IFC_CTRL,
1.59 + IFC_CTRL_SET,
1.60 + IFC_CTRL_CLR,
1.61 + OTG_CTRL,
1.62 + OTG_CTRL_SET,
1.63 + OTG_CTRL_CLR,
1.64 + USB_INT_EN_RISE,
1.65 + USB_INT_EN_RISE_SET,
1.66 + USB_INT_EN_RISE_CLR,
1.67 + USB_INT_EN_FALL,
1.68 + USB_INT_EN_FALL_SET,
1.69 + USB_INT_EN_FALL_CLR,
1.70 + USB_INT_STS,
1.71 + USB_INT_LATCH,
1.72 + DEBUG,
1.73 + SCRATCH_REG,
1.74 + SCRATCH_REG_SET,
1.75 + SCRATCH_REG_CLR,
1.76 + CARKIT_CTRL,
1.77 + CARKIT_CTRL_SET,
1.78 + CARKIT_CTRL_CLR,
1.79 + CARKIT_INT_DELAY,
1.80 + CARKIT_INT_EN,
1.81 + CARKIT_INT_EN_SET,
1.82 + CARKIT_INT_EN_CLR,
1.83 + CARKIT_INT_STS,
1.84 + CARKIT_INT_LATCH,
1.85 + CARKIT_PLS_CTRL,
1.86 + CARKIT_PLS_CTRL_SET,
1.87 + CARKIT_PLS_CTRL_CLR,
1.88 + TRANS_POS_WIDTH,
1.89 + TRANS_NEG_WIDTH,
1.90 + RCV_PLTY_RECOVERY,
1.91 + MCPC_CTRL = 0x30,
1.92 + MCPC_CTRL_SET,
1.93 + MCPC_CTRL_CLR,
1.94 + MCPC_IO_CTRL,
1.95 + MCPC_IO_CTRL_SET,
1.96 + MCPC_IO_CTRL_CLR,
1.97 + MCPC_CTRL2,
1.98 + MCPC_CTRL2_SET,
1.99 + MCPC_CTRL2_CLR,
1.100 + OTHER_FUNC_CTRL = EGroup48 + 0x80,
1.101 + OTHER_FUNC_CTRL_SET,
1.102 + OTHER_FUNC_CTRL_CLR,
1.103 + OTHER_IFC_CTRL,
1.104 + OTHER_IFC_CTRL_SET,
1.105 + OTHER_IFC_CTRL_CLR,
1.106 + OTHER_INT_EN_RISE,
1.107 + OTHER_INT_EN_RISE_SET,
1.108 + OTHER_INT_EN_RISE_CLR,
1.109 + OTHER_INT_EN_FALL,
1.110 + OTHER_INT_EN_FALL_SET,
1.111 + OTHER_INT_EN_FALL_CLR,
1.112 + OTHER_INT_STS,
1.113 + OTHER_INT_LATCH,
1.114 + ID_INT_EN_RISE,
1.115 + ID_INT_EN_RISE_SET,
1.116 + ID_INT_EN_RISE_CLR,
1.117 + ID_INT_EN_FALL,
1.118 + ID_INT_EN_FALL_SET,
1.119 + ID_INT_EN_FALL_CLR,
1.120 + ID_INT_STS,
1.121 + ID_INT_LATCH,
1.122 + ID_STATUS,
1.123 + CARKIT_SM_1_INT_EN,
1.124 + CARKIT_SM_1_INT_EN_SET,
1.125 + CARKIT_SM_1_INT_EN_CLR,
1.126 + CARKIT_SM_1_INT_STS,
1.127 + CARKIT_SM_1_INT_LATCH,
1.128 + CARKIT_SM_2_INT_EN,
1.129 + CARKIT_SM_2_INT_EN_SET,
1.130 + CARKIT_SM_2_INT_EN_CLR,
1.131 + CARKIT_SM_2_INT_STS,
1.132 + CARKIT_SM_2_INT_LATCH,
1.133 + CARKIT_SM_CTRL,
1.134 + CARKIT_SM_CTRL_SET,
1.135 + CARKIT_SM_CTRL_CLR,
1.136 + CARKIT_SM_CMD,
1.137 + CARKIT_SM_CMD_SET,
1.138 + CARKIT_SM_CMD_CLR,
1.139 + CARKIT_SM_CMD_STS,
1.140 + CARKIT_SM_STATUS,
1.141 + CARKIT_SM_NEXT_STATUS,
1.142 + CARKIT_SM_ERR_STATUS,
1.143 + CARKIT_SM_CTRL_STATE,
1.144 + POWER_CTRL,
1.145 + POWER_CTRL_SET,
1.146 + POWER_CTRL_CLR,
1.147 + OTHER_IFC_CTRL2,
1.148 + OTHER_IFC_CTRL2_SET,
1.149 + OTHER_IFC_CTRL2_CLR,
1.150 + REG_CTRL_EN,
1.151 + REG_CTRL_EN_SET,
1.152 + REG_CTRL_EN_CLR,
1.153 + REG_CTRL_ERROR,
1.154 + OTHER_FUNC_CTRL2,
1.155 + OTHER_FUNC_CTRL2_SET,
1.156 + OTHER_FUNC_CTRL2_CLR,
1.157 + CARKIT_ANA_CTRL,
1.158 + CARKIT_ANA_CTRL_SET,
1.159 + CARKIT_ANA_CTRL_CLR,
1.160 + VBUS_DEBOUNCE = EGroup48 + 0xC0,
1.161 + ID_DEBOUNCE,
1.162 + TPH_DP_CON_MIN,
1.163 + TPH_DP_CON_MAX,
1.164 + TCR_DP_CON_MIN,
1.165 + TCR_DP_CON_MAX,
1.166 + TPH_DP_PD_SHORT,
1.167 + TPH_CMD_DLY,
1.168 + TPH_DET_RST,
1.169 + TPH_AUD_BIAS,
1.170 + TCR_UART_DET_MIN,
1.171 + TCR_UART_DET_MAX,
1.172 + TPH_ID_INT_PW = EGroup48 + 0xCC,
1.173 + TACC_ID_INT_WAIT,
1.174 + TACC_ID_INT_PW,
1.175 + TPH_CMD_WAIT = EGroup48 + 0xD0,
1.176 + TPH_ACK_WAIT,
1.177 + TPH_DP_DISC_DET,
1.178 + VBAT_TIMER,
1.179 + CARKIT_4W_DEBUG = EGroup48 + 0xE0,
1.180 + CARKIT_5W_DEBUG,
1.181 + TEST_CTRL_CLR = EGroup48 + 0xEB,
1.182 + TEST_CARKIT_SET,
1.183 + TEST_CARKIT_CLR,
1.184 + TEST_POWER_SET,
1.185 + TEST_POWER_CLR,
1.186 + TEST_ULPI,
1.187 + TXVR_EN_TEST_SET,
1.188 + TXVR_EN_TEST_CLR,
1.189 + VBUS_EN_TEST,
1.190 + ID_EN_TEST,
1.191 + PSM_EN_TEST_SET,
1.192 + PSM_EN_TEST_CLR,
1.193 + PHY_TRIM_CTRL = EGroup48 + 0xFC,
1.194 + PHY_PWR_CTRL,
1.195 + PHY_CLK_CTRL,
1.196 + PHY_CLK_CTRL_STS // 0x000000ff
1.197 + };
1.198 +
1.199 +
1.200 + enum TGroup49Registers
1.201 + {
1.202 + CODEC_MODE = EGroup49 + 1,
1.203 + OPTION ,
1.204 + MICBIAS_CTL = EGroup49 + 0x04,
1.205 + ANAMICL,
1.206 + ANAMICR,
1.207 + AVADC_CTL,
1.208 + ADCMICSEL,
1.209 + DIGMIXING,
1.210 + ATXL1PGA,
1.211 + ATXR1PGA,
1.212 + AVTXL2PGA,
1.213 + AVTXR2PGA,
1.214 + AUDIO_IF,
1.215 + VOICE_IF,
1.216 + ARXR1PGA,
1.217 + ARXL1PGA,
1.218 + ARXR2PGA,
1.219 + ARXL2PGA,
1.220 + VRXPGA,
1.221 + VSTPGA,
1.222 + VRX2ARXPGA,
1.223 + AVDAC_CTL,
1.224 + ARX2VTXPGA,
1.225 + ARXL1_APGA_CTL,
1.226 + ARXR1_APGA_CTL,
1.227 + ARXL2_APGA_CTL,
1.228 + ARXR2_APGA_CTL,
1.229 + ATX2ARXPGA,
1.230 + BT_IF,
1.231 + BTPGA,
1.232 + BTSTPGA,
1.233 + EAR_CTL,
1.234 + HS_SEL,
1.235 + HS_GAIN_SET,
1.236 + HS_POPN_SET,
1.237 + PREDL_CTL,
1.238 + PREDR_CTL,
1.239 + PRECKL_CTL,
1.240 + PRECKR_CTL,
1.241 + HFL_CTL,
1.242 + HFR_CTL,
1.243 + ALC_CTL,
1.244 + ALC_SET1,
1.245 + ALC_SET2,
1.246 + BOOST_CTL,
1.247 + SOFTVOL_CTL,
1.248 + DTMF_FREQSEL,
1.249 + DTMF_TONEXT1H,
1.250 + DTMF_TONEXT1L,
1.251 + DTMF_TONEXT2H,
1.252 + DTMF_TONEXT2L,
1.253 + DTMF_TONOFF,
1.254 + DTMF_WANONOFF,// 8 0x0000 0036
1.255 +
1.256 + I2S_RX_SCRAMBLE_H,
1.257 + I2S_RX_SCRAMBLE_M,
1.258 + I2S_RX_SCRAMBLE_L,
1.259 + APLL_CTL,
1.260 + DTMF_CTL,
1.261 + DTMF_PGA_CTL2,
1.262 + DTMF_PGA_CTL1,
1.263 + MISC_SET_1,
1.264 + PCMBTMUX,
1.265 + RX_PATH_SEL,
1.266 + VDL_APGA_CTL,
1.267 + VIBRA_CTL,
1.268 + VIBRA_SET,
1.269 + ANAMIC_GAIN,
1.270 + MISC_SET_2,// RW 8 0x0000 0049
1.271 +
1.272 + AUDIO_TEST_CTL = EGroup49 + 0x0000004C,
1.273 + INT_TEST_CTL,
1.274 + DAC_ADC_TEST_CTL,
1.275 + RXTX_TRIM_IB,
1.276 + CLD_CONTROL,
1.277 + CLD_MODE_TIMING,
1.278 + CLD_TRIM_RAMP,
1.279 + CLD_TESTV_CTL,
1.280 + APLL_TEST_CTL,
1.281 + APLL_TEST_DIV,
1.282 + APLL_TEST_CTL2,
1.283 + APLL_TEST_CUR,
1.284 + DIGMIC_BIAS1_CTL,
1.285 + DIGMIC_BIAS2_CTL,
1.286 + RX_OFFSET_VOICE,
1.287 + RX_OFFSET_AL1,
1.288 + RX_OFFSET_AR1,
1.289 + RX_OFFSET_AL2,
1.290 + RX_OFFSET_AR2,
1.291 + OFFSET1,
1.292 + OFFSET2,
1.293 +
1.294 +
1.295 + GPIODATAIN1 = EGroup49 + 0x00000098,
1.296 + GPIODATAIN2,
1.297 + GPIODATAIN3,
1.298 + GPIODATADIR1,
1.299 + GPIODATADIR2,
1.300 + GPIODATADIR3,
1.301 + GPIODATAOUT1,
1.302 + GPIODATAOUT2,
1.303 + GPIODATAOUT3,
1.304 + CLEARGPIODATAOUT1,
1.305 + CLEARGPIODATAOUT2,
1.306 + CLEARGPIODATAOUT3,
1.307 + SETGPIODATAOUT1,
1.308 + SETGPIODATAOUT2,
1.309 + SETGPIODATAOUT3,
1.310 + GPIO_DEBEN1,
1.311 + GPIO_DEBEN3,
1.312 + GPIO_CTRL ,
1.313 + GPIOPUPDCTR1,
1.314 + GPIOPUPDCTR2,
1.315 + GPIOPUPDCTR3,
1.316 + GPIOPUPDCTR4,
1.317 + GPIOPUPDCTR5,
1.318 + GPIO_TEST,
1.319 + GPIO_ISR1A = EGroup49 + 0xb1,
1.320 + GPIO_ISR2A,
1.321 + GPIO_ISR3A,
1.322 + GPIO_IMR1A, //
1.323 + GPIO_IMR2A,
1.324 + GPIO_IMR3A,
1.325 + GPIO_ISR1B,
1.326 + GPIO_ISR2B,
1.327 + GPIO_ISR3B,
1.328 + GPIO_IMR1B,
1.329 + GPIO_IMR2B,
1.330 + GPIO_IMR3B,
1.331 + GPIO_SIR1,
1.332 + GPIO_SIR2,
1.333 + GPIO_SIR3,
1.334 + GPIO_EDR1,
1.335 + GPIO_EDR2,
1.336 + GPIO_EDR3,
1.337 + GPIO_EDR4,
1.338 + GPIO_EDR5,
1.339 + GPIO_SIH_CTRL,
1.340 +
1.341 + PIH_ISR_P1 = EGroup49 + 0x00000081,
1.342 + PIH_ISR_P2,
1.343 + PIH_SIR ,
1.344 + IDCODE_7_0 = EGroup49 + 0x00000085,
1.345 + IDCODE_15_8,
1.346 + IDCODE_23_16,
1.347 + IDCODE_31_24,
1.348 + DIEID_7_0,
1.349 + DIEID_15_8,
1.350 + DIEID_23_16,
1.351 + DIEID_31_24,
1.352 + DIEID_39_32,
1.353 + DIEID_47_40,
1.354 + DIEID_55_48,
1.355 + DIEID_63_56,
1.356 + GPBR1,
1.357 + PMBR1,
1.358 + PMBR2,
1.359 + GPPUPDCTR1,
1.360 + GPPUPDCTR2,
1.361 + GPPUPDCTR3,
1.362 + UNLOCK_TEST_REG,
1.363 + };
1.364 +
1.365 +
1.366 +
1.367 + /*
1.368 + Note: Access to the following registers is protected:
1.369 + · IDCODE_7_0
1.370 + · IDCODE_15_8
1.371 + · IDCODE_23_16
1.372 + · IDCODE_31_24
1.373 + · DIEID_7_0
1.374 + · DIEID_15_8
1.375 + · DIEID_23_16
1.376 + · DIEID_31_24
1.377 + · DIEID_39_32
1.378 + · DIEID_47_40
1.379 + · DIEID_55_48
1.380 + · DIEID_63_56
1.381 + To read these registers, the UNLOCK_TEST_REG register must first be written with 0x49.
1.382 + Table 2-29. GPPUPDCTR1
1.383 + Address Offset 0x0F
1.384 + Physical Address 0x0000 0094 Instance INT_SCINTBR
1.385 + */
1.386 +
1.387 + enum TGroup4aRegisters
1.388 + {
1.389 + CTRL1 = EGroup4a + 0,
1.390 + CTRL2,
1.391 + RTSELECT_LSB,
1.392 + RTSELECT_MSB,
1.393 + RTAVERAGE_LSB,
1.394 + RTAVERAGE_MSB,
1.395 + SW1SELECT_LSB,
1.396 + SW1SELECT_MSB,
1.397 + SW1AVERAGE_LSB,
1.398 + SW1AVERAGE_MSB,
1.399 + SW2SELECT_LSB,
1.400 + SW2SELECT_MSB,
1.401 + SW2AVERAGE_LSB,
1.402 + SW2AVERAGE_MSB,
1.403 + BCI_USBAVERAGE,
1.404 + ACQUISITION,
1.405 + USBREF_LSB,
1.406 + USBREF_MSB,
1.407 + CTRL_SW1,
1.408 + CTRL_SW2,
1.409 + MADC_TEST,
1.410 + GP_MADC_TEST1,
1.411 + GP_MADC_TEST2,
1.412 + RTCH0_LSB,
1.413 + RTCH0_MSB,
1.414 + RTCH1_LSB,
1.415 + RTCH1_MSB,
1.416 + RTCH2_LSB,
1.417 + RTCH2_MSB,
1.418 + RTCH3_LSB,
1.419 + RTCH3_MSB,
1.420 + RTCH4_LSB,
1.421 + RTCH4_MSB,
1.422 + RTCH5_LSB,
1.423 + RTCH5_MSB,
1.424 + RTCH6_LSB,
1.425 + RTCH6_MSB,
1.426 + RTCH7_LSB,
1.427 + RTCH7_MSB,
1.428 + RTCH8_LSB,
1.429 + RTCH8_MSB,
1.430 + RTCH9_LSB,
1.431 + RTCH9_MSB,
1.432 + RTCH10_LSB,
1.433 + RTCH10_MSB,
1.434 + RTCH11_LSB,
1.435 + RTCH11_MSB,
1.436 + RTCH12_LSB,
1.437 + RTCH12_MSB,
1.438 + RTCH13_LSB,
1.439 + RTCH13_MSB,
1.440 + RTCH14_LSB,
1.441 + RTCH14_MSB,
1.442 + RTCH15_LSB,
1.443 + RTCH15_MSB,
1.444 + GPCH0_LSB,
1.445 + GPCH0_MSB,
1.446 + GPCH1_LSB,
1.447 + GPCH1_MSB,
1.448 + GPCH2_LSB,
1.449 + GPCH2_MSB,
1.450 + GPCH3_LSB,
1.451 + GPCH3_MSB,
1.452 + GPCH4_LSB,
1.453 + GPCH4_MSB,
1.454 + GPCH5_LSB,
1.455 + GPCH5_MSB,
1.456 + GPCH6_LSB,
1.457 + GPCH6_MSB,
1.458 + GPCH7_LSB,
1.459 + GPCH7_MSB,
1.460 + GPCH8_LSB,
1.461 + GPCH8_MSB,
1.462 + GPCH9_LSB,
1.463 + GPCH9_MSB,
1.464 + GPCH10_LSB,
1.465 + GPCH10_MSB,
1.466 + GPCH11_LSB,
1.467 + GPCH11_MSB,
1.468 + GPCH12_LSB,
1.469 + GPCH12_MSB,
1.470 + GPCH13_LSB,
1.471 + GPCH13_MSB,
1.472 + GPCH14_LSB,
1.473 + GPCH14_MSB,
1.474 + GPCH15_LSB,
1.475 + GPCH15_MSB,
1.476 + BCICH0_LSB,
1.477 + BCICH0_MSB,
1.478 + BCICH1_LSB,
1.479 + BCICH1_MSB,
1.480 + BCICH2_LSB,
1.481 + BCICH2_MSB,
1.482 + BCICH3_LSB,
1.483 + BCICH3_MSB,
1.484 + BCICH4_LSB,
1.485 + BCICH4_MSB,
1.486 + MADC_ISR1,
1.487 + MADC_IMR1,
1.488 + MADC_ISR2,
1.489 + MADC_IMR2,
1.490 + MADC_SIR,
1.491 + MADC_EDR,
1.492 + MADC_SIH_CTRL,
1.493 + BCIMDEN,
1.494 + BCIMDKEY,
1.495 + BCIMSTATEC,
1.496 + BCIMSTATEP,
1.497 + BCIVBAT1,
1.498 + BCIVBAT2,
1.499 + BCITBAT1,
1.500 + BCITBAT2,
1.501 + BCIICHG1,
1.502 + BCIICHG2,
1.503 + BCIVAC1,
1.504 + BCIVAC2,
1.505 + BCIVBUS1,
1.506 + BCIVBUS2,
1.507 + BCIMFSTS2,
1.508 + BCIMFSTS3,
1.509 + BCIMFSTS4,
1.510 + BCIMFKEY,
1.511 + BCIMFEN1,
1.512 + BCIMFEN2,
1.513 + BCIMFEN3,
1.514 + BCIMFEN4,
1.515 + BCIMFTH1,
1.516 + BCIMFTH2,
1.517 + BCIMFTH3,
1.518 + BCIMFTH4,
1.519 + BCIMFTH5,
1.520 + BCIMFTH6,
1.521 + BCIMFTH7,
1.522 + BCIMFTH8,
1.523 + BCIMFTH9,
1.524 + BCITIMER1,
1.525 + BCITIMER2,
1.526 + BCIWDKEY,
1.527 + BCIWD,
1.528 + BCICTL1,
1.529 + BCICTL2,
1.530 + BCIVREF1,
1.531 + BCIVREF2,
1.532 + BCIIREF1,
1.533 + BCIIREF2,
1.534 + BCIPWM2,
1.535 + BCIPWM1,
1.536 + BCITRIM1,
1.537 + BCITRIM2,
1.538 + BCITRIM3,
1.539 + BCITRIM4,
1.540 + BCIVREFCOMB1,
1.541 + BCIVREFCOMB2,
1.542 + BCIIREFCOMB1,
1.543 + BCIIREFCOMB2,
1.544 +
1.545 + BCIISR1A = EGroup4a + 0x000000B9,
1.546 + BCIISR2A,
1.547 + BCIIMR1A,
1.548 + BCIIMR2A,
1.549 + BCIISR1B,
1.550 + BCIISR2B,
1.551 + BCIIMR1B,
1.552 + BCIIMR2B, //0x000000c0
1.553 +
1.554 + BCIEDR1 = EGroup4a + 0x000000c3,
1.555 + BCIEDR2,
1.556 + BCIEDR3,
1.557 + BCISIHCTRL, // c6
1.558 +
1.559 + KEYP_CTRL_REG = EGroup4a + 0x000000D2,
1.560 + KEY_DEB_REG,
1.561 + LONG_KEY_REG1,
1.562 + LK_PTV_REG,
1.563 + TIME_OUT_REG1,
1.564 + TIME_OUT_REG2,
1.565 + KBC_REG,
1.566 + KBR_REG,
1.567 + KEYP_SMS,
1.568 + FULL_CODE_7_0,
1.569 + FULL_CODE_15_8,
1.570 + FULL_CODE_23_16,
1.571 + FULL_CODE_31_24,
1.572 + FULL_CODE_39_32,
1.573 + FULL_CODE_47_40,
1.574 + FULL_CODE_55_48,
1.575 + FULL_CODE_63_56,
1.576 + KEYP_ISR1,
1.577 + KEYP_IMR1,
1.578 + KEYP_ISR2,
1.579 + KEYP_IMR2,
1.580 + KEYP_SIR,
1.581 + KEYP_EDR,
1.582 + KEYP_SIH_CTRL,
1.583 +
1.584 + LEDEN = EGroup4a + 0x000000EE,
1.585 + PWMAON,
1.586 + PWMAOFF,
1.587 + PWMBON,
1.588 + PWMBOFF,
1.589 +
1.590 + PWM1ON= EGroup4a + 0x000000FB,
1.591 + PWM1OFF,
1.592 + PWM0ON = EGroup4a + 0x000000F8,
1.593 + PWM0OFF,
1.594 + };
1.595 +
1.596 + enum TGroup4bRegisters
1.597 + {
1.598 + SECURED_REG_A = EGroup4b + 0,
1.599 + SECURED_REG_B,
1.600 + SECURED_REG_C,
1.601 + SECURED_REG_D,
1.602 + SECURED_REG_E,
1.603 + SECURED_REG_F,
1.604 + SECURED_REG_G,
1.605 + SECURED_REG_H,
1.606 + SECURED_REG_I,
1.607 + SECURED_REG_J,
1.608 + SECURED_REG_K,
1.609 + SECURED_REG_L,
1.610 + SECURED_REG_M,
1.611 + SECURED_REG_N,
1.612 + SECURED_REG_O,
1.613 + SECURED_REG_P,
1.614 + SECURED_REG_Q,
1.615 + SECURED_REG_R,
1.616 + SECURED_REG_S,
1.617 + SECURED_REG_U,
1.618 + BACKUP_REG_A,
1.619 + BACKUP_REG_B,
1.620 + BACKUP_REG_C,
1.621 + BACKUP_REG_D,
1.622 + BACKUP_REG_E,
1.623 + BACKUP_REG_F,
1.624 + BACKUP_REG_G,
1.625 + BACKUP_REG_H,
1.626 + PWR_ISR1 = EGroup4b + 0x2e,
1.627 + PWR_IMR1,
1.628 + PWR_ISR2,
1.629 + PWR_IMR2,
1.630 + PWR_SIR,
1.631 + PWR_EDR1,
1.632 + PWR_EDR2,
1.633 + PWR_SIH_CTRL,
1.634 + CFG_P1_TRANSITION,
1.635 + CFG_P2_TRANSITION,
1.636 + CFG_P3_TRANSITION,
1.637 + CFG_P123_TRANSITION,
1.638 + STS_BOOT,
1.639 + CFG_BOOT,
1.640 + SHUNDAN,
1.641 + BOOT_BCI,
1.642 + CFG_PWRANA1,
1.643 + CFG_PWRANA2,
1.644 + BGAP_TRIM,
1.645 + BACKUP_MISC_STS,
1.646 + BACKUP_MISC_CFG,
1.647 + BACKUP_MISC_TST,
1.648 + PROTECT_KEY,
1.649 + STS_HW_CONDITIONS,
1.650 + P1_SW_EVENTS,
1.651 + P2_SW_EVENTS,
1.652 + P3_SW_EVENTS,
1.653 + STS_P123_STATE,
1.654 + PB_CFG,
1.655 + PB_WORD_MSB,
1.656 + PB_WORD_LSB,
1.657 + RESERVED_A,
1.658 + RESERVED_B,
1.659 + RESERVED_C,
1.660 + RESERVED_D,
1.661 + RESERVED_E,
1.662 + SEQ_ADD_W2P,
1.663 + SEQ_ADD_P2A,
1.664 + SEQ_ADD_A2W,
1.665 + SEQ_ADD_A2S,
1.666 + SEQ_ADD_S2A12,
1.667 + SEQ_ADD_S2A3,
1.668 + SEQ_ADD_WARM,
1.669 + MEMORY_ADDRESS,
1.670 + MEMORY_DATA,
1.671 + SC_CONFIG,
1.672 + SC_DETECT1,
1.673 + SC_DETECT2,
1.674 + WATCHDOG_CFG,
1.675 + IT_CHECK_CFG,
1.676 + VIBRATOR_CFG,
1.677 + DCDC_GLOBAL_CFG,
1.678 + VDD1_TRIM1,
1.679 + VDD1_TRIM2,
1.680 + VDD2_TRIM1,
1.681 + VDD2_TRIM2,
1.682 + VIO_TRIM1,
1.683 + VIO_TRIM2,
1.684 + MISC_CFG,
1.685 + LS_TST_A,
1.686 + LS_TST_B,
1.687 + LS_TST_C,
1.688 + LS_TST_D,
1.689 + BB_CFG,
1.690 + MISC_TST,
1.691 + TRIM1,
1.692 + TRIM2,
1.693 + DCDC_TIMEOUT,
1.694 + VAUX1_DEV_GRP,
1.695 + VAUX1_TYPE,
1.696 + VAUX1_REMAP,
1.697 + VAUX1_DEDICATED,
1.698 + VAUX2_DEV_GRP,
1.699 + VAUX2_TYPE,
1.700 + VAUX2_REMAP,
1.701 + VAUX2_DEDICATED,
1.702 + VAUX3_DEV_GRP,
1.703 + VAUX3_TYPE,
1.704 + VAUX3_REMAP,
1.705 + VAUX3_DEDICATED,
1.706 + VAUX4_DEV_GRP,
1.707 + VAUX4_TYPE,
1.708 + VAUX4_REMAP,
1.709 + VAUX4_DEDICATED,
1.710 + VMMC1_DEV_GRP,
1.711 + VMMC1_TYPE,
1.712 + VMMC1_REMAP,
1.713 + VMMC1_DEDICATED,
1.714 + VMMC2_DEV_GRP,
1.715 + VMMC2_TYPE,
1.716 + VMMC2_REMAP,
1.717 + VMMC2_DEDICATED,
1.718 + VPLL1_DEV_GRP,
1.719 + VPLL1_TYPE,
1.720 + VPLL1_REMAP,
1.721 + VPLL1_DEDICATED,
1.722 + VPLL2_DEV_GRP,
1.723 + VPLL2_TYPE,
1.724 + VPLL2_REMAP,
1.725 + VPLL2_DEDICATED,
1.726 + VSIM_DEV_GRP,
1.727 + VSIM_TYPE,
1.728 + VSIM_REMAP,
1.729 + VSIM_DEDICATED,
1.730 + VDAC_DEV_GRP,
1.731 + VDAC_TYPE,
1.732 + VDAC_REMAP,
1.733 + VDAC_DEDICATED,
1.734 + VINTANA1_DEV_GRP,
1.735 + VINTANA1_TYPE,
1.736 + VINTANA1_REMAP,
1.737 + VINTANA1_DEDICATED,
1.738 + VINTANA2_DEV_GRP,
1.739 + VINTANA2_TYPE,
1.740 + VINTANA2_REMAP,
1.741 + VINTANA2_DEDICATED,
1.742 + VINTDIG_DEV_GRP,
1.743 + VINTDIG_TYPE,
1.744 + VINTDIG_REMAP,
1.745 + VINTDIG_DEDICATED,
1.746 + VIO_DEV_GRP,
1.747 + VIO_TYPE,
1.748 + VIO_REMAP,
1.749 + VIO_CFG,
1.750 + VIO_MISC_CFG,
1.751 + VIO_TEST1,
1.752 + VIO_TEST2,
1.753 + VIO_OSC,
1.754 + VIO_RESERVED,
1.755 + VIO_VSEL,
1.756 + VDD1_DEV_GRP,
1.757 + VDD1_TYPE,
1.758 + VDD1_REMAP,
1.759 + VDD1_CFG,
1.760 + VDD1_MISC_CFG,
1.761 + VDD1_TEST1,
1.762 + VDD1_TEST2,
1.763 + VDD1_OSC,
1.764 + VDD1_RESERVED,
1.765 + VDD1_VSEL,
1.766 + VDD1_VMODE_CFG,
1.767 + VDD1_VFLOOR,
1.768 + VDD1_VROOF,
1.769 + VDD1_STEP,
1.770 + VDD2_DEV_GRP,
1.771 + VDD2_TYPE,
1.772 + VDD2_REMAP,
1.773 + VDD2_CFG,
1.774 + VDD2_MISC_CFG,
1.775 + VDD2_TEST1,
1.776 + VDD2_TEST2,
1.777 + VDD2_OSC,
1.778 + VDD2_RESERVED,
1.779 + VDD2_VSEL,
1.780 + VDD2_VMODE_CFG,
1.781 + VDD2_VFLOOR,
1.782 + VDD2_VROOF,
1.783 + VDD2_STEP,
1.784 + VUSB1V5_DEV_GRP,
1.785 + VUSB1V5_TYPE,
1.786 + VUSB1V5_REMAP,
1.787 + VUSB1V8_DEV_GRP,
1.788 + VUSB1V8_TYPE,
1.789 + VUSB1V8_REMAP,
1.790 + VUSB3V1_DEV_GRP,
1.791 + VUSB3V1_TYPE,
1.792 + VUSB3V1_REMAP,
1.793 + VUSBCP_DEV_GRP,
1.794 + VUSBCP_TYPE,
1.795 + VUSBCP_REMAP,
1.796 + VUSB_DEDICATED1,
1.797 + VUSB_DEDICATED2,
1.798 + REGEN_DEV_GRP,
1.799 + REGEN_TYPE,
1.800 + REGEN_REMAP,
1.801 + NRESPWRON_DEV_GRP,
1.802 + NRESPWRON_TYPE,
1.803 + NRESPWRON_REMAP,
1.804 + CLKEN_DEV_GRP,
1.805 + CLKEN_TYPE,
1.806 + CLKEN_REMAP,
1.807 + SYSEN_DEV_GRP,
1.808 + SYSEN_TYPE,
1.809 + SYSEN_REMAP,
1.810 + HFCLKOUT_DEV_GRP,
1.811 + HFCLKOUT_TYPE,
1.812 + HFCLKOUT_REMAP,
1.813 + E32KCLKOUT_DEV_GRP,
1.814 + E32KCLKOUT_TYPE,
1.815 + E32KCLKOUT_REMAP,
1.816 + TRITON_RESET_DEV_GRP,
1.817 + TRITON_RESET_TYPE,
1.818 + TRITON_RESET_REMAP,
1.819 + MAINREF_DEV_GRP,
1.820 + MAINREF_TYPE,
1.821 + MAINREF_REMAP,
1.822 + SECONDS_REG,
1.823 + MINUTES_REG,
1.824 + HOURS_REG,
1.825 + DAYS_REG,
1.826 + MONTHS_REG,
1.827 + YEARS_REG,
1.828 + WEEKS_REG,
1.829 + ALARM_SECONDS_REG,
1.830 + ALARM_MINUTES_REG,
1.831 + ALARM_HOURS_REG,
1.832 + ALARM_DAYS_REG,
1.833 + ALARM_MONTHS_REG,
1.834 + ALARM_YEARS_REG,
1.835 + RTC_CTRL_REG,
1.836 + RTC_STATUS_REG,
1.837 + RTC_INTERRUPTS_REG,
1.838 + RTC_COMP_LSB_REG,
1.839 + RTC_COMP_MSB_REG, //2d
1.840 + };
1.841 + } // namespace Register
1.842 +
1.843 + namespace DCDC_GLOBAL_CFG
1.844 + {
1.845 + const TUint16 Addr = Register::DCDC_GLOBAL_CFG;
1.846 +
1.847 + const TUint8 CARD_DETECT_2_LEVEL = KBit7;
1.848 + const TUint8 CARD_DETECT_1_LEVEL = KBit6;
1.849 + const TUint8 REGEN_PU_DISABLE = KBit5;
1.850 + const TUint8 SYSEN_PU_DISABLE = KBit4;
1.851 + const TUint8 SMARTREFLEX_ENABLE = KBit3;
1.852 + const TUint8 CARD_DETECT_CFG = KBit2;
1.853 + const TUint8 CLK_32K_DEGATE = KBit1;
1.854 + const TUint8 CLK_HF_DEGATE = KBit0;
1.855 + };
1.856 +
1.857 +
1.858 + namespace _VMODE_CFG_
1.859 + {
1.860 + const TUint8 STS_BUSY = KBit5;
1.861 + const TUint8 STS_ROOF = KBit4;
1.862 + const TUint8 STS_FLOOR = KBit3;
1.863 + const TUint8 DCDC_SLP = KBit2;
1.864 + const TUint8 READ_REG = KBit1;
1.865 + const TUint8 ENABLE_VMODE = KBit0;
1.866 + }
1.867 +
1.868 + namespace VDD1_VMODE_CFG
1.869 + {
1.870 + const TUint16 Addr = Register::VDD1_VMODE_CFG;
1.871 + using namespace _VMODE_CFG_;
1.872 + };
1.873 +
1.874 + namespace VDD2_VMODE_CFG
1.875 + {
1.876 + const TUint16 Addr = Register::VDD2_VMODE_CFG;
1.877 + using namespace _VMODE_CFG_;
1.878 + };
1.879 +
1.880 + namespace _VDDx_VSEL_
1.881 + {
1.882 + namespace Mask
1.883 + {
1.884 + const TUint8 VSEL = 0x7F;
1.885 + }
1.886 +
1.887 + namespace Shift
1.888 + {
1.889 + const TUint VSEL = 0;
1.890 + }
1.891 + }
1.892 +
1.893 + namespace VDD1_VSEL
1.894 + {
1.895 + const TUint16 Addr = Register::VDD1_VSEL;
1.896 + using namespace _VDDx_VSEL_;
1.897 + };
1.898 +
1.899 + namespace VDD2_VSEL
1.900 + {
1.901 + const TUint16 Addr = Register::VDD2_VSEL;
1.902 + using namespace _VDDx_VSEL_;
1.903 + };
1.904 +
1.905 + namespace _PWR_I_1_
1.906 + {
1.907 + const TUint8 PWR_SC_DETECT = KBit7;
1.908 + const TUint8 PWR_MBCHG = KBit6;
1.909 + const TUint8 PWR_PWROK_TIMEOUT = KBit5;
1.910 + const TUint8 PWR_HOT_DIE = KBit4;
1.911 + const TUint8 PWR_RTC_IT = KBit3;
1.912 + const TUint8 PWR_USB_PRES = KBit2;
1.913 + const TUint8 PWR_CHG_PRES = KBit1;
1.914 + const TUint8 PWR_CHG_PWRONS = KBit0;
1.915 + }
1.916 +
1.917 + namespace PWR_IMR1
1.918 + {
1.919 + const TUint16 Addr = Register::PWR_IMR1;
1.920 + using namespace _PWR_I_1_;
1.921 + }
1.922 +
1.923 + namespace PWR_ISR1
1.924 + {
1.925 + const TUint16 Addr = Register::PWR_ISR1;
1.926 + using namespace _PWR_I_1_;
1.927 + }
1.928 +
1.929 + namespace _MADC_I_1_
1.930 + {
1.931 + const TUint8 MADC_USB_ISR1 = KBit3;
1.932 + const TUint8 MADC_SW2_ISR1 = KBit2;
1.933 + const TUint8 MADC_SW1_ISR1 = KBit1;
1.934 + const TUint8 MADC_RT_ISR1 = KBit0;
1.935 + }
1.936 +
1.937 + namespace MADC_IMR1
1.938 + {
1.939 + const TUint16 Addr = Register::MADC_IMR1;
1.940 + using namespace _MADC_I_1_;
1.941 + }
1.942 +
1.943 + namespace MADC_ISR1
1.944 + {
1.945 + const TUint16 Addr = Register::MADC_ISR1;
1.946 + using namespace _MADC_I_1_;
1.947 + }
1.948 +
1.949 + namespace _GPIO_I_1A_
1.950 + {
1.951 + const TUint8 GPIO7ISR1 = KBit7;
1.952 + const TUint8 GPIO6ISR1 = KBit6;
1.953 + const TUint8 GPIO5ISR1 = KBit5;
1.954 + const TUint8 GPIO4ISR1 = KBit4;
1.955 + const TUint8 GPIO3ISR1 = KBit3;
1.956 + const TUint8 GPIO2ISR1 = KBit2;
1.957 + const TUint8 GPIO1ISR1 = KBit1;
1.958 + const TUint8 GPIO0ISR1 = KBit0;
1.959 + }
1.960 +
1.961 + namespace _GPIO_I_2A_
1.962 + {
1.963 + const TUint8 GPIO15ISR2 = KBit7;
1.964 + const TUint8 GPIO14ISR2 = KBit6;
1.965 + const TUint8 GPIO13ISR2 = KBit5;
1.966 + const TUint8 GPIO12ISR2 = KBit4;
1.967 + const TUint8 GPIO11ISR2 = KBit3;
1.968 + const TUint8 GPIO10ISR2 = KBit2;
1.969 + const TUint8 GPIO9ISR2 = KBit1;
1.970 + const TUint8 GPIO8ISR2 = KBit0;
1.971 + }
1.972 +
1.973 + namespace _GPIO_I_3A_
1.974 + {
1.975 + const TUint8 GPIO17ISR3 = KBit1;
1.976 + const TUint8 GPIO16ISR3 = KBit0;
1.977 + }
1.978 +
1.979 + namespace GPIO_IMR1A
1.980 + {
1.981 + const TUint16 Addr = Register::GPIO_IMR1A;
1.982 + using namespace _GPIO_I_1A_;
1.983 + }
1.984 +
1.985 + namespace GPIO_ISR1A
1.986 + {
1.987 + const TUint16 Addr = Register::GPIO_ISR1A;
1.988 + using namespace _GPIO_I_1A_;
1.989 + }
1.990 +
1.991 + namespace GPIO_IMR2A
1.992 + {
1.993 + const TUint16 Addr = Register::GPIO_IMR2A;
1.994 + using namespace _GPIO_I_2A_;
1.995 + }
1.996 +
1.997 + namespace GPIO_ISR2A
1.998 + {
1.999 + const TUint16 Addr = Register::GPIO_ISR2A;
1.1000 + using namespace _GPIO_I_2A_;
1.1001 + }
1.1002 +
1.1003 + namespace GPIO_IMR3A
1.1004 + {
1.1005 + const TUint16 Addr = Register::GPIO_IMR3A;
1.1006 + using namespace _GPIO_I_3A_;
1.1007 + }
1.1008 +
1.1009 + namespace GPIO_ISR3A
1.1010 + {
1.1011 + const TUint16 Addr = Register::GPIO_ISR3A;
1.1012 + using namespace _GPIO_I_3A_;
1.1013 + }
1.1014 +
1.1015 + namespace _BCI_I_1_
1.1016 + {
1.1017 + const TUint8 BCI_BATSTS_ISR1 = KBit7;
1.1018 + const TUint8 BCI_TBATOR1_ISR1 = KBit6;
1.1019 + const TUint8 BCI_TBATOR2_ISR1 = KBit5;
1.1020 + const TUint8 BCI_ICHGEOC_ISR1 = KBit4;
1.1021 + const TUint8 BCI_ICHGLOW_ISR1ASTO = KBit3;
1.1022 + const TUint8 BCI_IICHGHIGH_ISR1 = KBit2;
1.1023 + const TUint8 BCI_TMOVF_ISR1 = KBit1;
1.1024 + const TUint8 BCI_WOVF_ISR1 = KBit0;
1.1025 + }
1.1026 +
1.1027 + namespace _BCI_I_2_
1.1028 + {
1.1029 + const TUint8 BCI_ACCHGOV_ISR1 = KBit3;
1.1030 + const TUint8 BCI_VBUSOV_ISR1 = KBit2;
1.1031 + const TUint8 BCI_VBATOV_ISR1 = KBit1;
1.1032 + const TUint8 BCI_VBATLVL_ISR1 = KBit0;
1.1033 + }
1.1034 +
1.1035 + namespace BCIIMR1A
1.1036 + {
1.1037 + const TUint16 Addr = Register::BCIIMR1A;
1.1038 + using namespace _BCI_I_1_;
1.1039 + }
1.1040 +
1.1041 + namespace BCIISR1A
1.1042 + {
1.1043 + const TUint16 Addr = Register::BCIISR1A;
1.1044 + using namespace _BCI_I_1_;
1.1045 + }
1.1046 +
1.1047 + namespace BCIIMR2A
1.1048 + {
1.1049 + const TUint16 Addr = Register::BCIIMR2A;
1.1050 + using namespace _BCI_I_2_;
1.1051 + }
1.1052 +
1.1053 + namespace BCIISR2A
1.1054 + {
1.1055 + const TUint16 Addr = Register::BCIISR2A;
1.1056 + using namespace _BCI_I_2_;
1.1057 + }
1.1058 +
1.1059 + namespace _KEYP_I_
1.1060 + {
1.1061 + const TUint8 KEYP_ITMISR1 = KBit3;
1.1062 + const TUint8 KEYP_ITTOISR1 = KBit2;
1.1063 + const TUint8 KEYP_ITLKISR1 = KBit1;
1.1064 + const TUint8 KEYP_ITKPISR1 = KBit0;
1.1065 + }
1.1066 +
1.1067 + namespace KEYP_IMR1
1.1068 + {
1.1069 + const TUint16 Addr = Register::KEYP_IMR1;
1.1070 + using namespace _KEYP_I_;
1.1071 + }
1.1072 +
1.1073 + namespace KEYP_ISR1
1.1074 + {
1.1075 + const TUint16 Addr = Register::KEYP_ISR1;
1.1076 + using namespace _KEYP_I_;
1.1077 + }
1.1078 +
1.1079 + namespace _USB_INT_EN_
1.1080 + {
1.1081 + const TUint8 USB_INTSTS_IDGND = KBit4;
1.1082 + const TUint8 USB_INTSTS_SESSEND = KBit3;
1.1083 + const TUint8 USB_INTSTS_SESSVALID = KBit2;
1.1084 + const TUint8 USB_INTSTS_VBUSVALID = KBit1;
1.1085 + const TUint8 USB_INTSTS_HOSTDISCONNECT = KBit0;
1.1086 + }
1.1087 +
1.1088 + namespace USB_INT_EN_RISE_SET
1.1089 + {
1.1090 + const TUint16 Addr = Register::USB_INT_EN_RISE_SET;
1.1091 + using namespace _USB_INT_EN_;
1.1092 + }
1.1093 +
1.1094 + namespace USB_INT_EN_RISE_CLR
1.1095 + {
1.1096 + const TUint16 Addr = Register::USB_INT_EN_RISE_CLR;
1.1097 + using namespace _USB_INT_EN_;
1.1098 + }
1.1099 +
1.1100 + namespace USB_INT_STS
1.1101 + {
1.1102 + const TUint16 Addr = Register::USB_INT_STS;
1.1103 + using namespace _USB_INT_EN_;
1.1104 + }
1.1105 +
1.1106 + namespace _OTHER_INT_
1.1107 + {
1.1108 + const TUint8 OTHER_INT_VB_SESS_VLD = KBit7;
1.1109 + const TUint8 OTHER_INT_DM_HI = KBit6;
1.1110 + const TUint8 OTHER_INT_DP_HI = KBit5;
1.1111 + const TUint8 OTHER_INT_MANU = KBit1;
1.1112 + const TUint8 OTHER_INT_ABNORMAL_STRESS = KBit0;
1.1113 + }
1.1114 +
1.1115 + namespace OTHER_INT_EN_RISE_SET
1.1116 + {
1.1117 + const TUint16 Addr = Register::OTHER_INT_EN_RISE_SET;
1.1118 + using namespace _OTHER_INT_;
1.1119 + }
1.1120 +
1.1121 + namespace OTHER_INT_EN_RISE_CLR
1.1122 + {
1.1123 + const TUint16 Addr = Register::OTHER_INT_EN_RISE_CLR;
1.1124 + using namespace _OTHER_INT_;
1.1125 + }
1.1126 +
1.1127 + namespace OTHER_INT_STS
1.1128 + {
1.1129 + const TUint16 Addr = Register::OTHER_INT_STS;
1.1130 + using namespace _OTHER_INT_;
1.1131 + }
1.1132 +
1.1133 + namespace _CARKIT_INT_
1.1134 + {
1.1135 + const TUint8 CARKIT_CARDP = KBit2;
1.1136 + const TUint8 CARKIT_CARINTDET = KBit1;
1.1137 + const TUint8 CARKIT_IDFLOAT = KBit0;
1.1138 + }
1.1139 +
1.1140 + namespace CARKIT_INT_EN_SET
1.1141 + {
1.1142 + const TUint16 Addr = Register::CARKIT_INT_EN_SET;
1.1143 + using namespace _CARKIT_INT_;
1.1144 + }
1.1145 +
1.1146 + namespace CARKIT_INT_EN_CLR
1.1147 + {
1.1148 + const TUint16 Addr = Register::CARKIT_INT_EN_CLR;
1.1149 + using namespace _CARKIT_INT_;
1.1150 + }
1.1151 +
1.1152 + namespace CARKIT_INT_STS
1.1153 + {
1.1154 + const TUint16 Addr = Register::CARKIT_INT_STS;
1.1155 + using namespace _CARKIT_INT_;
1.1156 + }
1.1157 +
1.1158 + namespace _ID_INT_
1.1159 + {
1.1160 + const TUint8 ID_INTID_RES_FLOAT = KBit3;
1.1161 + const TUint8 ID_INTID_RES_440K = KBit2;
1.1162 + const TUint8 ID_INTID_RES_200K = KBit1;
1.1163 + const TUint8 ID_INTID_RES_102K = KBit0;
1.1164 + }
1.1165 +
1.1166 + namespace ID_INT_EN_RISE_SET
1.1167 + {
1.1168 + const TUint16 Addr = Register::ID_INT_EN_RISE_SET;
1.1169 + using namespace _ID_INT_;
1.1170 + }
1.1171 +
1.1172 + namespace ID_INT_EN_RISE_CLR
1.1173 + {
1.1174 + const TUint16 Addr = Register::ID_INT_EN_RISE_CLR;
1.1175 + using namespace _ID_INT_;
1.1176 + }
1.1177 +
1.1178 + namespace ID_INT_STS
1.1179 + {
1.1180 + const TUint16 Addr = Register::ID_INT_STS;
1.1181 + using namespace _ID_INT_;
1.1182 + }
1.1183 +
1.1184 + namespace _CARKIT_SM_1_INT_
1.1185 + {
1.1186 + const TUint8 CARKIT_SM_1_PSM_ERROR = KBit6;
1.1187 + const TUint8 CARKIT_SM_1_PH_ACC = KBit5;
1.1188 + const TUint8 CARKIT_SM_1_CHARGER = KBit4;
1.1189 + const TUint8 CARKIT_SM_1_USB_HOST = KBit3;
1.1190 + const TUint8 CARKIT_SM_1_USB_OTG_B = KBit2;
1.1191 + const TUint8 CARKIT_SM_1_CARKIT = KBit1;
1.1192 + const TUint8 CARKIT_SM_1_DISCONNECTED = KBit0;
1.1193 + }
1.1194 +
1.1195 + namespace _CARKIT_SM_2_INT_
1.1196 + {
1.1197 + const TUint8 CARKIT_SM_2_STOP_PLS_MISS = KBit7;
1.1198 + const TUint8 CARKIT_SM_2_STEREO_TO_MONO = KBit3;
1.1199 + const TUint8 CARKIT_SM_2_PHONE_UART = KBit1;
1.1200 + const TUint8 CARKIT_SM_2_PH_NO_ACK = KBit0;
1.1201 + }
1.1202 +
1.1203 + namespace CARKIT_SM_1_INT_EN_SET
1.1204 + {
1.1205 + const TUint16 Addr = Register::CARKIT_SM_1_INT_EN_SET;
1.1206 + using namespace _CARKIT_SM_1_INT_;
1.1207 + }
1.1208 +
1.1209 + namespace CARKIT_SM_1_INT_EN_CLR
1.1210 + {
1.1211 + const TUint16 Addr = Register::CARKIT_SM_1_INT_EN_CLR;
1.1212 + using namespace _CARKIT_SM_1_INT_;
1.1213 + }
1.1214 +
1.1215 + namespace CARKIT_SM_1_INT_STS
1.1216 + {
1.1217 + const TUint16 Addr = Register::CARKIT_SM_1_INT_STS;
1.1218 + using namespace _CARKIT_SM_1_INT_;
1.1219 + }
1.1220 +
1.1221 + namespace CARKIT_SM_2_INT_EN_SET
1.1222 + {
1.1223 + const TUint16 Addr = Register::CARKIT_SM_2_INT_EN_SET;
1.1224 + using namespace _CARKIT_SM_2_INT_;
1.1225 + }
1.1226 +
1.1227 + namespace CARKIT_SM_2_INT_EN_CLR
1.1228 + {
1.1229 + const TUint16 Addr = Register::CARKIT_SM_2_INT_EN_CLR;
1.1230 + using namespace _CARKIT_SM_2_INT_;
1.1231 + }
1.1232 +
1.1233 + namespace CARKIT_SM_2_INT_STS
1.1234 + {
1.1235 + const TUint16 Addr = Register::CARKIT_SM_2_INT_STS;
1.1236 + using namespace _CARKIT_SM_2_INT_;
1.1237 + }
1.1238 +
1.1239 + namespace _PIH_
1.1240 + {
1.1241 + const TUint8 PIH_PWR_INT = KBit5;
1.1242 + const TUint8 PIH_USB_INT = KBit4;
1.1243 + const TUint8 PIH_MADC_INT = KBit3;
1.1244 + const TUint8 PIH_BCI_INT = KBit2;
1.1245 + const TUint8 PIH_KEYP_INT = KBit1;
1.1246 + const TUint8 PIH_GPIO_INT = KBit0;
1.1247 + }
1.1248 +
1.1249 + namespace PIH_ISR_P1
1.1250 + {
1.1251 + const TUint Addr = Register::PIH_ISR_P1;
1.1252 +
1.1253 + const TUint8 PIH_ISR7 = KBit7;
1.1254 + const TUint8 PIH_ISR6 = KBit6;
1.1255 + const TUint8 PIH_ISR5 = KBit5;
1.1256 + const TUint8 PIH_ISR4 = KBit4;
1.1257 + const TUint8 PIH_ISR3 = KBit3;
1.1258 + const TUint8 PIH_ISR2 = KBit2;
1.1259 + const TUint8 PIH_ISR1 = KBit1;
1.1260 + const TUint8 PIH_ISR0 = KBit0;
1.1261 + }
1.1262 +
1.1263 + namespace _SIH_CTRL_
1.1264 + {
1.1265 + const TUint8 SIH_EXCLEN = KBit0;
1.1266 + const TUint8 SIH_PENDDIS = KBit1;
1.1267 + const TUint8 SIH_COR = KBit2;
1.1268 + }
1.1269 +
1.1270 + namespace GPIO_SIH_CTRL
1.1271 + {
1.1272 + const TUint16 Addr = Register::GPIO_SIH_CTRL;
1.1273 + using namespace _SIH_CTRL_;
1.1274 + }
1.1275 +
1.1276 + namespace KEYP_SIH_CTRL
1.1277 + {
1.1278 + const TUint16 Addr = Register::KEYP_SIH_CTRL;
1.1279 + using namespace _SIH_CTRL_;
1.1280 + }
1.1281 +
1.1282 + namespace BCISIHCTRL
1.1283 + {
1.1284 + const TUint16 Addr = Register::BCISIHCTRL;
1.1285 + using namespace _SIH_CTRL_;
1.1286 + }
1.1287 +
1.1288 + namespace MADC_SIH_CTRL
1.1289 + {
1.1290 + const TUint16 Addr = Register::MADC_SIH_CTRL;
1.1291 + using namespace _SIH_CTRL_;
1.1292 + }
1.1293 +
1.1294 + namespace PWR_SIH_CTRL
1.1295 + {
1.1296 + const TUint16 Addr = Register::PWR_SIH_CTRL;
1.1297 + using namespace _SIH_CTRL_;
1.1298 + }
1.1299 +
1.1300 + namespace PROTECT_KEY
1.1301 + {
1.1302 + const TUint16 Addr = Register::PROTECT_KEY;
1.1303 +
1.1304 + const TUint8 KEY_TEST = KBit0;
1.1305 + const TUint8 KEY_CFG = KBit1;
1.1306 + }
1.1307 +
1.1308 + namespace RTC_CTRL_REG
1.1309 + {
1.1310 + const TUint16 Addr = Register::RTC_CTRL_REG;
1.1311 +
1.1312 + const TUint8 STOP_RTC = KBit0;
1.1313 + const TUint8 ROUND_30S = KBit1;
1.1314 + const TUint8 AUTO_COMP = KBit2;
1.1315 + const TUint8 MODE_12_24 = KBit3;
1.1316 + const TUint8 TEST_MODE = KBit4;
1.1317 + const TUint8 SET_32_COUNTER = KBit5;
1.1318 + const TUint8 GET_TIME = KBit6;
1.1319 + }
1.1320 +
1.1321 +} // namespace TPS65950
1.1322 +
1.1323 +#endif // define TPS65950_REGISTERS_H