1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/epoc32/include/assp/omap3530_assp/omap3530_timer.h Wed Mar 31 12:33:34 2010 +0100
1.3 @@ -0,0 +1,817 @@
1.4 +// Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// /omap3530/assp/inc/omap3530_timer.h
1.18 +//
1.19 +
1.20 +#ifndef HEADER_OMAP3530_TIMER_H_INCLUDED
1.21 +# define HEADER_OMAP3530_TIMER_H_INCLUDED
1.22 +
1.23 +/**
1.24 +@file
1.25 + omap3530_timer.h header file
1.26 +This file provides timer handling for the omap3530 timers
1.27 +@publishedAll
1.28 +@released
1.29 +*/
1.30 +
1.31 +#include <assp/omap3530_assp/omap3530_hardware_base.h>
1.32 +#include <assp/omap3530_assp/omap3530_irqmap.h>
1.33 +
1.34 +namespace TexasInstruments
1.35 + {
1.36 +
1.37 + namespace Omap3530
1.38 + {
1.39 +
1.40 +
1.41 + namespace GPTimer
1.42 + {
1.43 +
1.44 + namespace TIOCP_CFG
1.45 + {
1.46 + /**
1.47 + 0 AUTOIDLE Internal L4 interface clock gating strategy 0
1.48 + 0x0: L4 interface clock is free-running.
1.49 + 0x1: Automatic L4 interface clock gating strategy isapplied, based on the L4 interface activity.
1.50 + */
1.51 + typedef TSingleBitField<0> T_AUTOIDLE ;
1.52 +
1.53 + /**
1.54 + 1 SOFTRESET Software reset. This bit is automatically reset by the RW 0 hardware. During reads, it always returns 0.
1.55 + 0x0: Normal mode
1.56 + 0x1: The module is reset.
1.57 + */
1.58 + typedef TSingleBitField<1> T_SOFTRESET ;
1.59 +
1.60 + /**
1.61 + 2 ENAWAKEUP Wake-up feature global control RW 0
1.62 + 0x0: No wake-up line assertion in idle mode
1.63 + 0x1: Wake-up line assertion enabled in smart-idle mode
1.64 + */
1.65 + typedef TSingleBitField<2> T_ENAWAKEUP ;
1.66 +
1.67 + /**
1.68 + 4:3 IDLEMODE Power management, req/ack control RW 0x0
1.69 + 0x0: Force-idle. An idle request is acknowledged unconditionally.
1.70 + 0x1: No-idle. An idle request is never acknowledged.
1.71 + 0x2: Smart-idle. Acknowledgement to an idle request is given based on the internal activity of the module.
1.72 + 0x3: Reserved. Do not use.
1.73 + */
1.74 + class T_IDLEMODE : public TBitField<3, 2>
1.75 + {
1.76 + public :
1.77 + enum TConstants
1.78 + {
1.79 + KForceIdle = TConstVal<0>::KValue,
1.80 + KNoIdle = TConstVal<1>::KValue,
1.81 + KSmartIdle = TConstVal<2>::KValue
1.82 + } ;
1.83 + } ;
1.84 +
1.85 + /**
1.86 + 5 EMUFREE Emulation mode RW 0
1.87 + 0x0: Timer counter frozen in emulation
1.88 + 0x1: Timer counter free-running in emulation
1.89 + */
1.90 + typedef TSingleBitField<5> T_EMUFREE ;
1.91 +
1.92 + /**
1.93 + 9:8 CLOCKACTIVITY Clock activity during wakeup mode period: RW 0x0
1.94 + 0x0: L4 interface and Functional clocks can be switched off.
1.95 + 0x1: L4 interface clock is maintained during wake-up period; Functional clock can be switched off.
1.96 + 0x2: L4 interface clock can be switched off; Functional clock is maintained during wake-up period.
1.97 + 0x3: L4 interface and Functional clocks are maintained during wake-up period.
1.98 + */
1.99 + class T_CLOCKACTIVITY : public TBitField<8, 2>
1.100 + {
1.101 + public :
1.102 + enum TConstants
1.103 + {
1.104 + KMaintainNeither = TConstVal<0>::KValue,
1.105 + KMaintainIfClock = TConstVal<1>::KValue,
1.106 + KMaintainFuncClock = TConstVal<2>::KValue,
1.107 + KMaintainBoth = TConstVal<3>::KValue
1.108 + } ;
1.109 + } ;
1.110 +
1.111 + } ; // namespace TIOCP_CFG
1.112 +
1.113 + namespace TISTAT
1.114 + {
1.115 + /**
1.116 + 0 RESETDONE Internal reset monitoring R 0
1.117 + 0x0: Internal module reset is ongoing.
1.118 + 0x1: Reset completed
1.119 + */
1.120 + typedef TSingleBitField<0> T_RESETDONE ;
1.121 +
1.122 + } ; // namespace TISTAT
1.123 +
1.124 + namespace TISR
1.125 + {
1.126 + /**
1.127 + 0 MAT_IT_FLAG Pending match interrupt status RW 0
1.128 + Read 0x0: No match interrupt pending
1.129 + Write 0x0: Status unchanged
1.130 + Read 0x1: Match interrupt pending
1.131 + Write 0x1: Status bit cleared
1.132 + */
1.133 + typedef TSingleBitField<0> T_MAT_IT_FLAG ;
1.134 +
1.135 + /**
1.136 + 1 OVF_IT_FLAG Pending overflow interrupt status RW 0
1.137 + Read 0x0: No overflow interrupt pending
1.138 + Write 0x0: Status unchanged
1.139 + Read 0x1: Overflow interrupt pending
1.140 + Write 0x1: Status bit cleared
1.141 + */
1.142 + typedef TSingleBitField<1> T_OVF_IT_FLAG ;
1.143 +
1.144 + /**
1.145 + 2 TCAR_IT_FLAG Pending capture interrupt status RW 0
1.146 + Read 0x0: No capture interrupt event pending
1.147 + Write 0x0: Status unchanged
1.148 + Read 0x1: Capture interrupt event pending
1.149 + Write 0x1: Status bit cleared
1.150 + */
1.151 + typedef TSingleBitField<2> T_TCAR_IT_FLAG ;
1.152 +
1.153 + } ; // namespace TISR
1.154 +
1.155 + namespace TIER
1.156 + {
1.157 + /**
1.158 + 0 MAT_IT_ENA Enable match interrupt RW 0
1.159 + 0x0: Disable match interrupt.
1.160 + 0x1: Enable match interrupt.
1.161 + */
1.162 + typedef TSingleBitField<0> T_MAT_IT_ENA ;
1.163 +
1.164 + /**
1.165 + 1 OVF_IT_ENA Enable overflow interrupt RW 0
1.166 + 0x0: Disable overflow interrupt.
1.167 + 0x1: Enable overflow interrupt.
1.168 + */
1.169 + typedef TSingleBitField<1> T_OVF_IT_ENA ;
1.170 +
1.171 + /**
1.172 + 2 TCAR_IT_ENA Enable capture interrupt RW 0
1.173 + 0x0: Disable capture interrupt.
1.174 + 0x1: Enable capture interrupt.
1.175 + */
1.176 + typedef TSingleBitField<2> T_TCAR_IT_ENA ;
1.177 +
1.178 + } ; // namespace TIER
1.179 +
1.180 + namespace TWER
1.181 + {
1.182 + /**
1.183 + 0 MAT_WUP_ENA Enable match wake-up RW 0
1.184 + 0x0: Disable match wake-up.
1.185 + 0x1: Enable match wake-up.
1.186 + */
1.187 + typedef TSingleBitField<0> T_MAT_WUP_ENA ;
1.188 +
1.189 + /**
1.190 + 1 OVF_WUP_ENA Enable overflow wake-up RW 0
1.191 + 0x0: Disable overflow wake-up.
1.192 + 0x1: Enable overflow wake-up.
1.193 + */
1.194 + typedef TSingleBitField<1> T_OVF_WUP_ENA ;
1.195 +
1.196 + /**
1.197 + 2 TCAR_WUP_ENA Enable capture wake-up RW 0
1.198 + 0x0: Disable capture wake-up.
1.199 + 0x1: Enable capture wake-up.
1.200 + */
1.201 + typedef TSingleBitField<2> T_TCAR_WUP_ENA ;
1.202 +
1.203 + } ; // namespace TWER
1.204 +
1.205 + namespace TCLR
1.206 + {
1.207 + /**
1.208 + 0 ST Start/stop timer control RW 0
1.209 + 0x0: Stop the timer
1.210 + 0x1: Start the timer
1.211 + */
1.212 + typedef TSingleBitField<0> T_ST ;
1.213 +
1.214 + /**
1.215 + 1 AR Autoreload mode RW 0
1.216 + 0x0: One-shot mode overflow
1.217 + 0x1: Autoreload mode overflow
1.218 + */
1.219 + typedef TSingleBitField<1> T_AR ;
1.220 +
1.221 + /**
1.222 + 4:2 PTV Trigger output mode
1.223 + 0x0: The timer counter is prescaled with the value: RW 0x0
1.224 + 2(PTV+1). Example: PTV = 3, counter increases value (if started) after 16 functional clock periods.
1.225 + */
1.226 + class T_PTV : public TBitField<2, 3>
1.227 + {
1.228 + public :
1.229 + enum TConstants
1.230 + {
1.231 + KPS_2 = TConstVal<0>::KValue,
1.232 + KPS_4 = TConstVal<1>::KValue,
1.233 + KPS_8 = TConstVal<2>::KValue,
1.234 + KPS_16 = TConstVal<3>::KValue,
1.235 + KPS_32 = TConstVal<4>::KValue,
1.236 + KPS_64 = TConstVal<5>::KValue,
1.237 + KPS_128 = TConstVal<6>::KValue,
1.238 + KPS_256 = TConstVal<7>::KValue
1.239 + } ;
1.240 + } ;
1.241 +
1.242 + /**
1.243 + 5 PRE Prescaler enable RW 0
1.244 + 0x0: Prescaler disabled
1.245 + 0x1: Prescaler enabled
1.246 + */
1.247 + typedef TSingleBitField<5> T_PRE ;
1.248 +
1.249 + /**
1.250 + 6 CE Compare enable RW 0
1.251 + 0x0: Compare disabled
1.252 + 0x1: Compare enabled
1.253 + */
1.254 + typedef TSingleBitField<6> T_CE ;
1.255 +
1.256 + /**
1.257 + 7 SCPWM Pulse-width-modulation output pin default setting when RW 0
1.258 + counter is stopped or trigger output mode is set to no trigger.
1.259 + 0x0: Default value of PWM_out output: 0
1.260 + 0x1: Default value of PWM_out output: 1
1.261 + */
1.262 + typedef TSingleBitField<7> T_SCPWM ;
1.263 +
1.264 + /**
1.265 + 9:8 TCM Transition capture mode RW 0x0
1.266 + 0x0: No capture
1.267 + 0x1: Capture on rising edges of EVENT_CAPTURE pin.
1.268 + 0x2: Capture on falling edges of EVENT_CAPTURE pin.
1.269 + 0x3: Capture on both edges of EVENT_CAPTURE pin.
1.270 + */
1.271 + class T_TCM : public TBitField<8, 2>
1.272 + {
1.273 + public :
1.274 + enum TConstants
1.275 + {
1.276 + KNoCapture = TConstVal<0>::KValue,
1.277 + KRisingEdge = TConstVal<1>::KValue,
1.278 + KFallingEdge = TConstVal<2>::KValue,
1.279 + KBothEdges = TConstVal<3>::KValue
1.280 + } ;
1.281 + } ;
1.282 +
1.283 + /**
1.284 + 11:10 TRG Trigger output mode RW 0x0
1.285 + 0x0: No trigger
1.286 + 0x1: Overflow trigger
1.287 + 0x2: Overflow and match trigger
1.288 + 0x3: Reserved
1.289 + */
1.290 + class T_IDLEMODE : public TBitField<10, 2>
1.291 + {
1.292 + public :
1.293 + enum TConstants
1.294 + {
1.295 + KNoTrigger = TConstVal<0>::KValue,
1.296 + KOverflow = TConstVal<1>::KValue,
1.297 + KOverflowAndMatch = TConstVal<2>::KValue
1.298 + } ;
1.299 + } ;
1.300 +
1.301 + /**
1.302 + 12 PT Pulse or toggle select bit RW 0
1.303 + 0x0: Pulse modulation
1.304 + 0x1: Toggle modulation
1.305 + */
1.306 + typedef TSingleBitField<12> T_PT ;
1.307 +
1.308 + /**
1.309 + 13 CAPT_MODE Capture mode select bit (first/second) RW 0
1.310 + 0x0: Capture the first enabled capture event in TCAR1.
1.311 + 0x1: Capture the second enabled capture event in TCAR2.
1.312 + */
1.313 + typedef TSingleBitField<13> T_CAPT_MODE ;
1.314 +
1.315 + /**
1.316 + 14 GPO_CFG PWM output/event detection input pin direction control: RW 0
1.317 + 0x0: Configures the pin as an output (needed when PWM mode is required)
1.318 + 0x1: Configures the pin as an input (needed when capture mode is required)
1.319 + */
1.320 + typedef TSingleBitField<14> T_GPO_CFG ;
1.321 +
1.322 + } ; // namespace TCLR
1.323 +
1.324 + namespace TWPS
1.325 + {
1.326 + /**
1.327 + 0 W_PEND_TCLR Write pending for register GPT_TCLR R 0
1.328 + 0x0: Control register write not pending
1.329 + 0x1: Control register write pending
1.330 + */
1.331 + typedef TSingleBitField<0> T_W_PEND_TCLR ;
1.332 +
1.333 + /**
1.334 + 1 W_PEND_TCRR Write pending for register GPT_TCRR R 0
1.335 + 0x0: Counter register write not pending
1.336 + 0x1: Counter register write pending
1.337 + */
1.338 + typedef TSingleBitField<1> T_W_PEND_TCRR ;
1.339 +
1.340 + /**
1.341 + 2 W_PEND_TLDR Write pending for register GPT_TLDR R 0
1.342 + 0x0: Load register write not pending
1.343 + 0x1: Load register write pending
1.344 + */
1.345 + typedef TSingleBitField<2> T_W_PEND_TLDR ;
1.346 +
1.347 + /**
1.348 + 3 W_PEND_TTGR Write pending for register GPT_TTGR R 0
1.349 + 0x0: Trigger register write not pending
1.350 + 0x1: Trigger register write pending
1.351 + */
1.352 + typedef TSingleBitField<3> T_W_PEND_TTGR ;
1.353 +
1.354 + /**
1.355 + 4 W_PEND_TMAR Write pending for register GPT_TMAR R 0
1.356 + 0x0: Match register write not pending
1.357 + 0x1: Match register write pending
1.358 + */
1.359 + typedef TSingleBitField<4> T_W_PEND_TMAR;
1.360 +
1.361 + /**
1.362 + 5 W_PEND_TPIR Write pending for register GPT_TPIR R 0
1.363 + Reserved for instances 3, 4, 5, 6, 7, 8, 9, 11, 12 Read returns reset value. R 0
1.364 + 0x0: Positive increment register write not pending
1.365 + 0x1: Positive increment register write pending
1.366 + */
1.367 + typedef TSingleBitField<5> T_W_PEND_TPIR ;
1.368 +
1.369 + /**
1.370 + 6 W_PEND_TNIR Write pending for register GPT_TNIR R 0
1.371 + 0x0: Negative increment register write not pending
1.372 + 0x1: Negative increment register write pending
1.373 + Reserved for instances 3, 4, 5, 6, 7, 8, 9, 11, 12 Read returns reset value. R 0
1.374 + */
1.375 + typedef TSingleBitField<6> T_W_PEND_TNIR ;
1.376 +
1.377 + /**
1.378 + 7 W_PEND_TCVR Write pending for register GPT_TCVR R 0
1.379 + 0x0: Counter value register write not pending
1.380 + 0x1: Counter value register write pending
1.381 + Reserved for instances 3, 4, 5, 6, 7, 8, 9, 11, 12 Read returns reset value. R 0
1.382 + */
1.383 + typedef TSingleBitField<7> T_W_PEND_TCVR ;
1.384 +
1.385 + /**
1.386 + 8 W_PEND_TOCR Write pending for register GPT_TOCR R 0
1.387 + 0x0: Overflow counter register write not pending
1.388 + 0x1: Overflow counter register write pending
1.389 + Reserved for instances 3, 4, 5, 6, 7, 8, 9, 11, 12 Read returns reset value. R 0
1.390 + */
1.391 + typedef TSingleBitField<8> T_W_PEND_TOCR ;
1.392 +
1.393 + /**
1.394 + 9 W_PEND_TOWR Write pending for register GPT_TOWR R 0
1.395 + 0x0: Overflow wrapping register write not pending
1.396 + 0x1: Overflow wrapping register write pending
1.397 + Reserved for instances 3, 4, 5, 6, 7, 8, 9, 11, 12 Read returns reset value. R 0
1.398 + */
1.399 + typedef TSingleBitField<9> T_W_PEND_TOWR ;
1.400 +
1.401 + } ; // namespace TWPS
1.402 +
1.403 + namespace TSICR
1.404 + {
1.405 + /**
1.406 + 1 SFT Reset software functional registers. This bit is automatically reset RW 0
1.407 + by the hardware. During reads, it always returns 0.
1.408 + 0x0: Normal functional mode
1.409 + 0x1: The functional registers are reset.
1.410 + */
1.411 + typedef TSingleBitField<1> T_SFT ;
1.412 +
1.413 + /**
1.414 + 2 POSTED Posted mode selection RW 1
1.415 + 0x0: Non-posted mode selected
1.416 + 0x1: Posted mode selected
1.417 + */
1.418 + typedef TSingleBitField<2> T_POSTED ;
1.419 +
1.420 + } ; // namespace TSICR
1.421 +
1.422 + namespace TOCR
1.423 + {
1.424 + /**
1.425 + 23:0 OVF_COUNTER_VALUE The number of overflow events. RW 0x00000000
1.426 + */
1.427 + class T_OVF_COUNTER_VALUE : public TBitField<0, 24>
1.428 + {
1.429 + public :
1.430 + enum TConstants
1.431 + {
1.432 + } ;
1.433 + } ;
1.434 +
1.435 + } ; // namespace TOCR
1.436 +
1.437 + namespace TOWR
1.438 + {
1.439 + /**
1.440 + 23:0 OVF_WRAPPING_VALUE The number of masked interrupts. RW 0x00000000
1.441 + */
1.442 + class T_OVF_WRAPPING_VALUE : public TBitField<0, 24>
1.443 + {
1.444 + public :
1.445 + enum TConstants
1.446 + {
1.447 + } ;
1.448 + } ;
1.449 +
1.450 + } ; // namespace TOWR
1.451 +
1.452 + enum TBaseAddress
1.453 + {
1.454 + KGPTIMER1_Base = TVirtual<0x48318000>::Value,
1.455 + KGPTIMER2_Base = TVirtual<0x49032000>::Value,
1.456 + KGPTIMER3_Base = TVirtual<0x49034000>::Value,
1.457 + KGPTIMER4_Base = TVirtual<0x49036000>::Value,
1.458 + KGPTIMER5_Base = TVirtual<0x49038000>::Value,
1.459 + KGPTIMER6_Base = TVirtual<0x4903A000>::Value,
1.460 + KGPTIMER7_Base = TVirtual<0x4903C000>::Value,
1.461 + KGPTIMER8_Base = TVirtual<0x4903E000>::Value,
1.462 + KGPTIMER9_Base = TVirtual<0x49040000>::Value,
1.463 + KGPTIMER10_Base = TVirtual<0x48086000>::Value,
1.464 + KGPTIMER11_Base = TVirtual<0x48088000>::Value,
1.465 + KGPTIMER12_Base = TVirtual<0x48304000>::Value,
1.466 + } ;
1.467 +
1.468 + enum TTimerNumber
1.469 + {
1.470 + EGpTimer1,
1.471 + EGpTimer2,
1.472 + EGpTimer3,
1.473 + EGpTimer4,
1.474 + EGpTimer5,
1.475 + EGpTimer6,
1.476 + EGpTimer7,
1.477 + EGpTimer8,
1.478 + EGpTimer9,
1.479 + EGpTimer10,
1.480 + EGpTimer11,
1.481 + EGpTimer12
1.482 + };
1.483 +
1.484 + typedef void (*TTimerIsr)(TAny*) ;
1.485 +
1.486 + template<const TTimerNumber tImEr>
1.487 + struct TTimerTraits
1.488 + {
1.489 + } ;
1.490 +
1.491 + template<>
1.492 + struct TTimerTraits<EGpTimer1>
1.493 + {
1.494 + enum TraitValues
1.495 + {
1.496 + KBaseAddress = KGPTIMER1_Base,
1.497 + KIrq = EOmap3530_IRQ37_GPT1_IRQ,
1.498 + KClockSelMask = TSingleBitField<7>::KMask,
1.499 + KClockSelValue = TSingleBitField<7>::KOn,
1.500 + } ;
1.501 + } ;
1.502 +
1.503 + template<>
1.504 + struct TTimerTraits<EGpTimer2>
1.505 + {
1.506 + enum TraitValues
1.507 + {
1.508 + KBaseAddress = KGPTIMER2_Base,
1.509 + KIrq = EOmap3530_IRQ38_GPT2_IRQ,
1.510 + } ;
1.511 + } ;
1.512 +
1.513 + template<>
1.514 + struct TTimerTraits<EGpTimer3>
1.515 + {
1.516 + enum TraitValues
1.517 + {
1.518 + KBaseAddress = KGPTIMER3_Base,
1.519 + KIrq = EOmap3530_IRQ39_GPT3_IRQ,
1.520 + } ;
1.521 + } ;
1.522 +
1.523 + template<>
1.524 + struct TTimerTraits<EGpTimer4>
1.525 + {
1.526 + enum TraitValues
1.527 + {
1.528 + KBaseAddress = KGPTIMER4_Base,
1.529 + KIrq = EOmap3530_IRQ40_GPT4_IRQ,
1.530 + } ;
1.531 + } ;
1.532 +
1.533 + template<>
1.534 + struct TTimerTraits<EGpTimer5>
1.535 + {
1.536 + enum TraitValues
1.537 + {
1.538 + KBaseAddress = KGPTIMER5_Base,
1.539 + KIrq = EOmap3530_IRQ41_GPT5_IRQ,
1.540 + } ;
1.541 + } ;
1.542 +
1.543 + template<>
1.544 + struct TTimerTraits<EGpTimer6>
1.545 + {
1.546 + enum TraitValues
1.547 + {
1.548 + KBaseAddress = KGPTIMER6_Base,
1.549 + KIrq = EOmap3530_IRQ42_GPT6_IRQ,
1.550 + } ;
1.551 + } ;
1.552 +
1.553 + template<>
1.554 + struct TTimerTraits<EGpTimer7>
1.555 + {
1.556 + enum TraitValues
1.557 + {
1.558 + KBaseAddress = KGPTIMER7_Base,
1.559 + KIrq = EOmap3530_IRQ43_GPT7_IRQ,
1.560 + } ;
1.561 + } ;
1.562 +
1.563 + template<>
1.564 + struct TTimerTraits<EGpTimer8>
1.565 + {
1.566 + enum TraitValues
1.567 + {
1.568 + KBaseAddress = KGPTIMER8_Base,
1.569 + KIrq = EOmap3530_IRQ44_GPT8_IRQ,
1.570 + } ;
1.571 + } ;
1.572 +
1.573 + template<>
1.574 + struct TTimerTraits<EGpTimer9>
1.575 + {
1.576 + enum TraitValues
1.577 + {
1.578 + KBaseAddress = KGPTIMER9_Base,
1.579 + KIrq = EOmap3530_IRQ45_GPT9_IRQ,
1.580 + } ;
1.581 + } ;
1.582 +
1.583 + template<>
1.584 + struct TTimerTraits<EGpTimer10>
1.585 + {
1.586 + enum TraitValues
1.587 + {
1.588 + KBaseAddress = KGPTIMER10_Base,
1.589 + KIrq = EOmap3530_IRQ46_GPT10_IRQ,
1.590 + } ;
1.591 + } ;
1.592 +
1.593 + template<>
1.594 + struct TTimerTraits<EGpTimer11>
1.595 + {
1.596 + enum TraitValues
1.597 + {
1.598 + KBaseAddress = KGPTIMER11_Base,
1.599 + KIrq = EOmap3530_IRQ47_GPT11_IRQ,
1.600 + } ;
1.601 + } ;
1.602 +
1.603 + template<>
1.604 + struct TTimerTraits<EGpTimer12>
1.605 + {
1.606 + enum TraitValues
1.607 + {
1.608 + KBaseAddress = KGPTIMER12_Base,
1.609 + KIrq = EOmap3530_IRQ95_GPT12_IRQ,
1.610 + KClockSelReg = 0,
1.611 + KClockSelMask = 0,
1.612 + KClockSel32K = 0,
1.613 + KClockSelSys = 0,
1.614 + KClockSelValue = KClockSel32K
1.615 + } ;
1.616 + } ;
1.617 +
1.618 + /**
1.619 + An interface template for OMAP3530 General Purpose timer functionality.
1.620 + */
1.621 + template <const TTimerNumber tImEr>
1.622 + class TGPT
1.623 + {
1.624 + protected :
1.625 + enum TRegisterOffsets
1.626 + {
1.627 + KTIOCP_CFG_Offset = 0x010,
1.628 + KTISTAT_Offset = 0x014,
1.629 + KTISR_Offset = 0x018,
1.630 + KTIER_Offset = 0x01C,
1.631 + KTWER_Offset = 0x020,
1.632 + KTCLR_Offset = 0x024,
1.633 + KTCRR_Offset = 0x028,
1.634 + KTLDR_Offset = 0x02C,
1.635 + KTTGR_Offset = 0x030,
1.636 + KTWPS_Offset = 0x034,
1.637 + KTMAR_Offset = 0x038,
1.638 + KTCAR1_Offset = 0x03C,
1.639 + KTSICR_Offset = 0x040,
1.640 + KTCAR2_Offset = 0x044
1.641 + } ;
1.642 + enum TConstants
1.643 + {
1.644 + KHz = 1000,
1.645 + KClockInputFrequency = 32768,
1.646 + } ;
1.647 +
1.648 + public :
1.649 + static inline TOmap3530_IRQ Irq()
1.650 + {
1.651 + return TOmap3530_IRQ(TTimerTraits<tImEr>::KIrq) ;
1.652 + }
1.653 + static inline TBool CanWriteTCLR()
1.654 + {
1.655 + return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TCLR::KOn)) ;
1.656 + }
1.657 + static inline TBool CanWriteTCRR()
1.658 + {
1.659 + return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TCRR::KOn)) ;
1.660 + }
1.661 + static inline TBool CanWriteTLDR()
1.662 + {
1.663 + return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TLDR::KOn)) ;
1.664 + }
1.665 + static inline TBool CanWriteTTGR()
1.666 + {
1.667 + return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TTGR::KOn)) ;
1.668 + }
1.669 + static inline TBool CanWriteTMAR()
1.670 + {
1.671 + return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TMAR::KOn)) ;
1.672 + }
1.673 + static inline void Reset()
1.674 + {
1.675 + iTIOCP_CFG.Write(TIOCP_CFG::T_SOFTRESET::KOn) ;
1.676 + }
1.677 + static inline TBool ResetComplete()
1.678 + {
1.679 + return (TISTAT::T_RESETDONE::KOn & iTISTAT.Read()) ;
1.680 + }
1.681 + static inline TBool WriteOutstanding()
1.682 + {
1.683 + return (iTWPS.Read()) ;
1.684 + }
1.685 +
1.686 + public :
1.687 + static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTIOCP_CFG_Offset)> iTIOCP_CFG ;
1.688 + static TReg32_R<(TTimerTraits<tImEr>::KBaseAddress + KTISTAT_Offset)> iTISTAT ;
1.689 + static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTISR_Offset)> iTISR ;
1.690 + static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTIER_Offset)> iTIER ;
1.691 + static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTWER_Offset)> iTWER ;
1.692 + static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTCLR_Offset)> iTCLR ;
1.693 + static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTCRR_Offset)> iTCRR ;
1.694 + static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTLDR_Offset)> iTLDR ;
1.695 + static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTTGR_Offset)> iTTGR ;
1.696 + static TReg32_R<(TTimerTraits<tImEr>::KBaseAddress + KTWPS_Offset)> iTWPS ;
1.697 + static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTMAR_Offset)> iTMAR ;
1.698 + static TReg32_R<(TTimerTraits<tImEr>::KBaseAddress + KTCAR1_Offset)> iTCAR1 ;
1.699 + static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTSICR_Offset)> iTSICR ;
1.700 + static TReg32_R<(TTimerTraits<tImEr>::KBaseAddress + KTCAR2_Offset)> iTCAR2 ;
1.701 + } ; // class TGPTi
1.702 +
1.703 + /**
1.704 +
1.705 + An interface template for OMAP3530 Microsecond aligned timer functionality.
1.706 + Encapsulates the extra registers provided for timers 1, 2 and 10.
1.707 + */
1.708 + template <const TTimerNumber tImEr>
1.709 + class TMsSyncTimer : public TGPT<tImEr>
1.710 + {
1.711 + using TGPT<tImEr>::iTWPS ;
1.712 + using TGPT<tImEr>::iTLDR ;
1.713 +
1.714 + protected :
1.715 + enum TRegisterOffsets
1.716 + {
1.717 + KTPIR_Offset = 0x048,
1.718 + KTNIR_Offset = 0x04C,
1.719 + KTCVR_Offset = 0x050,
1.720 + KTOCR_Offset = 0x054,
1.721 + KTOWR_Offset = 0x058
1.722 + } ;
1.723 +
1.724 + public :
1.725 + enum TRegisterValues
1.726 + {
1.727 + KInitialLoad = 0xFFFFFFE0,
1.728 + KInitialPIR = 0x38A40,
1.729 + KInitialNIR = 0xFFF44800
1.730 + } ;
1.731 +
1.732 + static inline TBool CanWriteTPIR()
1.733 + {
1.734 + return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TPIR::KOn)) ;
1.735 + }
1.736 + static inline TBool CanWriteTNIR()
1.737 + {
1.738 + return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TNIR::KOn)) ;
1.739 + }
1.740 + static inline TBool CanWriteTCVR()
1.741 + {
1.742 + return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TCVR::KOn)) ;
1.743 + }
1.744 + static inline TBool CanWriteTOCR()
1.745 + {
1.746 + return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TOCR::KOn)) ;
1.747 + }
1.748 + static inline TBool CanWriteTOWR()
1.749 + {
1.750 + return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TOWR::KOn)) ;
1.751 + }
1.752 +
1.753 + static inline void ConfigureFor1Ms()
1.754 + {
1.755 + iTLDR.Write( KInitialLoad );
1.756 + iTPIR.Write( KInitialPIR );
1.757 + iTNIR.Write( KInitialNIR );
1.758 + }
1.759 +
1.760 + public :
1.761 + static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTPIR_Offset)> iTPIR ;
1.762 + static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTNIR_Offset)> iTNIR ;
1.763 + static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTCVR_Offset)> iTCVR ;
1.764 + static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTOCR_Offset)> iTOCR ;
1.765 + static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTOWR_Offset)> iTOWR ;
1.766 + } ; // class TMsSyncTimer
1.767 +
1.768 +
1.769 + } // namespage GPTimer
1.770 +
1.771 + typedef GPTimer::TMsSyncTimer<GPTimer::EGpTimer1> TGpTimer1 ;
1.772 + typedef GPTimer::TMsSyncTimer<GPTimer::EGpTimer2> TGpTimer2 ;
1.773 + typedef GPTimer::TGPT<GPTimer::EGpTimer3> TGpTimer3 ;
1.774 + typedef GPTimer::TGPT<GPTimer::EGpTimer4> TGpTimer4 ;
1.775 + typedef GPTimer::TGPT<GPTimer::EGpTimer5> TGpTimer5 ;
1.776 + typedef GPTimer::TGPT<GPTimer::EGpTimer6> TGpTimer6 ;
1.777 + typedef GPTimer::TGPT<GPTimer::EGpTimer7> TGpTimer7 ;
1.778 + typedef GPTimer::TGPT<GPTimer::EGpTimer8> TGpTimer8 ;
1.779 + typedef GPTimer::TGPT<GPTimer::EGpTimer9> TGpTimer9 ;
1.780 + typedef GPTimer::TMsSyncTimer<GPTimer::EGpTimer10> TGpTimer10 ;
1.781 + typedef GPTimer::TGPT<GPTimer::EGpTimer11> TGpTimer11 ;
1.782 + typedef GPTimer::TGPT<GPTimer::EGpTimer12> TGpTimer12 ;
1.783 +
1.784 +
1.785 + /**
1.786 + An interface template for OMAP3530 32-KHz aligned timer functionality.
1.787 + */
1.788 + class T32KhzSyncTimer
1.789 + {
1.790 + protected :
1.791 + enum TRegisterAddress
1.792 + {
1.793 + KREG_32KSYNCNT_SYSCONFIG = TVirtual<0x48320004>::Value,
1.794 + KREG_32KSYNCNT_CR = TVirtual<0x48320010>::Value
1.795 + } ;
1.796 +
1.797 + public :
1.798 + static TReg32_RW<KREG_32KSYNCNT_SYSCONFIG> iSysConfig ;
1.799 + static TReg32_R<KREG_32KSYNCNT_CR> iCR ;
1.800 +
1.801 + private :
1.802 + } ; // class TMsSyncTimer
1.803 +
1.804 + } // namespace Omap3530
1.805 +
1.806 + } // namespace TexasInstruments
1.807 +
1.808 +
1.809 +// **** TEST CODE ****
1.810 +//# define HEADER_OMAP3530_TIMER_H_DO_COMPILE_TIME_CHECK_TESTS 1
1.811 +# ifdef HEADER_OMAP3530_TIMER_H_DO_COMPILE_TIME_CHECK_TESTS
1.812 + inline void CompileTimeChecks(void)
1.813 + {
1.814 + __ASSERT_COMPILE((TI::Omap3530::GPTimer::TIOCP_CFG::T_IDLEMODE::KSmartIdle == (2 << 3))) ;
1.815 + __ASSERT_COMPILE((TI::Omap3530::GPTimer::TIOCP_CFG::T_CLOCKACTIVITY::KMaintainIfClock == (1 << 8))) ;
1.816 + __ASSERT_COMPILE((TI::Omap3530::GPTimer::KGPTIMER1_Base == (0xC6318000))) ;
1.817 + __ASSERT_COMPILE((0)) ; // Prove that testing is happening
1.818 + }
1.819 +# endif
1.820 +#endif /* ndef HEADER_OMAP3530_TIMER_H_INCLUDED */