1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/epoc32/include/assp/template_assp/template_assp.h Tue Mar 16 16:12:26 2010 +0000
1.3 @@ -0,0 +1,230 @@
1.4 +// Copyright (c) 1997-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Symbian Foundation License v1.0" to Symbian Foundation members and "Symbian Foundation End User License Agreement v1.0" to non-members
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.symbianfoundation.org/legal/licencesv10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// template\template_assp\template_assp.h
1.18 +// Definitions for Template ASSP
1.19 +//
1.20 +//
1.21 +
1.22 +
1.23 +
1.24 +#ifndef __A32TEMPLATEV1_H__
1.25 +#define __A32TEMPLATEV1_H__
1.26 +#include <e32const.h>
1.27 +#include <platform.h>
1.28 +#include <e32hal.h>
1.29 +#include <assp.h>
1.30 +#include <kern_priv.h>
1.31 +
1.32 +//----------------------------------------------------------------------------
1.33 +// Constant conventions:
1.34 +//----------------------------------------------------------------------------
1.35 +
1.36 +// KH Hardware definition
1.37 +// KHw 4-byte word definition prefix
1.38 +// KHb Byte definition prefix
1.39 +// KHt Bit definition prefix
1.40 +// KHm Mask definition prefix
1.41 +// KHs Shift definition prefix
1.42 +// KHo Offset definition prefix
1.43 +// KHwRo Read-only register
1.44 +// KHwWo Write-only register
1.45 +// KHwRw Read/write register
1.46 +// KHwBase Base address within memory map
1.47 +// _i Input suffix
1.48 +// _o Output suffix
1.49 +// _b Input/output suffix
1.50 +
1.51 +//----------------------------------------------------------------------------
1.52 +// Memory map: physical addresses
1.53 +//----------------------------------------------------------------------------
1.54 +// NB: these are just examples
1.55 +
1.56 +const TUint KHwBaseCs0 = 0x00000000;
1.57 +const TUint KHwBaseCs1 = KHwBaseCs0 + 128*KMega;
1.58 +const TUint KHwBaseCs2 = KHwBaseCs1 + 128*KMega;
1.59 +const TUint KHwBaseCs3 = KHwBaseCs2 + 128*KMega;
1.60 +
1.61 +const TUint KHwBaseMemBank0 = 0x20000000;
1.62 +const TUint KHwBaseMemBank1 = KHwBaseMemBank0 + 256*KMega;
1.63 +
1.64 +const TUint KHwBaseRegisters = 0x80000000;
1.65 +const TUint KHwBasePeripherals = KHwBaseRegisters; // 8000.0000
1.66 +const TUint KHwBasePeripheralsA = KHwBasePeripherals + 256*KMega; // 9000.0000
1.67 +const TUint KHwBasePeripheralsB = KHwBasePeripheralsA + 256*KMega; // A000.0000
1.68 +const TUint KHwBasePeripheralsC = KHwBasePeripheralsB + 256*KMega; // B000.0000
1.69 +
1.70 +// etc...
1.71 +
1.72 +//----------------------------------------------------------------------------
1.73 +// Memory map: linear addresses
1.74 +//----------------------------------------------------------------------------
1.75 +
1.76 +#if defined (__MEMMODEL_MULTIPLE__)
1.77 +const TUint KHwLinBaseRegisters = 0xc6000000; // as mapped by bootstrap
1.78 +const TUint KHwLinSeparation = 0x1000;
1.79 +#elif defined(__MEMMODEL_DIRECT__)
1.80 +const TUint KHwLinBaseRegisters = 0x10000000; // physical address (example only)
1.81 +const TUint KHwLinSeparation = 0x01000000; // physical offsets (example only)
1.82 +#else
1.83 +const TUint KHwLinBaseRegisters = 0x63000000; // as mapped by bootstrap
1.84 +const TUint KHwLinSeparation = 0x1000;
1.85 +#endif
1.86 +
1.87 +// EXAMPLE ONLY:
1.88 +const TUint KHwLinBasePeriphGroupA = KHwLinBaseRegisters;
1.89 +const TUint KHwLinBasePeripheral1 = KHwLinBasePeriphGroupA + 0x00*KHwLinSeparation;
1.90 +const TUint KHwLinBasePeripheral2 = KHwLinBasePeriphGroupA + 0x01*KHwLinSeparation;
1.91 +const TUint KHwLinBasePeripheral3 = KHwLinBasePeriphGroupA + 0x02*KHwLinSeparation;
1.92 +const TUint KHwLinBasePeripheral4 = KHwLinBasePeriphGroupA + 0x03*KHwLinSeparation;
1.93 +
1.94 +const TUint KHwLinBasePeriphGroupB = KHwLinBaseRegisters + 0x20*KHwLinSeparation;
1.95 +
1.96 +const TUint KHwBaseSerial1 = KHwLinBasePeriphGroupB + 0x00*KHwLinSeparation;
1.97 +const TUint KHwBaseSerial2 = KHwLinBasePeriphGroupB + 0x01*KHwLinSeparation;
1.98 +const TUint KHwBaseSerial3 = KHwLinBasePeriphGroupB + 0x02*KHwLinSeparation;
1.99 +
1.100 +const TUint KHwLinBasePeriphGroupC = KHwLinBaseRegisters + 0x30*KHwLinSeparation;
1.101 +
1.102 +const TUint KHwBaseInterrupts = KHwLinBasePeriphGroupC + 0x00*KHwLinSeparation;
1.103 +const TUint KHwInterruptsMaskRo = KHwBaseInterrupts + 0x00;
1.104 +const TUint KHwInterruptsMaskSet = KHwBaseInterrupts + 0x04;
1.105 +const TUint KHwInterruptsMaskClear = KHwBaseInterrupts + 0x08;
1.106 +const TUint KHoInterruptsIrqPending = 0x0C;
1.107 +const TUint KHwInterruptsIrqPending = KHwBaseInterrupts + KHoInterruptsIrqPending;
1.108 +const TUint KHoInterruptsFiqPending = 0x10;
1.109 +const TUint KHwInterruptsFiqending = KHwBaseInterrupts + KHoInterruptsFiqPending;
1.110 +
1.111 +
1.112 +// Other device specifc constants, register offsets, bit masks, general-purpose I/O allocations,
1.113 +// interrupt sources, Memory settings and geometries, etc
1.114 +
1.115 +
1.116 +class TTemplate
1.117 + {
1.118 + /**
1.119 + * Accessor functions to hardware resources managed by ASSP (ASIC). Auxiliary and information functions which
1.120 + * are commonly used by Device Drivers or ASSP/Variant code.
1.121 + * Some examples below. These examples assume that the hardware blocks they access (e.g. Interrupt controller
1.122 + * RTC, Clock Control Module, UART, etc) are part of the ASSP.
1.123 + */
1.124 +public:
1.125 + /**
1.126 + * initialisation
1.127 + */
1.128 + static void Init3();
1.129 + /**
1.130 + * Active waiting loop (not to be used after System Tick timer has been set up - Init3()
1.131 + * @param aDuration A wait time in milliseconds
1.132 + */
1.133 + IMPORT_C static void BootWaitMilliSeconds(TInt aDuration);
1.134 + /**
1.135 + * Read and return the Startup reason of the Hardware
1.136 + * @return A TMachineStartupType enumerated value
1.137 + */
1.138 + IMPORT_C static TMachineStartupType StartupReason();
1.139 + /**
1.140 + * Read and return the the CPU ID
1.141 + * @return An integer containing the CPU ID string read off the hardware
1.142 + */
1.143 + IMPORT_C static TInt CpuVersionId();
1.144 + /**
1.145 + * Read Linear base address of debug UART (as selected in obey file or with eshell debugport command).
1.146 + * @return An integer containing the Linear address of debug Serial Port
1.147 + */
1.148 + IMPORT_C static TUint DebugPortAddr();
1.149 + /**
1.150 + * Read CPU clock period in picoseconds
1.151 + * @return An integer containing the CPU clock period in picoseconds
1.152 + */
1.153 + IMPORT_C static TUint ProcessorPeriodInPs();
1.154 + /**
1.155 + * Set the Hardware Interrupt masks
1.156 + * @param aValue A new interrupt mask value
1.157 + */
1.158 + IMPORT_C static void SetIntMask(TUint aValue);
1.159 + /**
1.160 + * Modify the Hardware Interrupt masks
1.161 + * @param aClearMask A mask with interrupt source bits to clear (disable)
1.162 + * @param aSetMask A mask with interrupt source bits to set (enable)
1.163 + */
1.164 + IMPORT_C static void ModifyIntMask(TUint aClearMask,TUint aSetMask);
1.165 + /**
1.166 + * Read the state of pending interrupts
1.167 + * @return A mask containing bits set for all pending interrupts
1.168 + */
1.169 + IMPORT_C static TUint IntsPending();
1.170 + /**
1.171 + * Read the current time of the RTC
1.172 + * @return A value that is the real time as given by a RTC
1.173 + */
1.174 + IMPORT_C static TUint RtcData();
1.175 + /**
1.176 + * Set the RTC time
1.177 + * @param aValue The real time to set the RTC
1.178 + */
1.179 + IMPORT_C static void SetRtcData(TUint aValue);
1.180 + /**
1.181 + * Obtain the physical start address of Video Buffer
1.182 + * @return the physical start address of Video Buffer
1.183 + */
1.184 + IMPORT_C static TPhysAddr VideoRamPhys();
1.185 +private:
1.186 + /**
1.187 + * Auxiliary accessor functions for Hardware registers (used by functions above)
1.188 + */
1.189 + static inline TUint Register32(TUint aAddr);
1.190 + static inline void SetRegister32(TUint aValue, TUint aAddr);
1.191 + static void ModifyRegister32(TUint aClearMask, TUint aSetMask, TUint aAddr);
1.192 + /**
1.193 + * Assp-specific implementation for Kern::NanoWait function
1.194 + */
1.195 + static void NanoWait(TUint32 aInterval);
1.196 + };
1.197 +
1.198 +// TO DO: (optional)
1.199 +//
1.200 +// Enumerate here all ASSP interrupt souces. It could be a good idea to enumerate them in a way that facilitates
1.201 +// operating on the corresponding interrupt controller registers (e.g using their value as a shift count)
1.202 +//
1.203 +// EXAMPLE ONLY
1.204 +enum TTemplateAsspInterruptId
1.205 + {
1.206 + // ASSP or first-level Interrupt IDs
1.207 + EAsspIntIdA=0,
1.208 + EAsspIntIdB=1,
1.209 + EAsspIntIdC=2,
1.210 + EAsspIntIdD=3,
1.211 + EAsspIntIdE=4,
1.212 + // ...
1.213 + EAsspIntIdUsb=11,
1.214 + EAsspIntIdDma=12,
1.215 + // ...
1.216 + EAsspIntIdZ=25
1.217 + };
1.218 +
1.219 +//
1.220 +// TO DO: (optional)
1.221 +//
1.222 +// Define here some commonly used ASSP interrupts
1.223 +//
1.224 +// EXAMPLE ONLY
1.225 +const TInt KIntIdExpansion=EAsspIntIdA; // this is the ASSP interrupt which connects to second-level (Variant)
1.226 + // Interrupt controller: all 2nd level interrupts come through this interrupt
1.227 +const TInt KIntIdOstMatchMsTimer=EAsspIntIdB;
1.228 +const TInt KIntIdDigitiser=EAsspIntIdC;
1.229 +const TInt KIntIdSound=EAsspIntIdD;
1.230 +const TInt KIntIdTimer1=EAsspIntIdE;
1.231 +
1.232 +
1.233 +#endif