sl@0: // Copyright (c) 1994-2009 Nokia Corporation and/or its subsidiary(-ies).
sl@0: // All rights reserved.
sl@0: // This component and the accompanying materials are made available
sl@0: // under the terms of the License "Eclipse Public License v1.0"
sl@0: // which accompanies this distribution, and is available
sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
sl@0: //
sl@0: // Initial Contributors:
sl@0: // Nokia Corporation - initial contribution.
sl@0: //
sl@0: // Contributors:
sl@0: //
sl@0: // Description:
sl@0: // e32\memmodel\epoc\moving\arm\xkernel.cia
sl@0: // 
sl@0: //
sl@0: 
sl@0: #include <e32cia.h>
sl@0: #include <arm_mem.h>
sl@0: 
sl@0: __NAKED__ void DArmPlatChunk::MoveHomePdes(TLinAddr /*aOldAddr*/, TLinAddr /*aNewAddr*/)
sl@0: 	{
sl@0: 	asm("mov r2, r2, lsr #20 ");			// r2=pde index for new addr
sl@0: 	asm("subs r2, r2, r1, lsr #20 ");		// subtract pde index for old addr
sl@0: 	__JUMP(eq,lr);							// if zero, nothing to do
sl@0: 	asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iNumPdes));
sl@0: 	asm("cmp r1, #0 ");
sl@0: 	__JUMP(eq,lr);							// if chunk empty, nothing to do
sl@0: 	asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomePdes));
sl@0: 	asm("add r1, r1, r2, asl #2 ");			// move home pde address
sl@0: 	asm("str r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomePdes));
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: __NAKED__ void DArmPlatChunk::MoveCurrentPdes(TLinAddr /*aOldAddr*/, TLinAddr /*aNewAddr*/)
sl@0: 	{
sl@0: 	asm("mov r2, r2, lsr #20 ");			// r2=pde index for new addr
sl@0: 	asm("subs r2, r2, r1, lsr #20 ");		// subtract pde index for old addr
sl@0: 	__JUMP(eq,lr);							// if zero, nothing to do
sl@0: 	asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iNumPdes));
sl@0: 	asm("cmp r1, #0 ");
sl@0: 	__JUMP(eq,lr);							// if chunk empty, nothing to do
sl@0: 	asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdes));
sl@0: 	asm("add r1, r1, r2, asl #2 ");			// move current pde address
sl@0: 	asm("str r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdes));
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: __NAKED__ void DArmPlatChunk::AddPde(TInt /*aOffset*/)
sl@0: 	{
sl@0: 	asm("mov r1, r1, lsr #20 ");			// r1=pde number
sl@0: 	asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iMaxSize));
sl@0: 	asm("cmp r2, #0x02000000 ");
sl@0: 	asm("ldr r3, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdeBitMap));
sl@0: 	asm("bhi add_pde_large ");
sl@0: 	asm("mov ip, #1 ");
sl@0: 	asm("orr r3, r3, ip, lsl r1 ");			// set bit in bitmap
sl@0: 	asm("str r3, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdeBitMap));
sl@0: 	asm("b scan_small_bitmap ");
sl@0: 
sl@0: 	asm("add_pde_large: ");
sl@0: 	asm("stmfd sp!, {r4,lr} ");
sl@0: 	asm("mov lr, r1, lsr #5 ");				// lr=word number in bitmap
sl@0: 	asm("and r1, r1, #31 ");				// r1=bit number in word
sl@0: 	asm("ldr r4, [r3, lr, lsl #2] ");
sl@0: 	asm("mov ip, #1 ");
sl@0: 	asm("orr r4, r4, ip, lsl r1 ");
sl@0: 	asm("str r4, [r3, lr, lsl #2] ");		// set bit in bitmap
sl@0: 	asm("b scan_large_bitmap ");
sl@0: 	}
sl@0: 
sl@0: __NAKED__ void DArmPlatChunk::RemovePde(TInt /*anOffset*/)
sl@0: 	{
sl@0: 	asm("mov r1, r1, lsr #20 ");			// r1=pde number
sl@0: 	asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iMaxSize));
sl@0: 	asm("cmp r2, #0x02000000 ");
sl@0: 	asm("ldr r3, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdeBitMap));
sl@0: 	asm("bhi rem_pde_large ");
sl@0: 	asm("mov ip, #1 ");
sl@0: 	asm("bics r3, r3, ip, lsl r1 ");		// clear bit in bitmap
sl@0: 	asm("str r3, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdeBitMap));
sl@0: 	asm("beq empty_chunk ");				// if chunk empty, skip rest
sl@0: 
sl@0: 	asm("scan_small_bitmap: ");				// r3 contains nonzero bitmap
sl@0: #ifdef __CPU_ARM_HAS_CLZ
sl@0: 	asm("sub r2, r3, #1 ");					// ip will hold index of first pde
sl@0: 	asm("eor r2, r2, r3 ");
sl@0: 	CLZ(12,2);
sl@0: 	asm("rsb r12, r12, #31 ");
sl@0: 	asm("mov r3, r3, lsr r12 ");			// shift bitmap so bit 0 set
sl@0: 	CLZ(1, 3);
sl@0: 	asm("rsb r1, r1, #32 ");				// r1 will be 1+most significant 1 in r3	
sl@0: #else
sl@0: 	asm("mov ip, #0 ");						// ip will hold index of first pde
sl@0: 	asm("movs r2, r3, lsl #16 ");			// test if bottom 16 bits zero
sl@0: 	asm("moveq r3, r3, lsr #16 ");			// if bottom 16 zero, shift right by 16
sl@0: 	asm("addeq ip, ip, #16 ");				// and add 16 to lsb index
sl@0: 	asm("tst r3, #0xff ");
sl@0: 	asm("moveq r3, r3, lsr #8 ");
sl@0: 	asm("addeq ip, ip, #8 ");
sl@0: 	asm("tst r3, #0x0f ");
sl@0: 	asm("moveq r3, r3, lsr #4 ");
sl@0: 	asm("addeq ip, ip, #4 ");
sl@0: 	asm("tst r3, #0x03 ");
sl@0: 	asm("moveq r3, r3, lsr #2 ");
sl@0: 	asm("addeq ip, ip, #2 ");
sl@0: 	asm("tst r3, #0x01 ");
sl@0: 	asm("moveq r3, r3, lsr #1 ");
sl@0: 	asm("addeq ip, ip, #1 ");				// ip=number of right shifts applied, r3 bit 0 set
sl@0: 	asm("mov r1, #32 ");					// r1 will be 1+most significant 1 in r3
sl@0: 	asm("cmp r3, #0x00010000 ");
sl@0: 	asm("movcc r3, r3, lsl #16 ");
sl@0: 	asm("subcc r1, r1, #16 ");
sl@0: 	asm("cmp r3, #0x01000000 ");
sl@0: 	asm("movcc r3, r3, lsl #8 ");
sl@0: 	asm("subcc r1, r1, #8 ");
sl@0: 	asm("cmp r3, #0x10000000 ");
sl@0: 	asm("movcc r3, r3, lsl #4 ");
sl@0: 	asm("subcc r1, r1, #4 ");
sl@0: 	asm("cmp r3, #0x40000000 ");
sl@0: 	asm("movcc r3, r3, lsl #2 ");
sl@0: 	asm("subcc r1, r1, #2 ");
sl@0: 	asm("cmp r3, #0x80000000 ");
sl@0: 	asm("movcc r3, r3, lsl #1 ");
sl@0: 	asm("subcc r1, r1, #1 ");
sl@0: #endif
sl@0: 
sl@0: 	asm("scan_bitmap_end: ");
sl@0: 	asm("str r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iNumPdes));	// r1 gives number of PDEs in range
sl@0: 	asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iBase));
sl@0: 	asm("add r2, ip, r2, lsr #20 ");		// r2=pde index of first current pde
sl@0: 	asm("mov r2, r2, lsl #2 ");
sl@0: 	asm("add r2, r2, #%a0" : : "i" ((TInt)KPageDirectoryBase));			// r2->first current pde
sl@0: 	asm("str r2, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdes));
sl@0: 	asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomeBase));
sl@0: 	asm("add r2, ip, r2, lsr #20 ");		// r2=pde index of first home pde
sl@0: 	asm("mov r2, r2, lsl #2 ");
sl@0: 	asm("add r2, r2, #%a0" : : "i" ((TInt)KPageDirectoryBase));			// r2->first home pde
sl@0: 	asm("str r2, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomePdes));
sl@0: 	__JUMP(,lr);
sl@0: 
sl@0: 	asm("empty_chunk: ");
sl@0: 	asm("mov r1, #0 ");
sl@0: 	asm("str r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iNumPdes));
sl@0: 	asm("str r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdes));
sl@0: 	asm("str r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomePdes));
sl@0: 	__JUMP(,lr);
sl@0: 
sl@0: 	asm("rem_pde_large: ");
sl@0: 	asm("stmfd sp!, {r4,lr} ");
sl@0: 	asm("mov lr, r1, lsr #5 ");				// lr=word number in bitmap
sl@0: 	asm("and r1, r1, #31 ");				// r1=bit number in word
sl@0: 	asm("ldr r4, [r3, lr, lsl #2] ");
sl@0: 	asm("mov ip, #1 ");
sl@0: 	asm("bic r4, r4, ip, lsl r1 ");
sl@0: 	asm("str r4, [r3, lr, lsl #2] ");		// set bit in bitmap
sl@0: 
sl@0: 	asm("scan_large_bitmap: ");
sl@0: 	// r0=this, r2=max size, r3->pde bit map
sl@0: 	asm("add r2, r2, #0x1f00000 ");
sl@0: 	asm("mov r2, r2, lsr #25 ");			// r2=number of words in bitmap
sl@0: 	asm("add r2, r3, r2, lsl #2 ");			// r2=bitmap end address
sl@0: 	asm("mov r4, r3 ");						// save bitmap start address
sl@0: 
sl@0: 	asm("scan_large_1: ");
sl@0: 	asm("ldr ip, [r3], #4 ");
sl@0: 	asm("cmp ip, #0 ");
sl@0: 	asm("bne scan_large_2 ");				// found non-empty word
sl@0: 	asm("cmp r3, r2 ");
sl@0: 	asm("bne scan_large_1 ");				// if not reached end, do next word
sl@0: 	asm("ldmfd sp!, {r4,lr} ");
sl@0: 	asm("b empty_chunk ");					// branch if no bits set
sl@0: 
sl@0: 	asm("scan_large_2: ");
sl@0: 	asm("sub r1, r3, r4 ");
sl@0: 	asm("sub r1, r1, #4 ");
sl@0: 	asm("mov r1, r1, lsl #3 ");				// r1=bit number of lsb of this word
sl@0: #ifdef __CPU_ARM_HAS_CLZ
sl@0: 	asm("sub lr, ip, #1 ");					// ip will hold index of first pde
sl@0: 	asm("eor ip, lr, ip ");
sl@0: 	CLZ(12, 12);
sl@0: 	asm("rsb ip, ip, #31 ");
sl@0: 	asm("add r1, r1, ip ");					// r1 now = first occupied pde offset
sl@0: #else
sl@0: 	asm("movs lr, ip, lsl #16 ");
sl@0: 	asm("moveq ip, ip, lsr #16 ");
sl@0: 	asm("addeq r1, r1, #16 ");
sl@0: 	asm("tst ip, #0xff ");
sl@0: 	asm("moveq ip, ip, lsr #8 ");
sl@0: 	asm("addeq r1, r1, #8 ");
sl@0: 	asm("tst ip, #0x0f ");
sl@0: 	asm("moveq ip, ip, lsr #4 ");
sl@0: 	asm("addeq r1, r1, #4 ");
sl@0: 	asm("tst ip, #0x03 ");
sl@0: 	asm("moveq ip, ip, lsr #2 ");
sl@0: 	asm("addeq r1, r1, #2 ");
sl@0: 	asm("tst ip, #0x01 ");
sl@0: 	asm("moveq ip, ip, lsr #1 ");
sl@0: 	asm("addeq r1, r1, #1 ");				// r1 now = first occupied pde offset
sl@0: #endif
sl@0: 	
sl@0: 	asm("scan_large_3: ");
sl@0: 	asm("ldr ip, [r2, #-4]! ");				// fetch words from end of bitmap
sl@0: 	asm("cmp ip, #0 ");
sl@0: 	asm("beq scan_large_3 ");				// we know there is at least one non-zero word
sl@0: 	asm("sub r2, r2, r4 ");
sl@0: 	asm("mov r2, r2, lsl #3 ");				// r2=bit number of lsb of this word
sl@0: #ifdef __CPU_ARM_HAS_CLZ
sl@0: 	CLZ(12, 12);
sl@0: 	asm("rsb ip, ip, #31 ");
sl@0: 	asm("add r2, r2, ip ");					// r2 now = last occupied pde offset
sl@0: #else
sl@0: 	asm("movs lr, ip, lsr #16 ");
sl@0: 	asm("movne ip, lr ");
sl@0: 	asm("addne r2, r2, #16 ");
sl@0: 	asm("movs lr, ip, lsr #8 ");
sl@0: 	asm("movne ip, lr ");
sl@0: 	asm("addne r2, r2, #8 ");
sl@0: 	asm("movs lr, ip, lsr #4 ");
sl@0: 	asm("movne ip, lr ");
sl@0: 	asm("addne r2, r2, #4 ");
sl@0: 	asm("movs lr, ip, lsr #2 ");
sl@0: 	asm("movne ip, lr ");
sl@0: 	asm("addne r2, r2, #2 ");
sl@0: 	asm("movs lr, ip, lsr #1 ");
sl@0: 	asm("movne ip, lr ");
sl@0: 	asm("addne r2, r2, #1 ");				// r2 now = last occupied pde offset
sl@0: #endif
sl@0: 	asm("sub r3, r2, r1 ");					// r3=last-first
sl@0: 	asm("mov ip, r1 ");						// ip=first
sl@0: 	asm("add r1, r3, #1 ");					// r1 = number of pdes in range
sl@0: 	asm("ldmfd sp!, {r4,lr} ");
sl@0: 	asm("b scan_bitmap_end ");				// go back to set pde info
sl@0: 	}
sl@0: 
sl@0: __NAKED__ TBool Exc::IsMagic(TLinAddr /*anAddress*/)
sl@0: //
sl@0: // Return TRUE if anAddress is a 'magic' exception handling instruction
sl@0: //
sl@0: 	{
sl@0: 	asm("adr r1, __magic_addresses ");		// r1 points to list of magic addresses
sl@0: 	asm("is_magic_1: ");
sl@0: 	asm("ldr r2, [r1], #4 ");				// r2=next magic address to check
sl@0: 	asm("cmp r2, r0 ");						// is r0=magic address?
sl@0: 	asm("cmpne r2, #0 ");					// if not, have we reached end of list?
sl@0: 	asm("bne is_magic_1 ");					// if neither, check next address
sl@0: 	asm("movs r0, r2 ");					// r0=0 if not magic, r0 unchanged if magic
sl@0: 	__JUMP(,lr);
sl@0: 
sl@0: 	asm("__magic_addresses: ");
sl@0: 	asm(".word __magic_address_kusaferead ");
sl@0: 	asm(".word __magic_address_saferead ");
sl@0: 	asm(".word __magic_address_kusafewrite ");
sl@0: 	asm(".word __magic_address_safewrite ");
sl@0: 	asm(".word __magic_address_msg_lookup_1 ");			// in preprocess handler
sl@0: 	asm(".word __magic_address_readdesheader1 ");
sl@0: 	asm(".word __magic_address_readdesheader2 ");
sl@0: 	asm(".word __magic_address_readdesheader3 ");
sl@0: #ifdef __MESSAGE_MACHINE_CODED_2__
sl@0: 	asm(".word __magic_address_msg_lookup_2 ");
sl@0: #endif
sl@0: #ifdef __CLIENT_REQUEST_MACHINE_CODED__
sl@0: 	asm(".word __magic_address_client_request_callback");
sl@0: 	asm(".word __magic_address_svr_accept_1 ");
sl@0: 	asm(".word __magic_address_svr_accept_2 ");
sl@0: 	asm(".word __magic_address_svr_accept_3 ");
sl@0: 	asm(".word __magic_address_svr_accept_4 ");
sl@0: 	asm(".word __magic_address_svr_accept_5 ");
sl@0: 	asm(".word __magic_address_svr_accept_6 ");
sl@0: 	asm(".word __magic_address_svr_accept_7 ");
sl@0: 	asm(".word __magic_address_svr_accept_8 ");
sl@0: #endif
sl@0: #ifdef __REQUEST_COMPLETE_MACHINE_CODED__
sl@0: 	asm(".word __magic_address_reqc ");
sl@0: 	asm(".word __magic_address_kern_request_complete ");
sl@0: #endif
sl@0: 	// list terminator
sl@0: 	asm(".word 0 ");
sl@0: 	}
sl@0: 
sl@0: __NAKED__ TAny* MM::CurrentAddress(DThread* /*aThread*/, const TAny* /*aPtr*/, TInt /*aSize*/, TBool /*aWrite*/)
sl@0: //
sl@0: // Return the current base address corresponding to run address region
sl@0: // aPtr to aPtr+aBase-1 in the context of aThread.
sl@0: // aWrite indicates whether the address is intended for writing (aWrite=TRUE) or reading (aWrite=FALSE).
sl@0: // Return NULL if the address range is not all accessible to aThread for access type specified by aWrite.
sl@0: // aWrite=FALSE allows access to the ROM and RAM-loaded code chunks whereas aWrite=TRUE disallows these.
sl@0: // NOTE THIS FUNCTION CONTAINS KNOWLEDGE OF FIXED LINEAR ADDRESSES (the RAM drive and HIVECS area).
sl@0: //
sl@0: // ALLERT! the ip register returns a pointer to the chunk which contains the addresses (null if none)
sl@0: //
sl@0: 	{
sl@0: 	asm("CurrentAddress:");
sl@0: 	asm("ldr r0, [r0, #%a0]" : : "i" _FOFF(DThread, iOwningProcess));
sl@0: 	asm("stmfd sp!, {r4,r5,lr} ");
sl@0: 	asm("eor r4, r1, #0x40000000 ");		// r4<0x20000000u for RAM drive
sl@0: 	asm("cmp r4, #0x20000000 ");			// Check for RAM drive - ASSUMES RAM DRIVE IS AT 40000000-5FFFFFFF
sl@0: 	asm("ldr lr, [r0, #%a0]!" : : "i" _FOFF(DMemModelProcess, iNumChunks));		// step r0 on to iChunks[0]
sl@0: 	asm("bcc lookup_chunk_3 ");				// branch if RAM drive
sl@0: 	asm("subs lr, lr, #1 ");
sl@0: 	asm("bcc lookup_chunk_2 ");				// no chunks so do read check
sl@0: 	asm("lookup_chunk_1: ");
sl@0: 	asm("ldmib r0!, {r4,ip} ");				// r4=data section base, ip=chunk ptr
sl@0: 	asm("add r0, r0, #4 ");					// move to next entry
sl@0: 	asm("subs r4, r1, r4 ");				// r4=offset
sl@0: 	asm("ldrcs r5, [ip, #%a0]" : : "i" _FOFF(DChunk,iMaxSize));	// if offset>=0, r5=chunk max size
sl@0: 	asm("cmpcs r4, r5 ");					// and compare offset to max size
sl@0: 	asm("subcss lr, lr, #1 ");				// if offset>=max size, decrement counter
sl@0: 	asm("bcs lookup_chunk_1 ");				// loop if more chunks to check
sl@0: 	asm("cmp lr, #0 ");						// did we find chunk?
sl@0: 	asm("ldrge r0, [ip, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomeRegionOffset));
sl@0: 	asm("ldrge r5, [ip, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomeRegionSize));
sl@0: 	asm("ldrge lr, [ip, #%a0]" : : "i" _FOFF(DChunk,iBase));
sl@0: 	asm("cmpge r4, r0 ");					// if chunk not found or offset<iHomeRegionOffset, do read check
sl@0: 	asm("blt lookup_chunk_2 ");
sl@0: 	asm("add r0, r0, r5 ");					// r0=home region offset+home region size
sl@0: 	asm("add r5, r4, r2 ");					// r5=offset after end of block
sl@0: 	asm("cmp r5, r0 ");						// check if offset after end<=iHomeRegionOffset+iHomeRegionSize
sl@0: 	asm("addle r0, lr, r4 ");				// if so, r0=current chunk base + offset
sl@0: 	asm("ldmlefd sp!, {r4,r5,pc} ");		// and we are done
sl@0: 
sl@0: 	asm("lookup_chunk_2: ");				// come here if address not found in a chunk
sl@0: 	asm("mov ip, #0");						// ip = 0 to indicate chunk not found
sl@0: 	asm("ldr r4, __code_limit ");
sl@0: 	asm("mov r0, #0 ");
sl@0: 	asm("cmn r1, #0x00100000 ");			// address in hivecs area?
sl@0: 	asm("ldr r4, [r4] ");					// r4 = lowest legitimate code address
sl@0: 	asm("ldmcsfd sp!, {r4,r5,pc} ");		// if in hivecs, return NULL
sl@0: 	asm("cmp r3, #0 ");						// is this address intended for writing?
sl@0: 	asm("ldmnefd sp!, {r4,r5,pc} ");		// if it is, return NULL
sl@0: 	asm("cmp r1, r4 ");						// check if address is in RAM-loaded code or ROM
sl@0: 	asm("ldmccfd sp!, {r4,r5,pc} ");		// if not, return NULL
sl@0: 	asm("adds r4, r1, r2 ");				// r4 = end address of requested region
sl@0: 	asm("ldmcsfd sp!, {r4,r5,pc} ");		// if it wrapped, return NULL
sl@0: 	asm("cmn r4, #0x100000 ");				// if it didn't wrap, check if it reaches into hivecs area
sl@0: 	asm("movls r0, r1 ");					// if not, addr is OK for reading
sl@0: 	asm("ldmfd sp!, {r4,r5,pc} ");
sl@0: 
sl@0: 	asm("lookup_chunk_3: ");				// come here if address in RAM drive
sl@0: 	asm("mov ip, #0");						// ip = 0 to indicate chunk not found
sl@0: 	asm("ldr r3, __f32 ");					// r3=&K::TheFileServerProcess
sl@0: 	asm("sub r4, r0, #%a0" : : "i" _FOFF(DMemModelProcess, iNumChunks));	// r4=aThread->iOwningProcess
sl@0: 	asm("mov r0, #0 ");
sl@0: 	asm("ldr r3, [r3] ");					// r3=K::TheFileServerProcess
sl@0: 	asm("add r5, r1, r2 ");					// r5=end address of requested region + 1
sl@0: 	asm("cmp r5, #0x60000000 ");			// is this past the end of the RAM drive? ASSUMES ADDRESS OF RAM DRIVE
sl@0: 	asm("cmpls r3, r4 ");					// if not, is aThread part of F32?
sl@0: 	asm("moveq r0, r1 ");					// if it is, allow the access and return the address unaltered
sl@0: 	asm("ldmfd sp!, {r4,r5,pc} ");			// else return NULL
sl@0: 
sl@0: 	asm("__f32: ");
sl@0: 	asm(".word  " CSM_ZN1K20TheFileServerProcessE );
sl@0: 	asm("__code_limit: ");
sl@0: 	asm(".word %a0" : : "i" ((TInt)&::TheMmu.iUserCodeBase) );
sl@0: 	}
sl@0: