sl@0: // Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
sl@0: // All rights reserved.
sl@0: // This component and the accompanying materials are made available
sl@0: // under the terms of the License "Eclipse Public License v1.0"
sl@0: // which accompanies this distribution, and is available
sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
sl@0: //
sl@0: // Initial Contributors:
sl@0: // Nokia Corporation - initial contribution.
sl@0: //
sl@0: // Contributors:
sl@0: //
sl@0: // Description:
sl@0: // e32\include\nkern\x86\nk_plat.h
sl@0: // 
sl@0: // WARNING: This file contains some APIs which are internal and are subject
sl@0: //          to change without notice. Such APIs should therefore not be used
sl@0: //          outside the Kernel and Hardware Services package.
sl@0: //
sl@0: 
sl@0: /**
sl@0:  @file
sl@0:  @internalComponent
sl@0: */
sl@0: 
sl@0: #ifndef __NK_X86_H__
sl@0: #define __NK_X86_H__
sl@0: #include <nk_cpu.h>
sl@0: 
sl@0: #define IRQ_STACK_SIZE	1024
sl@0: 
sl@0: //#define __SCHEDULER_MACHINE_CODED__
sl@0: //#define __DFC_MACHINE_CODED__
sl@0: //#define __MSTIM_MACHINE_CODED__
sl@0: //#define __PRI_LIST_MACHINE_CODED__
sl@0: //#define __FAST_SEM_MACHINE_CODED__
sl@0: //#define __FAST_MUTEX_MACHINE_CODED__
sl@0: 
sl@0: // TScheduler member data
sl@0: #define	i_ExcInfo			iExtras[15]		// pointer to exception info for crash debugger
sl@0: 
sl@0: class TX86RegSet;
sl@0: class NThread : public NThreadBase
sl@0: 	{
sl@0: public:
sl@0: 	TInt Create(SNThreadCreateInfo& anInfo, TBool aInitial);
sl@0: 	inline void Stillborn()
sl@0: 		{}
sl@0: 	void GetUserContext(TX86RegSet& aContext);
sl@0: 	void ModifyUsp(TLinAddr aUsp);
sl@0: public:
sl@0: 	TUint32	i_NThread_Pad1;
sl@0: 	TUint64	iCoprocessorState[64];	// state of FPU, SSE, SSE2
sl@0: 	};
sl@0: 
sl@0: __ASSERT_COMPILE(!(_FOFF(NThread,iCoprocessorState)&7));
sl@0: 
sl@0: // Positions of registers on stack, relative to saved SP
sl@0: struct SThreadStack
sl@0: 	{
sl@0: 	TUint32 iCR0;
sl@0: 	TUint32 iEbx;
sl@0: 	TUint32 iEsi;
sl@0: 	TUint32 iEdi;
sl@0: 	TUint32 iEbp;
sl@0: 	TUint32 iGs;
sl@0: 	TUint32 iFs;
sl@0: 	TUint32 iReschedFlag;
sl@0: 	TUint32 iEip;
sl@0: 	};
sl@0: 
sl@0: extern "C" {
sl@0: GLREF_D TUint32 X86_IrqStack[IRQ_STACK_SIZE/4];
sl@0: GLREF_D TLinAddr X86_IrqHandler;
sl@0: GLREF_D TInt X86_IrqNestCount;
sl@0: GLREF_D SCpuIdleHandler CpuIdleHandler;
sl@0: GLREF_D TBool X86_UseGlobalPTEs;
sl@0: GLREF_D TUint64 DefaultCoprocessorState[64];
sl@0: }
sl@0: 
sl@0: 
sl@0: /** Ensure the ordering of explicit memory writes
sl@0: 
sl@0: 	On x86 this is a no-op
sl@0: */
sl@0: #define	wmb()
sl@0: #define smp_wmb()
sl@0: 
sl@0: /** Ensure the ordering of explicit memory accesses
sl@0: 
sl@0: 	On x86 any instruction with the LOCK prefix does this
sl@0: */
sl@0: #ifdef __GCC32__
sl@0: #define	mb()	__asm__ __volatile__("lock add dword ptr [esp], 0" : : : "memory")
sl@0: #else
sl@0: #define	mb()	do { _asm lock add dword ptr [esp], 0 } while (0)
sl@0: #endif
sl@0: #define smp_mb()
sl@0: 
sl@0: // End of file
sl@0: #endif