sl@0: // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
sl@0: // All rights reserved.
sl@0: // This component and the accompanying materials are made available
sl@0: // under the terms of the License "Eclipse Public License v1.0"
sl@0: // which accompanies this distribution, and is available
sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
sl@0: //
sl@0: // Initial Contributors:
sl@0: // Nokia Corporation - initial contribution.
sl@0: //
sl@0: // Contributors:
sl@0: //
sl@0: // Description:
sl@0: // e32/include/nkern/arm/entry.h
sl@0: // 
sl@0: //
sl@0: 
sl@0: extern "C" {
sl@0: 
sl@0: extern void __ArmVectorReset();
sl@0: extern void __ArmVectorUndef();
sl@0: extern void __ArmVectorSwi();
sl@0: extern void __ArmVectorAbortPrefetch();
sl@0: extern void __ArmVectorAbortData();
sl@0: extern void __ArmVectorReserved();
sl@0: extern void __ArmVectorIrq();
sl@0: extern void __ArmVectorFiq();
sl@0: 
sl@0: #define __DECLARE_UNDEFINED_INSTRUCTION_HANDLER		asm(".word __ArmVectorUndef ")
sl@0: #define __DECLARE_PREFETCH_ABORT_HANDLER			asm(".word __ArmVectorAbortPrefetch ")
sl@0: #define __DECLARE_DATA_ABORT_HANDLER				asm(".word __ArmVectorAbortData ")
sl@0: 
sl@0: /* NOTE: We must ensure that this code goes at the beginning of the kernel image.
sl@0: */
sl@0: __NAKED__ void __this_must_go_at_the_beginning_of_the_kernel_image()
sl@0: 	{
sl@0: 	asm("ldr	pc, __reset_vector ");		// 00 = Reset vector
sl@0: 	asm("ldr	pc, __undef_vector ");		// 04 = Undefined instruction vector
sl@0: 	asm("ldr	pc, __swi_vector ");		// 08 = SWI vector
sl@0: 	asm("ldr	pc, __pabt_vector ");		// 0C = Prefetch abort vector
sl@0: 	asm("ldr	pc, __dabt_vector ");		// 10 = Data abort vector
sl@0: 	asm("ldr	pc, __unused_vector ");		// 14 = unused
sl@0: 	asm("b		HandleIrq ");				// 18 = IRQ vector
sl@0: 											// 1C = FIQ vector, code in situ
sl@0: 	asm("ldr r12, __ArmInterrupt ");	// THIS MUST BE AN IDEMPOTENT INSTRUCTION TO AVOID A PROBLEM WITH XSCALE PXA255
sl@0: 	asm("sub lr, lr, #4 ");
sl@0: 	asm("str lr, [sp, #-4]! ");
sl@0: 	// we assume FIQ handler preserves r0-r7 but not r8-r12
sl@0: 	// hence must be assembler, so stack misalignment OK
sl@0: #if defined(__CPU_ARM_HAS_WORKING_CLREX)
sl@0: 	CLREX
sl@0: #elif defined(__CPU_ARM_HAS_LDREX_STREX)
sl@0: 	STREX(8,14, 13);		// dummy STREX to reset exclusivity monitor
sl@0: #endif
sl@0: #ifdef __USER_MEMORY_GUARDS_ENABLED__
sl@0: 	USER_MEMORY_GUARD_ON(,lr,r8);
sl@0: 	asm("str lr, [sp, #-4]! ");
sl@0: #endif
sl@0: #ifdef BTRACE_CPU_USAGE
sl@0: 	asm("ldrb r8, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iCpuUsageFilter));
sl@0: 	asm("ldr lr, _ArmVectorFiq ");
sl@0: 	asm("mov r10, #%a0" : : "i" ((TInt)(BTrace::ECpuUsage<<BTrace::ECategoryIndex*8)+(BTrace::EFiqStart<<BTrace::ESubCategoryIndex*8)) );
sl@0: 	asm("cmp r8,#0");
sl@0: 	asm("bne btrace_fiq");
sl@0: 	asm("ldr pc, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iFiqHandler)); // call FIQ handler, return to ArmVectorFiq
sl@0: 
sl@0: 	asm("btrace_fiq:");		// call trace handler before fiq handler...
sl@0: 	asm("stmdb sp!, {r0-r3} ");
sl@0: 	asm("add r0, r10, #%a0" : : "i" ((TInt)4) ); // add size of trace into header
sl@0: 	asm("mov lr, pc");
sl@0: 	asm("ldr pc, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iBTraceHandler));
sl@0: 	asm("ldr r12, __ArmInterrupt ");
sl@0: 	asm("ldmia sp!, {r0-r3} ");
sl@0: #endif	
sl@0: 	asm("ldr lr, _ArmVectorFiq ");
sl@0: 	asm("ldr pc, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iFiqHandler)); // call FIQ handler, return to ArmVectorFiq
sl@0: 
sl@0: 	asm("HandleIrq: ");
sl@0: 	asm("sub lr, lr, #4 ");
sl@0: 	asm("stmfd sp!, {r0-r3,r12,lr} ");
sl@0: #if defined(__CPU_ARM_HAS_WORKING_CLREX)
sl@0: 	CLREX
sl@0: #elif defined(__CPU_ARM_HAS_LDREX_STREX)
sl@0: 	STREX(12, 0, 13);	// dummy STREX to reset exclusivity monitor
sl@0: #endif
sl@0: #ifdef __USER_MEMORY_GUARDS_ENABLED__
sl@0: 	USER_MEMORY_GUARD_ON(,lr,r12);
sl@0: 	asm("str lr, [sp, #-8]! ");
sl@0: #endif
sl@0: 	asm("ldr r12, __ArmInterrupt ");
sl@0: #ifdef BTRACE_CPU_USAGE
sl@0: 	asm("mov r0, #%a0" : : "i" ((TInt)(BTrace::ECpuUsage<<BTrace::ECategoryIndex*8)+(BTrace::EIrqStart<<BTrace::ESubCategoryIndex*8)) );
sl@0: 	asm("add r0, r0, #%a0" : : "i" ((TInt)4) ); // add size of trace into header
sl@0: 	asm("ldrb r1, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iCpuUsageFilter));
sl@0: 	asm("ldr lr, _ArmVectorIrq ");
sl@0: 	asm("cmp r1,#0");
sl@0: 	asm("bne btrace_irq");
sl@0: 	asm("ldr pc, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iIrqHandler));  // call IRQ handler, return to ArmVectorIrq
sl@0: 
sl@0: 	asm("btrace_irq:");	// call trace handler before irq handler...
sl@0: 	asm("mov lr, pc");
sl@0: 	asm("ldr pc, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iBTraceHandler));
sl@0: 	asm("ldr r12, __ArmInterrupt ");
sl@0: #endif
sl@0: 	asm("ldr lr, _ArmVectorIrq ");
sl@0: 	asm("ldr pc, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iIrqHandler)); // call IRQ handler, return to ArmVectorIrq
sl@0: 
sl@0: 	asm("__reset_vector:");
sl@0: 	asm(".word	__ArmVectorReset "); 
sl@0: 	asm("__undef_vector:");
sl@0: 	__DECLARE_UNDEFINED_INSTRUCTION_HANDLER;
sl@0: 	asm("__swi_vector:");
sl@0: 	asm(".word	__ArmVectorSwi "); 
sl@0: 	asm("__pabt_vector:");
sl@0: 	__DECLARE_PREFETCH_ABORT_HANDLER;
sl@0: 	asm("__dabt_vector:");
sl@0: 	__DECLARE_DATA_ABORT_HANDLER;
sl@0: 	asm("__unused_vector:");
sl@0: 	asm(".word	__ArmVectorReserved ");
sl@0: 
sl@0: 	asm("__ArmInterrupt: ");
sl@0: 	asm(".word  ArmInterruptInfo ");
sl@0: 	asm("_ArmVectorIrq:");
sl@0: 	asm(".word __ArmVectorIrq"); 
sl@0: 	asm("_ArmVectorFiq:");
sl@0: 	asm(".word __ArmVectorFiq ");
sl@0: 	}
sl@0: }
sl@0: