sl@0: // Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
sl@0: // All rights reserved.
sl@0: // This component and the accompanying materials are made available
sl@0: // under the terms of the License "Eclipse Public License v1.0"
sl@0: // which accompanies this distribution, and is available
sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
sl@0: //
sl@0: // Initial Contributors:
sl@0: // Nokia Corporation - initial contribution.
sl@0: //
sl@0: // Contributors:
sl@0: //
sl@0: // Description:
sl@0: // e32\include\memmodel\epoc\multiple\x86\mmboot.h
sl@0: // 
sl@0: //
sl@0: 
sl@0: /**
sl@0:  @file
sl@0:  @publishedPartner
sl@0:  @released
sl@0: */
sl@0: 
sl@0: #ifndef __MMBOOT_H__
sl@0: #define __MMBOOT_H__
sl@0: #include <x86.h>
sl@0: #include <memmodel.h>
sl@0: #include <kernel/cache.h>
sl@0: 
sl@0: //
sl@0: // Linear address map:
sl@0: // 00000000-003FFFFF	Unmapped except for AP boot page at 7F000
sl@0: // 00400000-37FFFFFF	Local data
sl@0: // 38000000-3FFFFFFF	DLL static data (=phys ram size/2 up to 128M)
sl@0: // 40000000-6FFFFFFF	Shared data
sl@0: // 70000000-7FFFFFFF	RAM loaded code (=phys ram size up to 256M)
sl@0: // 80000000-8FFFFFFF	ROM
sl@0: // 90000000-9FFFFFFF	User Global Area
sl@0: // A0000000-BFFFFFFF	RAM drive
sl@0: // C0000000-C0001FFF	Super page/CPU page (extends to C0005FFF for SMP)
sl@0: // C0006000-C0006FFF	Trampoline page for SMP
sl@0: // C0030000-C00303FF	KPageInfoMap
sl@0: // C0040000-C004FFFF	ASID info
sl@0: // C0080000-C00FFFFF	Page table info	
sl@0: // C1000000-C1FFFFFF	Page directories
sl@0: // C2000000-C5FFFFFF	Page tables
sl@0: // C6000000-C6FFFFFF	Primary I/O mappings
sl@0: // C7000000-C7FFFFFF
sl@0: // C8000000-C8FFFFFF	Kernel .data/.bss, initial stack, kernel heap
sl@0: // C9000000-C93FFFFF	Kernel stacks
sl@0: // C9400000-F9FFFFFF	Extra kernel mappings (I/O, RAM loaded device drivers)
sl@0: // FA000000-FA3FFFFF	IPC Alias for CPU 0
sl@0: // FA400000-FA7FFFFF	IPC Alias for CPU 1 (SMP only)
sl@0: // FA800000-FABFFFFF	IPC Alias for CPU 2 (SMP only)
sl@0: // FAC00000-FAFFFFFF	IPC Alias for CPU 3 (SMP only)
sl@0: // FB000000-FB3FFFFF	IPC Alias for CPU 4 (SMP only)
sl@0: // FB400000-FB7FFFFF	IPC Alias for CPU 5 (SMP only)
sl@0: // FB800000-FBBFFFFF	IPC Alias for CPU 6 (SMP only)
sl@0: // FBC00000-FBFFFFFF	IPC Alias for CPU 7 (SMP only)
sl@0: // FC000000-FDFFFFFF	Page Info array
sl@0: // FE000000-FEBFFFFF	Unused
sl@0: // FEC00000-FEFFFFFF	IO APIC + Local APIC
sl@0: // FF000000-FFFFFFFF	Unused
sl@0: 
sl@0: // Linear addresses
sl@0: const TLinAddr KUserLocalDataBase	=0x00400000u;
sl@0: const TLinAddr KUserSharedDataBase	=0x40000000u;
sl@0: const TLinAddr KUserSharedDataEnd	=0x80000000u;	// after code
sl@0: const TLinAddr KRomLinearBase		=0x80000000u;
sl@0: const TLinAddr KRomLinearEnd		=0x90000000u;
sl@0: const TLinAddr KUserGlobalDataBase	=0x90000000u;
sl@0: const TLinAddr KUserGlobalDataEnd	=0xA0000000u;
sl@0: const TLinAddr KRamDriveStartAddress=0xA0000000u;
sl@0: const TInt KRamDriveMaxSize=0x20000000;
sl@0: const TLinAddr KRamDriveEndAddress	=0xC0000000u;
sl@0: const TLinAddr KSuperPageLinAddr	=0xC0000000u;
sl@0: const TLinAddr KPageInfoMap			=0xC0030000u;
sl@0: const TLinAddr KAsidInfoBase		=0xC0040000u;
sl@0: const TLinAddr KPageTableInfoBase	=0xC0080000u;
sl@0: const TLinAddr KPageDirectoryBase	=0xC1000000u;
sl@0: const TLinAddr KPageTableBase		=0xC2000000u;
sl@0: const TLinAddr KPrimaryIOBase		=0xC6000000u;
sl@0: const TLinAddr KKernelSectionEnd	=0xFA000000u;
sl@0: const TLinAddr KIPCAlias			=0xFA000000u;	// for SMP 4MB for each CPU
sl@0: 													// Thus CPU0->FC0, CPU1->FC4, ..., CPU7->FDC
sl@0: const TUint32  KIPCAliasAreaSize	=0x02000000u;	// total size of alias area
sl@0: const TLinAddr KPageInfoLinearBase	=0xFC000000u;
sl@0: 
sl@0: const TLinAddr KMachineConfigLinAddr=0xC0000800u;
sl@0: const TLinAddr KTempAddr=0xC0010000u;
sl@0: const TLinAddr KSecondTempAddr=0xC0014000u;
sl@0: const TLinAddr KDefragAltStackAddr=0xC001F000u;
sl@0: const TLinAddr KApTrampolinePageLin	=0xC0006000u;
sl@0: const TLinAddr KBiosInfoLin			=0xC0100000u;	// RAM info + MP info
sl@0: 
sl@0: // Constants for X86 MMU
sl@0: const TInt KChunkShift=22;
sl@0: const TInt KChunkSize=1<<KChunkShift;
sl@0: const TInt KChunkMask=KChunkSize-1;
sl@0: const TInt KPageTableShift=KChunkShift-12+2;	// PTE is 4 bytes
sl@0: const TInt KPageTableSize=1<<KPageTableShift;
sl@0: const TInt KPageTableMask=KPageTableSize-1;
sl@0: const TInt KPtClusterShift=12-KPageTableShift;
sl@0: const TInt KPtClusterSize=1<<KPtClusterShift;
sl@0: const TInt KPtClusterMask=KPtClusterSize-1;
sl@0: const TInt KPtBlockShift=12-3;					/**< @internalTechnology */	// sizeof(SPageTableInfo)=8
sl@0: const TInt KPtBlockSize=1<<KPtBlockShift;		/**< @internalTechnology */
sl@0: const TInt KPtBlockMask=KPtBlockSize-1;			/**< @internalTechnology */
sl@0: const TInt KPagesInPDEShift=KChunkShift-12;
sl@0: const TInt KPagesInPDE=1<<KPagesInPDEShift;
sl@0: const TInt KPagesInPDEMask=KPagesInPDE-1;
sl@0: 
sl@0: 
sl@0: const TInt KPageInfoShift = 5;
sl@0: 
sl@0: #endif	// __MMBOOT_H__