sl@0: // Copyright (c) 1996-2009 Nokia Corporation and/or its subsidiary(-ies).
sl@0: // All rights reserved.
sl@0: // This component and the accompanying materials are made available
sl@0: // under the terms of the License "Eclipse Public License v1.0"
sl@0: // which accompanies this distribution, and is available
sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
sl@0: //
sl@0: // Initial Contributors:
sl@0: // Nokia Corporation - initial contribution.
sl@0: //
sl@0: // Contributors:
sl@0: //
sl@0: // Description:
sl@0: // e32\include\drivers\uart16550.h
sl@0: // 
sl@0: //
sl@0: 
sl@0: /**
sl@0:  @file
sl@0:  @internalTechnology
sl@0: */
sl@0: 
sl@0: #ifndef __UART16550_H__
sl@0: #define __UART16550_H__
sl@0: #include <e32def.h>
sl@0: 
sl@0: //								 
sl@0: // Register Definitions for 16550-type UARTs
sl@0: //
sl@0: 
sl@0: const TUint8 K16550TXHROffset=0<<K16550OffsetShift;			// Transmit Holding Register
sl@0: const TUint8 K16550RXHROffset=0<<K16550OffsetShift;			// Receive Holding Register
sl@0: const TUint8 K16550BDLoOffset=0<<K16550OffsetShift;			// Baud Rate Divisor Low
sl@0: const TUint8 K16550IEROffset=1<<K16550OffsetShift;			// Interrupt Enable Register
sl@0: const TUint8 K16550BDHiOffset=1<<K16550OffsetShift;			// Baud Rate Divisor High
sl@0: const TUint8 K16550ISROffset=2<<K16550OffsetShift;			// Interrupt Status Register
sl@0: const TUint8 K16550FCROffset=2<<K16550OffsetShift;			// FIFO Control Register
sl@0: const TUint8 K16550LCROffset=3<<K16550OffsetShift;			// Line Control Register
sl@0: const TUint8 K16550MCROffset=4<<K16550OffsetShift;			// Modem Control Register
sl@0: const TUint8 K16550LSROffset=5<<K16550OffsetShift;			// Line Status Register
sl@0: const TUint8 K16550MSROffset=6<<K16550OffsetShift;			// Modem Status Register
sl@0: const TUint8 K16550ScratchpadOffset=7<<K16550OffsetShift;	// Scratchpad Register
sl@0: 
sl@0: // Interrupt Enable Register
sl@0: 
sl@0: const TUint8 K16550IER_RDAI=1;				// Received Data Available
sl@0: const TUint8 K16550IER_THREI=2;				// Transmit Holding Register Empty
sl@0: const TUint8 K16550IER_RLSI=4;				// Receive Line Status (error or break)
sl@0: const TUint8 K16550IER_MSI=8;				// Modem Status
sl@0: 
sl@0: // Interrupt Status Register
sl@0: 
sl@0: const TUint8 K16550ISR_NotPending=1;		// Not Interrupt Pending
sl@0: const TUint8 K16550ISR_IntIdMask=6;			// Mask for Interrupt Identification
sl@0: const TUint8 K16550ISR_RDAI=4;				// Received Data Available
sl@0: const TUint8 K16550ISR_THREI=2;				// Transmit Holding Register Empty
sl@0: const TUint8 K16550ISR_RLSI=6;				// Receive Line Status
sl@0: const TUint8 K16550ISR_MSI=0;				// Modem Status
sl@0: const TUint8 K16550ISR_RxTimeout=8;			// Set if FIFO timeout (in conjunction with RDA)
sl@0: 
sl@0: // FIFO control Register
sl@0: 
sl@0: const TUint8 K16550FCR_Enable=1;			// Enable TX and RX FIFOs
sl@0: const TUint8 K16550FCR_RxReset=2;			// Reset RX FIFO (self-clearing)
sl@0: const TUint8 K16550FCR_TxReset=4;			// Reset TX FIFO (self-clearing)
sl@0: const TUint8 K16550FCR_TxRxRdy=8;			//
sl@0: const TUint8 K16550FCR_RxTrig1=0;			// RX FIFO triggers when >=1 char received
sl@0: const TUint8 K16550FCR_RxTrig4=64;			// RX FIFO triggers when >=4 chars received
sl@0: const TUint8 K16550FCR_RxTrig8=128;			// RX FIFO triggers when >=8 chars received
sl@0: const TUint8 K16550FCR_RxTrig14=192;		// RX FIFO triggers when >=14 chars received
sl@0: 
sl@0: // Line Control Register
sl@0: 
sl@0: const TUint8 K16550LCR_Data5=0;				// 5 bit characters
sl@0: const TUint8 K16550LCR_Data6=1;				// 6 bit characters
sl@0: const TUint8 K16550LCR_Data7=2;				// 7 bit characters
sl@0: const TUint8 K16550LCR_Data8=3;				// 8 bit characters
sl@0: const TUint8 K16550LCR_Stop1=0;				// 1 stop bit
sl@0: const TUint8 K16550LCR_Stop2=4;				// 2 stop bits
sl@0: const TUint8 K16550LCR_ParityEnable=8;		// Use parity
sl@0: const TUint8 K16550LCR_ParityEven=16;		// Use even parity
sl@0: const TUint8 K16550LCR_ParityMark=40;		// Use mark parity
sl@0: const TUint8 K16550LCR_ParitySpace=56;		// Use space parity
sl@0: const TUint8 K16550LCR_TxBreak=64;			// Transmit a break
sl@0: const TUint8 K16550LCR_DLAB=128;			// Divisor Latch Access
sl@0: 
sl@0: // Modem Control Register
sl@0: 
sl@0: const TUint8 K16550MCR_DTR=1;
sl@0: const TUint8 K16550MCR_RTS=2;
sl@0: const TUint8 K16550MCR_OUT1=4;
sl@0: const TUint8 K16550MCR_OUT2=8;
sl@0: const TUint8 K16550MCR_LocalLoop=16;
sl@0: 
sl@0: // Line Status Register
sl@0: 
sl@0: const TUint8 K16550LSR_RxReady=1;			// Received data ready
sl@0: const TUint8 K16550LSR_RxOverrun=2;			// Receiver overrun
sl@0: const TUint8 K16550LSR_RxParityErr=4;		// Receiver parity error
sl@0: const TUint8 K16550LSR_RxFrameErr=8;		// Receiver framing error
sl@0: const TUint8 K16550LSR_RxBreak=16;			// Receive break detect
sl@0: const TUint8 K16550LSR_TXHREmpty=32;		// Transmit Holding Register Empty (FIFO empty)
sl@0: const TUint8 K16550LSR_TxIdle=64;			// Transmitter Idle
sl@0: const TUint8 K16550LSR_RxErrPending=128;	// FIFO contains an error or break indication
sl@0: 
sl@0: // Modem Status Register
sl@0: 
sl@0: const TUint8 K16550MSR_DeltaCTS=1;
sl@0: const TUint8 K16550MSR_DeltaDSR=2;
sl@0: const TUint8 K16550MSR_TERI=4;
sl@0: const TUint8 K16550MSR_DeltaDCD=8;
sl@0: const TUint8 K16550MSR_CTS=16;
sl@0: const TUint8 K16550MSR_DSR=32;
sl@0: const TUint8 K16550MSR_RI=64;
sl@0: const TUint8 K16550MSR_DCD=128;
sl@0: 
sl@0: // Wrapper class
sl@0: 
sl@0: class T16550Uart
sl@0: 	{
sl@0: public:
sl@0: 	void ModifyFCR(TUint aClearMask, TUint aSetMask);
sl@0: 	void ModifyLCR(TUint aClearMask, TUint aSetMask);
sl@0: 	void ModifyMCR(TUint aClearMask, TUint aSetMask);
sl@0: 	void ModifyIER(TUint aClearMask, TUint aSetMask);
sl@0: 	void SetFCR(TUint aValue);
sl@0: 	void SetLCR(TUint aValue);
sl@0: 	void SetMCR(TUint aValue);
sl@0: 	void SetIER(TUint aValue);
sl@0: 	inline TUint FCR()
sl@0: 		{return iFCR;}
sl@0: 	inline TUint LCR()
sl@0: 		{return iLCR;}
sl@0: 	inline TUint MCR()
sl@0: 		{return iMCR;}
sl@0: 	inline TUint IER()
sl@0: 		{return iIER;}
sl@0: 	inline void SetTxData(TUint aData)
sl@0: 		{iBase[K16550TXHROffset]=(TUint8)aData;}
sl@0: 	inline TUint RxData()
sl@0: 		{return iBase[K16550RXHROffset];}
sl@0: 	inline TUint ISR()
sl@0: 		{return iBase[K16550ISROffset];}
sl@0: 	inline TUint LSR()
sl@0: 		{return iBase[K16550LSROffset];}
sl@0: 	inline TUint MSR()
sl@0: 		{return iBase[K16550MSROffset];}
sl@0: 	inline TUint TestISR(TUint aMask)
sl@0: 		{return iBase[K16550ISROffset]&aMask;}
sl@0: 	inline TUint TestLSR(TUint aMask)
sl@0: 		{return iBase[K16550LSROffset]&aMask;}
sl@0: 	inline TUint TestMSR(TUint aMask)
sl@0: 		{return iBase[K16550MSROffset]&aMask;}
sl@0: 	inline void SetScratch(TUint aValue)
sl@0: 		{iBase[K16550ScratchpadOffset]=(TUint8)aValue;}
sl@0: 	inline TUint Scratch()
sl@0: 		{return iBase[K16550ScratchpadOffset];}
sl@0: 	inline void SetBaudRateDivisor(TUint aValue)
sl@0: 		{iBase[K16550BDHiOffset]=(TUint8)(aValue>>8); iBase[K16550BDLoOffset]=(TUint8)aValue;}
sl@0: public:
sl@0: 	volatile TUint8* iBase;					// base address
sl@0: 	TUint8 iFCR;							// FCR follower
sl@0: 	TUint8 iLCR;							// LCR follower
sl@0: 	TUint8 iMCR;							// MCR follower
sl@0: 	TUint8 iIER;							// IER follower
sl@0: 	};
sl@0: 
sl@0: 
sl@0: #endif
sl@0: 
sl@0: